Xilinx Virtex-4 RocketIO User manual

R
Virtex-4 RocketIO
Multi-Gigabit
Transceiver
User Guide
UG076 (v4.1) November 2, 2008

Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008
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UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide
Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/05 1.0 Xilinx Initial Release.
03/10/05 1.1 Modified “Power Supply Requirements” in Chapter 6 and Table 6-1, page 176.
04/07/05 1.2 General typographical edits. Revised Table 2-2, Table 2-8, Figure 2-7, Figure 2-8,
Figure 2-11, Figure 2-12, Figure 6-4, Figure 6-8, and Figure E-2. Added “Resetting the
Transceiver,” page 85 and Figure 2-12. Edited Table 4-1, Table 4-3, Table 4-5, Table 7-3,
Table 7-4, Table 7-5, Table 7-6, Table A-1, Table C-14, and Table C-28.
07/01/05 1.3 Changes in Figure 2-4, Figure 2-9, Figure 3-14, Figure 4-9, Figure 6-4 and Figure 6-8.
Revised Table 3-23 and Table 3-24. Added Table 5-5, revised Table 5-5. Changes to
Table 7-4, Table 7-5, Table 7-6. For clarity, revised all the notes in the tables in
Appendix C. Added a default value to DCDR_FILTER in Appendix F.
01/16/06 2.0 Major revision. All material completely revised and updated, substantial new material
added.
05/23/06 3.0 Major revision. Chapter 1: All Ports/Attributes tables reviewed and expanded. Chapter
2: New Reset section. Low-latency material removed. Chapter 8: New. Chapters 9-12
(Section II): New.
07/19/06 3.1 •Table 1-3: Corrected maximum reference clock frequency to 644 MHz for Aurora
protocols.
•Table 1-11: Deleted instruction to set TXTERMTRIM to 0000.
•Chapter 2, section “Resetting the Transceiver”:
♦Modified all references to LOCKUPDATE cycles to REFCLK cycles.
♦Corrected state definitions in all flowcharts.
•Chapter 3, section “Channel Bonding”: Rewritten and enlarged.
•Chapter 8, section “RXSYNC”:
♦Modified all references to LOCKUPDATE cycles to REFCLK cycles.
•Table C-6 and Table C-19: Corrected TXTERMTRIM default state to 1100.
09/29/06 3.2 •Removed references to the FF1760 package. Not supported.
•Removed references to 1-byte and 2-byte external fabric widths for PCS Bypass mode.
Not supported.
•Removed references to OC-48 protocol. Not supported.
•Removed references to Digital ReceiverLoopback. Not supported.
•Removed former Tables 4-6, 4-7, and Figure 4-12 from section “Out-of-Band (OOB)
Signals.”
•Added RX/TXFDCAL_CLOCK_DIVIDE setting of FOUR for RX/TX calibration with
reference clock speeds over 500 MHz (Table 4-4, Table 4-5).
•Added in several places throughout the Guide the recommendation to use the
RocketIO Wizard for MGT configuration.
•Added several new sections and diagrams to Chapter 6, “Analog and Board Design
Considerations” relating to powering MGTs. Existing material edited and updated.
•Added new section “SelectIO-to-MGT Crosstalk”to Chapter 6, “Analog and Board
Design Considerations.”
•Added Appendix D, “Special Analog Functions.” Previously part of Chapter 4.

Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008
08/17/07 4.0 Major revision. All material completely revised and updated.
•General typographical edits.
•Added no data encoding and NRZ signaling to “MGT Features.”
•Removed 64B/66B encoding from Preface, Chapter 1, Chapter 2, Chapter 3,
Chapter 4, Chapter 6, Chapter 7, and Appendix E.
•Removed Decision Feedback Equalizer (DFE) from Preface and Chapter 4.
•Changed ring buffer size to 13x64 in Figure 2-7, Figure 3-2, Figure 8-1, and Figure 8-16
to Figure 8-21.
Chapter 1:
•Added notes to Figure 1-1.
•In Table 1-3; modified reference clock frequency values, added notes 2 through 5,
added new Aurora Transmit and Receive rows. Removed 64B/66B, OIF SxI-5, OIF SFI
4.2, and Aurora 64B/66B protocols.
•Rewrote text before Table 1-4.
•Modified port definitions in Table 1-5.
•Modified port definitions and end note in Table 1-6.
•Modified attribute descriptions, and added RXCMADJ, POWER_ENABLE,
RXCPSEL, and TXCPSEL attributes in Table 1-11.
•Modified attribute descriptions and added end note after Table 1-12 and Table 1-13.
Chapter 2:
•Added note to Figure 2-1.
•Modified description of SYNCLK1IN and SYNCLK2IN, and added I/O column to
Table 2-1.
•Removed support of RXPCSHCLKOUT, TXPCSHCLKOUT, and RXMCLK in
Table 2-2.
•Modified notes before Figure 2-4, Figure 2-5 and Figure 2-9.
•Modified notes in Figure 2-4 and Figure 2-5.
•Added Table 2-5 and Table 2-7.
•Added “RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency.”
•Modified label in and added note to Figure 2-7.
•Added note to Figure 2-8.
•Modified labels in Figure 2-9.
•Modified Figure 2-11.
•Removed 64B/66B Scrambler/Descrambler and 10G BASE R
Gearbox/Decode/Block Sync from “TXRESET” and “RXRESET.”
•Modified last step in “Receive Reset Sequence: RX Buffer Bypassed.”
Chapter 3:
•Added note to Figure 3-1.
•Modified label in and added note to Figure 3-2.
•Modified overflow and underflow labels in Figure 3-3 and Figure 3-4.
•Relocated “RX Fabric Interface and Channel Bonding.”
•Modified text in “8B/10B Encoding/Decoding.”
•Modified text in paragraph before Figure 3-4.
•Removed 64B/66B from Table 3-4.
•Removed PCS_BIT_SLIP from “Symbol Alignment and Detection (Comma
Detection).”
Date Version Revision

UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide
08/17/07
(cont’d)
4.0
(cont’d)
•Modified “10-Bit Alignment for 8B/10B Encoded Data.”
•Expanded SONET alignment sequence figure into Figure 3-15 and Figure 3-16.
•Removed support of RXSYNC functionality in “RXSLIDE.”
•Modified Figure 3-18.
•Modified last paragraph of “Clock Correction Sequences.”
•Removed RXBLOCKSYNC64B66BUSE column, last two rows (64B/66B), and note
from Table 3-14.
•Modified Figure 3-24.
•Modified nominal frequency and period in text following Table 3-25.
•Removed Clocking in Buffer Bypass Mode section from Chapter 3.
•Removed Buffer Bypass Mode column from Table 3-26.
Chapter 4:
•Modified attribute definitions in Table 4-1.
•Removed description of TXUSRCLK from “Clock and Data Recovery.”
•Corrected references to RXAFEEQ in Figure 4-8.
•Removed description of MGT from “POWERDOWN.”
Chapter 5:
•Added description of CRC wakeup in “Latency and Timing.”
Chapter 6:
•Modified Figure 6-1 and Figure 6-4.
•Corrected equation references in “Determining Power Supply Budget.”
•Added additional bullet item to “Powering Unused MGTs.”
•Modified text in “Reference Clock” and Figure 6-7.
Chapter 7:
•Added “Reference Clock Period Restriction.”
•Rewrote description of TXENOOB and RXSIGDET in “Out-of-Band (OOB)
Signaling.”
•Deleted TXENOOB and RXSIGDET, and added RXSYNC to “MGT Ports that Cannot
Be Simulated.”
Chapter 8:
•Modified note 2 after Table 8-1.
•Changed port name to RXBLOCKSYNC64B66BUSE in Table 8-3, Table 8-11, and
Table 8-12.
•Added notes to say that 64B/66B encoding/decoding is not supported in Figure 8-1,
Figure 8-2, Figure 8-4 to Figure 8-11, Figure 8-13, Figure 8-14, Figure 8-16 to
Figure 8-21, Table 8-1 to Table 8-9, Table 8-13 to Table 8-17.
•Added item 5 to “Usage.”
Chapter 9:
•Expanded description in “Clock Traces.”
Chapter 10:
•Rewrote “Optimal Cable Length.”
Appendix A:
•Removed 64B/66B from and modified descriptions of TXOUTCLK1/2 and
RXRECCLK1/2 in Table A-1.
•Added notes to Figure A-1, Table A-6, and Table A-7.
Date Version Revision

Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008
08/17/07
(cont’d)
4.0
(cont’d)
Appendix C:
•Modified Table C-2 to Table C-6, Table C-8 to Table C-11, Table C-13 to Table C-15,
Table C-17 to Table C-20, Table C-23, Table C-24, Table C-26, and Table C-27.
•Modified notes 1 and 3 after Table C-6 and Table C-25 and expanded note 4 after
Table C-6.
Appendix D:
•Expanded note in “Receiver Sample Phase Adjustment.”
Appendix E:
•Removed 64B/66B encoding scheme from Virtex-4 devices and added note 4 in
Table E-4.
•Modified Figure E-2.
•Modified text in “Loopback.”
•Removed section on TKERR[0] vs. TKERR[3].
•Removed section on clock correction and channel bonding sequences and
accompanying table.
•Removed discrete equalization row from Table E-10.
Modified references in Appendix F.
11/02/08 4.1 Added a new paragraph regarding 2.5V power and filtering to “Powering Unused
MGTs” in Chapter 6.
Date Version Revision

Virtex-4 RocketIO MGT User Guide www.xilinx.com 7
UG076 (v4.1) November 2, 2008
Preface: About This Guide
MGT Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
User Guide Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Related Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
User Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Logical / Mathematical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Port and Attribute Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Comma Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Jitter Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Total Jitter (DJ + RJ) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MGT Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Section I:
FPGA Level Design
Chapter 1: RocketIO Transceiver Overview
Basic Architecture and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuring the RocketIO MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Available Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Byte Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 2: Clocking, Timing, and Resets
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Tile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
GT11CLK_MGT and Reference Clock Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
MGT Clock Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Common Reference Clock Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
High-Speed Dedicated MGT Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Fabric Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PMA Transmit Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PMA Receive Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency . . . . . . 72
PMA/PCS Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PMA Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Common MGT Clocking Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Setting the Clocking Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table of Contents

8www.xilinx.com Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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Special Clocking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
RXCLKSTABLE and TXCLKSTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
TXPMARESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
RXPMARESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
TXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CRC Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Resetting the Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Transmit Reset Sequence: TX Buffer Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Transmit Reset Sequence: TX Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Receive Reset Sequence: RX Buffer Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Receive Reset Sequence: RX Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Reset Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
RX Reset Sequence Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Chapter 3: PCS Digital Design Considerations
Top-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Transmit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Fabric Interface Synchronicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
RX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
External Bus Width Configuration (Fabric Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Internal Bus Width Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Fabric Interface Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PCS Bypass Byte Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8B/10B Encoding/Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
TXCHARDISPVAL and TXCHARDISPMODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TXCHARISK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TXKERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
RXCHARISK and RXRUNDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RXDISPERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RXNOTINTABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RXCHARISCOMMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Non-Standard Running Disparity Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Transmitting Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Receiving Vitesse Channel Bonding Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Symbol Alignment and Detection (Comma Detection) . . . . . . . . . . . . . . . . . . . . . . 116
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8-Bit / 10-Bit Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10-Bit Alignment for 8B/10B Encoded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Determining Barrel Shifter Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SONET Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Alignment Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Byte Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ALIGN_COMMA_WORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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RXSLIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Append/Remove Idle Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_MASK,
CLK_COR_SEQ_LEN Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Determining Correct CLK_COR_MIN_LAT and CLK_COR_MAX_LAT . . . . . . . . 126
Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
CCCB_ARBITRATOR_DISABLE = TRUE, CLOCK_CORRECTION_USE = FALSE . . 127
CCCB_ARBITRATOR_DISABLE = FALSE, CLOCK_CORRECTION_USE = TRUE . . 127
CCCB_ARBITRATOR_DISABLE Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_MASK,
CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes . . . . . . . . . . . . . . . 130
Disable Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Setting CHAN_BOND_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Implementation Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
RX Fabric Interface and Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Status and Event Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Event Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
RXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
TXBUFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Digital Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Clocking in Buffered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Chapter 4: PMA Analog Design Considerations
Serial I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Differential Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Output Swing and Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Receiver Lock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Receive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Special Analog Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Out-of-Band (OOB) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Calibration for the PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
POWERDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
RXDCCOUPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
RXPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TXPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 5: Cyclic Redundancy Check (CRC)
Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Handling End-of-Packet Residue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Latency and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
64-Bit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

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32-Bit Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example . . . . . . . . . . . . . . . . . 160
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Chapter 6: Analog and Board Design Considerations
Physical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Power Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Determining Power Supply Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Powering Unused MGTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
AC and DC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SelectIO-to-MGT Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
High-Speed Serial Trace Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Routing Serial Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Differential Trace Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 7: Simulation and Implementation
Model Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Simulation Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SmartModel Simulation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
After Reset or Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reference Clock Period Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
RXP/RXN Period Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reset After Changing Clock Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Out-of-Band (OOB) Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
1-Byte or 2-Byte Fabric Interface Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Toggling GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Simulating in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Simulating in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Frequency Calibration and Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SONET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
8B/10B Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
MGT Ports that Cannot Be Simulated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
TXBUFFERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Transceiver Location and Package Pin Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
MGT Package Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Chapter 8: Low-Latency Design
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
PCS Clocking Domains and Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192