ZiLOG Z80-AIO Instructions for use

Zilog
Z80-AIO/AIB
Hardware User's Manual
••
Zilog
yißm

Price: $4.50
03-0090-01
RevisionA
May 1978
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Z80-AIO/AIB
HARDWAREUSER'SMANUAL
780428
REVISIONA

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Z80-AIO USER1S MANUAL
TABLE OFCONTENTS
SECTIONPAGE
1.0 GENERALINFORMATION1
1.1ProductDescription1
1.2Block Diagram 1
2. 0 INSTALLATION2
2.1 Introduction 2
2.2InitialUnpackingandInspection2
2.3Installation (MCZ-1) 2
2.4PowerandSignalConnections3
3.0OPERATION4
3.1Introduction4
3.2Description4
3.3AddressModification5
3.4 Input/Output Handling6
3.5Application7
4.0PROGRAMMINGANDINITIALIZATION14
4.1Introduction14
4.2 Input Programming14
4. 3 OutputProgramming16
5.0TESTING17
5.1Introduction17
5.2Test Eguipment andAids17
5.3Calibration18
5. 4 SystemTest22

SECTIONPAGE
6.0TECHNICALDESCRIPTION27
6.1Introduction27
6.2 Description 27
6.3Spec if ication29
7. 0 MAINTENANCE32
7.1Introduction32
7.2Drift32
8. 0 DRAWINGS33
8.1Introduction33
9. 0 SUPPLEMENTARYINFORMATION40
9.1Introduction40
9.2ListofSupplementaryInformation40

AIO USER'S MANUAL
SECTION1;GENERAL INFORMATION
1.1 Product Description
TheZ80-AIOisa 12-bit analoginput/output card,
compatiblewiththeZ80 Microcoinputer BoardSeries.
Theanalogtodigitalportioncanaccept16differential
or32 single-ended channels withinputvoltagesranging
from (+/-) 2.5mV füll scale to(+/-)10V füll scale.
Thedigitaltoanalogportionprovides two, 12-bitD/A
Converterswithdoublebufferingto minimize output
switchingtransients.TheOutputvoltageisselectable
forbipolarorunipolarOperationwithOutputvoltages
rangingfrom (+/-) 2.5V füll scaleto(+/-)10V füll
scale.Thisanalog systera isinterfaced äs I/Otothe
CPUandmayoperateina pollingorinterrupt mode. I/O
addressingmaybechangedbyon-boardjumperselections.
1.2 BlockDiagram
K
ADU \
Rllfi /
Y
4
ADDR
DECODE
1
CONTROLr
\INFS \
N
<k
\
/
i
p>
CNTL&
TIMING
INTR
r ^L
PIO
DATA
BUS
INT
/l
/
v,
N
i
CHANSTB
3)
D
Z
H
r 1 1
12BIT
A/D
CONV
STROBE
1i
SAMPLE& HOLD
AMPLIFIED
^
r^
INSTRU
AMPLIF
STB (A)^
^
—• *f
STB(B)
L__^
Y
ANALOG
MUX
h^
•ANALOG
\ INPUTS
VIENTATION
ER
12BIT
D/A
CONV
12BIT
D/A
CONV
ANALOG
OUTPUTS

SECTION2:INSTALLATION
2.1 Introduction
The following section contains Informationoninitial
unpacking and inspection, powerandSignal connections
totheMCB,andInstallationofthe AIO Boardor AIB in
theMCZl series Systems.
2.2InitialUnpackingandInspection
Inspecttheproductfor shipping damage äs soon äs it is
unpacked.Checkforany physical damage that maybe
attributed toabuseand handling during shipment. If
theproduct is damaged in anyway, notify the carrier
immediately.
2.3Installation (MCZ-1)
TheAnalogBoardsmaybe installed in either ofthe
prewired I/Oboard positions in the MCZ-1/20 or MCZ-1/25
Systems.ThesepositionsareJ2andJ3 äs described in
theMCZHardware User's Manual. Jl, an undedicated and
unwired position, mayalsobeused.Inthe MCZ-1/30
System,Jl,J2andJ3ofeachcardcage,maybeused in
the identical manner äs previously described.Inthe
MCZ-1/05, -1/10and PDS, Jl (User's Option)andJ4
(VideoDisplayBoard) will directly accommodate the
AnalogBoards.

2.4PowerandSignalConnections
TheZ80AIOand AIB are pin-compatible withtheZ80MCB
bus structure.Forconvenience,thewire list for
interconnectionbetweentheMCBandtheAnalogBoardsis
provided:
TO
AIO:1-3,59-51
AIO:4
AIO:5
NextIEI
AIO: 7
AIO: 8
AIO:12
AIO:13
AIO:23
AIO:26
AIO:29
AIO:30
AIO:62-64,120-122
AIO:68
AIO:71
AIO:73
AIO:75
AIO:79
AIO:98
AIO:99
AIO:100
AIO:101
AIO:102
AIO:103
AIO:115
AIO:116
FROM
MCB:l-3,59-61
MCB: 4
MCB:5
AIO:6
LastusedIEO
MCB: 8
MCB:12
MCB:13
MCB:23
MCB:26
MCB:29
MCB:30
MCB:62-64,120-122
MCB:68
MCB:71
MCB:73
MCB:75
MCB:79
MCB:98
MCB:99
MCB:100
MCB:101
MCB:102
MCB:103
MCB:115
MCB:115
DESCRIPTION
+5V P.S.
IORQ-
DATABIT(5)
IEOof AIO/AIB
IEIOfAIO/AIB
DATABIT(3)
BIT
BIT
(6)
(0)
DATA
DATA
WR-
ADDR.BIT(7)
ADDR.BIT(5)
ADDR.BIT(6)
COMMOM
DATABIT(4)
DATABIT(2)
DATABIT(7)
DATABIT(1)
INT-
ADDR.BIT(4)
PHI-
ADDR.BIT(3)
ADDR.BIT(2)
ADDR.BIT(1)
ADDRBIT(0)
Ml-
RD-
TABLE2.3.1:MCBTOAIOORAIBWIRELIST

SECTION3:OPERATION
3.1 Introduction
This section contains a qeneral description oftheAnalog
Boards1 Operation,and provides some application Softwarefor
initializing and communicating tothe AIO and AIB.
3.2Description
Interfacing theAIOorAIBtotheSystembus is accommodated
bythe on-board PIO and is addressed äs I/O.TheADDRESS
DECODERusestenaddressesto direct all board operations.
By selecting thePIOportA orB controladdresses,thePIO
may be prograinnied toInterrupttheCPUSystemandsupplyan
Interruptvectoraddressupon completion ofanA/D
conversion. TheCONTROLandTIMING will gate therequested
analog input channel totheANALOG MULTIPLEXER, strobethe
SAMPLEandHOLD AMPLIFIER andrequestconversionoftheA/D
CONVERTER.Upon completing theconversion,theA/DCONVERTER
will respondtothePIOthroughtheCONTROLandTIMINGthat
theconverteddata is ready.At this time, thePIO may
InterrupttheSystemortheSystemmayreadtheStatus
register to find thattheconversiondata is readyandthe
resultshavenot previously beenread.
Each 12-bit D/Aconverter has twoI/Oportsforthe eight
least significant bits andthefourmost significant bits of
thedataword.The12-bitdataword is formed andpresented
totheDAC inputs forconversionwhenthemostsignificant
byte is output.

3.3Address Modifikation
The AIO or AIB InterfacestotheZ80 MCB I/Obus, occupying
ten locations in theI/O address space.The first four
locations are required forthe PIO. Thenexttwolocations
areusedtotransferthe input channeladdressandboard
Status while the remaining locationsareusedforpassing
datatothetwoD/AConverters.
I/OADDR. FUNCTION
80PORTA data
81PORTB data
82PORTA Control
83PORTB Control
88AddressRegister (Sei. Ch. No.)
89
8C
8D
8E
8F
StatusRegister
Low byteDACl Register
High byteDACl Register
LowbyteDAC2 Register
High byteDAC2 Register
TABLE 3.3.1:PREWIREDI/OADDRESSES
Theboard, äs received from the factory, is wired tooccupy
thoselocationsshown in Table 3.3.1.However, it is
possible tomovetheonboardPIOandtheboard registers
independently throughouttheI/Oaddressspace.The only
limitations uponaddress selection are that thePIOandboard
registers cannot occupythe same locations,andthethree
most significant address bits must bethesänne.
Address modification is achieved by removing the existing
addressselectionJumpersandthen installinq those indicated
in Tables3.3.2and3.3.3forthe desired address. Wherever
a "one" occurs in the address, the High jumper should be
installed. Wherever a "zero" occurs,theLowjumpershould
beinstalled.

ADDRESSBITHIGH LOW
2JP39JP38
3JP41JP40
4JP30JP31
5JP32 J^33
6JP27JP26
7JP28JP29
TABLE 3.3.2. PIO Address Selection Jumpers.
ADDRESSBITHIGHLOW
3JP37JP36
4JP34JP35
5JP32JP33
6JP27JP26
7JP28JP29
TABLE3.3.3.RegisterAddressSelection Jumpers
3.4 Input/Output Handling
Inputting ofdatacanbe accomplished in oneoftwomodes;
Polling andInterrupt.Thesemodes operate äs follows:
Polling Mode- During initialization ofthePIO,the
Interruptenable flag mustberesettopreventthe generation
ofInterrupts.Whena conversion is desired, it is initiated
by writing theAnalogChannelAddresstotheaddress
register. Theprogrammustthen periodically testthe
conversion bit in the Status registerto determine v/henthe
conversion is complete.
InterruptMode- After setting the board's PIOInterrupt
enableandvector address, conversion is startedbywriting
totheaddressregister.Theprogram execution canthen
continue until theendofconversion has occurred.Atthat
time, thePIOgeneratesanInterruptvector causing theCPU
to begin executionoftheInterruptService routine.
Outputting Data - Outputting ofdatatothe AIO's twoD/A
Converters is straight-forward. Thetwo 12-bit D/A
ConvertershaveseparateI/Oaddressesfortheupperand
lower bytesofthedataword.A word is formed by loading
the eight least significant bits into a latch wheretheyare
bufferedfromtheD/A inputs untilthefinalfour bits ofthe
datawordare received. The combined 12-bits of data are

then gated simultaneously totheD/A inputs. This double
bufferinq schemeprevents conversion of partial words, and
therefore, eliminates spiking in theOutputSignal.
3.5Application
3.5.1 Input Range Selection
Thedata acquisition Systemhasbeen jumpered for(+/-)10V
Operation. Other rangesare possible andcanbeselected äs
shown in Table 3.5.1.3.
RANGE JUMPERS
(+/-)10V W8*, W7*, W9*, W10*
(+/-)5V W8*, JP21, W9*, W10*
(+/-)2.5V W8*, JP20,JP21, W9*, WlO*
0to+10VJP23,JP21,JP25,JP43
0to+5VJP23,JP20,JP21,JP25,JP43
TABLE3.5.1.1.InputRange Setting Jumpers.
All jumpers marked with an asterisk (*)are installed atthe
factoryandare implemented by a plated-through hole
connecting padsontheupperand lower surfacesoftheboard.
Thesecanbe removed bycareful manual drilling with a 0.055"
(#54)drill.Allotherjumpersare wire and should be
sleevedwherevera possibleshort could occur.
When theränge is changed,those existing jumpersthatare
notusedforthenewränge must first beremoved,andthen
the Installation ofthe additional jumpers performed.
TheanalogtodigitalConverterOutputdata is normally
presented in 2"s complement format forbipolarranges.For
straight binary Operationremove wire JumperW9and install
JP25.
3.5.2OutputRangeSelection
EachDAC is jumperedatthefactoryfor (+/-)10 volt
Operationand two's complement coding (Table 3.5.2.2).
However, it is possibleto alter thesejumpers äs shown in
Table3.5.2.1forotherOutputvoltages.Jumpers indicated
byanasteriskareplated-through holes ontheboardand
shouldberemovedbycarefulmanualdrilling with a 0.055"

(#54)drill. When making a change, first remove those
jumpers indicated forthepresentränge,andreplace them
with thosejumpers recruired forthe desired ränge.
JUMPERS
RANGEDACl DAC2
(+/-)10V Wl*, W2* W3*, W4*
(+/-)5VJP11, W2*
(+/-)2.5V JP11, W2*, JP9JP15, W4*, JP13
0to +10VJP11, JP8 JP15,JP12
0to+5V JP11,JP8, JP9 JP15,JP12,JP13
TABLE 3.5.2.1.OutputRange Selection Jumpers.
When converting from bipolarto unipolar Operation, W5*
should be removed andJP7 installed. This convertsfrom
two's complement Operationto straight binary.
Bipolar- Two'sComplement
Digital Input/Output (+/-)10V (+/-)5V (+/-)2.5V
0111...11 "(7FFH) +9.9951V +4.9975V +2.4988V
100...00 (800H) -10.0000V -5.0000V-2.5000V
^s.
Unipolar- StraightBinary
Digital Input/Output0 to+10V0 to+5V
111...111 (FFFH) 9.9975V4.9988
000...00 (OOOH) 0.0000V0.0000V
TABLE3.5.2.2.Analog Input andOutput Füll Scale RangeValues,
3.5.3 Differentlal-Single EndedSelected
Theboard, äs received fromthefactory, is wired for
differential input. The input Systemcanbe changed from
differential to single-ended or vice versa by simply changing
severaljumpers.W6* is required fordifferentialOperation,
and JP16andJP18are reauired forsingle-endedOperation.
W6* is a plated-through connection andshouldberemovedby
careful manual drilling with a 0.055"(#54)drill.
DifferentialOperation is generally usedto minimize common
mode noise during low level Operation.Single-ended
ooeration is suitable for large inputSignals. However, a
noise reduction often-to-onecanbe achieved in single-ended

Operationbymaking a "pseudo differential" connection.This
involvessensingthegroundatthesignalsourceratherthan
at theboard.Tousethis method, allinputSignals must be
onthe sanie groundSystemat their source.
Pseudo-differential Operationoccurswhen jumper JP18 has
beenremovedand JPl isinstalled.
3.5.4InputSystem Low LevelOperation
Whenitisdesiredtooperatetheinput systein
instrumentation amplifier atotherthanunitygainfor low
level Signals,a simplechangeofthegainsettingresistor
isallthatisrequired.R8andtheoptionalparallel
resistorR9formthisresistance.The value ofthegain
settingresistorcanbecalculatedfromthefollowing
formula:
20K
R =
G- l
Stable(10 ppm/deg C)wire-woundresistorsshouldbeused.
Increasingtheamplifiergainalsoincreasesitssettling
time.Asa result,theSystem delay timermustbeextended
byincreasingthevalueofR15andtheoptionalparallel
resistorR14.DelaysandvaluesofR15versusGainareshown
in Table 3.5.4.1.
AmplifierGainDelayTime(us)R15(+20%)
l20 9.5K
1030 14.3K
1004019K
100010047.5K
TABLE3.5.4.1.DelayTimevs.AmplifierGain.
3.5.5InputSystem Application
ThedataacquisitionSystem,incorporatedintothe AIO or
AIB, uses a fixed timing sequence between channel selection
andtheStartofdataconversion. If desired,this time may
beincreasedbytheadditionofanexternalresistorand
capacitor. Thisprocedureisdescribedinthelowlevel
Operationsection.

Multiplexer
on Kt-sistdnct
FIGURE3.5.5.1.OnChannelMultiplexerCircuitfor
Single-Ended Operation.
Fora gain ofl (setat factory), multiplexer settling time
is 20us which is sufficient for most application. The only
externalfactorwhichaffectsthemultiplexer settling time
is theoutput impedance (Rs)ofthesourceconnectedtoa
channel. A circuit roodelofan "Cn" channel is shown in
Figure 3.5.5.1. The input capacitance (Cl) of50pFfor
single-ended Operationdoesnotaffectthesettling time
since it is continuously connectedto thesource.TheSignal
attheOutputofthemultiplexermustbeallowedtosettleto
(+/-)0.01% (nine time constants)to maintain the füll
accuracyoftheSystem.Themultiplexer time constantcanbe
calculated with theformula:Ts= (Rs+ Ron) Co. Fora
source resistance of1k,Ts= (l+ 1.8k)x 50pF= 14Ons.
Thus,1.20us is neededtosettleto+0.01%. This is well
below the fixed lOus allowedformultiplexersettling.The
accuracyoftheSystem, is therefore, preserved.
If thesource bandwidth canbe limited, high impedance
sources may beaccuratelyhandledby placing a large
capacitor ecross themultiplexerinput.An analysis ofsuch
a circuit shows thata capacitorof O.SuF is sufficient.For
sucha capacitance,themultiplexer time constant becomes
90ns.If this method cannotbeused,the time allowedfor
settlingcanbe increased äs described in the section on low
level Operation.
10

For switchinq of large Signals, it must be remembered that
theon resistance is thechannel resistance ofa FET which IF
a nonlinear function ofthe applied voltaqes.Asa result,
the previous calculations are only an approximation derived
froma linearized mode. Another factornot considered in the
above calculation is the addressing delay ofthe multiplexer.
This is typically 250nsand is additivetotheabove
calculated times.
For differential units, thesame considerations apply. Even
thoughtwo input circuits are involved, there is sufficient
component matching within themultiplexertoprevent
measurable differences in thetransfer functions foreach
halfoftheSignal. When operated in thedifferential irode,
Co in Figure 3.5.5.1becomes 12.5pF with an Ron= 1.8k in
eachleg. Therefore, the time constantbecomes one-half the
time constantforthe single-ended channel.
Theanalog inputs have reversed-biased diode circuitswhich
prevent damage from discharge of static electricity.
However, it is still wise to take reasonable precautions
against staticdischarge.
3.5.6ThermocoupleTemperature Acauisition
Thermocouples are oftenused äs temperature sensorsfor
processcontrolSystems.Thermocouplesare characterized by
temperature coefficients of10to70uV/degC and operatinq
rangesofminushundredstoplusthousandsofdegrees
centrigrade. Whenthe AIO or AIB is operated with an
Instrumentation amplifier gain of100or more, it maybe
connected directly tothese devices. The wires running from
thermocouple measuring devicesoften pick uplarge
common-mode noise Signalsof60Hzorhigher freauencies.
The high common-mode rejection oftheInstrumentamplifier
will reject common-modenoise.To minimize differentialmode
noise,theSignal wire shouldbe twisted, and if possible,
shielded.Asa rule, an unshielded twisted pair is better
thana coaxbuta shieldedtwisted pair is best.
Theremotesensorshouldbe earth-grounded toprevent
common-modevoltagesfrom exceeding the+5 volt rängeofthe
multiplexer.Tocompletea thermocoupleSystem, it is
necessaryto terminate allthermocouple wire pairs atan
isothermal boxorconnector strip of some type. An ordinary
11

barrierstrip may be monitored to allow the observed
thermocouple cmftobe cold-junction compensated. Figure
3.5.6.2showsa circuitforthispurpose.TheOutputis
connectedtooneoftheinput channels tosupply ambient
temperature datatotheSystem Computer. Outputsensitivity
isapproximately2 mV/deg C.
12