ZiLOG Z80 series User manual

VM
SD
microcomputer
handbook

(1

The Z-
80 Microcomputer
Handbook
by
William
Barden, Jr.
DISTRIBUTORS
L. P. ENTERPRISES
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INDIANA 46268 USA

Copyright © 1978 by Howard W. Sams & Co., Inc.,
Indianapolis
, Indiana 46268
FIRST EDITION
FIRST PRINTING-1978
All rights reserved .
Reproduction or use, without
express permission, of editorial or pictorial content,
in any manner, is prohibited
.
No patent liability is
assumed with respect to the use of the information
contained herein. While every precaution has been
taken in the preparation of this book
, the publisher
assumes no responsibility for errors or omissions.
Neither is any liability assumed for damages resulting
from the use of the information contained herein.
International Standard Book Number: 0-672-21500-4
Library of
Congress Catalog
Card Number: 77-93166
Printed in the United States
of America.

Preface
Microprocessors have evolved from units that handled data in
4-bit slices with rudimentary instruction sets into devices that rival,
or surpass, minicomputers in architecture and software instruction
repertoire. The Zilog Model Z-80 represents a microprocessor that is
extremely sophisticated from both a hardware implementation and
software implementation viewpoint. The Z-80 microprocessor is
truly a computer on a chip that requires only a few external compo-
nents-a 5-volt power supply, a simple oscillator, and read-only
memory-to construct a complete computer system. The instruction
set of the Z-80 includes that of the Intel 8080A as a subset, making
the Z-80 an ideal software replacement for the 8080A; the Z-80 has
many new instructions and addressing modes to supplement the
8080A instructions. A search of a string of characters, for example,
can be implemented with one instruction after initialization, the one
search instruction replacing four equivalent instructions in other
microprocessors.
In addition to the Z-80 microprocessor itself, Zilog has imple-
mented other devices to supplement the power of the Z-80. A PIO
provides parallel I/O with two 8-bit ports, software configured I/O,
vectored-interrupt capability, and automatic priority interrupt en-
coding. A CTC, or Counter-Timer-Circuit, provides programmable
counting and timing functions for real-time events. Other major
devices are also available. Zilog and other manufacturers have de-
veloped microcomputer systems based on this family of Z-80 devices,
and the systems have played their role in narrowing the gap between
"minicomputer systems" and "microcomputer systems," a division
that becomes less and less distinct from month to month.
The purpose of this book is threefold, to acquaint the reader with
the hardware of the Z-80, to discuss the almost overwhelming (in
number of instructions) software aspects of the Z-80, and to describe
microcomputer systems built around the Z-80.

Section I discusses Z-80 hardware. The architecture, interface sig-
nals, and timing are discussed in the first two chapters. Addressing
modes and instructions are covered in the next two chapters; both
addressing and instruction repertoire are fairly easily grouped and
explained, although they may appear confusing at first glance. The
effect of arithmetic operations and other operations on CPU flags is
presented in Chapter 6. The powerful interrupt sequences of the
Z-80 are discussed in the next chapter. Chapter 8 describes interfac-
ing examples of I/O and memory devices.
Section II describes Z-80 software. A representative Z-80 assembler
program is introduced in the first chapter of the section. An assem-
bler is almost a necessity with a microprocessor having such a large
instruction set, but machine language aspects are also covered.
Chapters 10 through 15 present the common programming opera-
tions of moving data, arithmetic operations, shifting and bit opera-
tions, list and table procedures, subroutine use, and I/O functions in
relation to instruction set groups. Many examples of each kind of
operation are provided. The last chapter of the section details some
commonly used subroutines written in Z-80 assembly language.
The third section discusses microcomputers built around the Z-80.
Chapter 17 covers Zilog products including the microcomputer
board products in the Z-80 family and development systems. Four
other Z-80 microcomputer manufacturers are described in the last
chapter. Technical Design Labs, Inc., Cromemco, Inc., The Digital
Group, Inc., and Radio Shack. The hardware and software aspects
of all five manufacturers are presented.
The Z-80 will prove attractive to many users, not only as a succes-
sor to the 8080A, but as a powerful computer in its own right.
The Z-80 will soon have a successor, in this dynamic microcom-
puter development environment, but for the time being it represents
microcomputer "state-of-the-art." The author hopes that the reader
will derive a great deal of benefit from the book and that the Z-80
will solve a few hardware and software implementation problems.
Much credit for this book goes to my wife, Janet, who has solved
my major software implementation problems-manuscript prepara-
tion.
WILLIAM BARDEN, JR.
To Bill and Norma and
the Little Green Onions.

Contents
SECTION
I-Z-80 Hardware
CHAPTER 1
INTRODUCTION .
. 11
CHAPTER 2
Z-80 ARCHITECTURE . . . . . . . . . . . . . 15
General-
Purpose Registers
-
Flag Registers
-
Special-Purpose Regis-
ters-Microcomputer
Component Parts
CHAPTER 3
INTERFACE SIGNALS AND TIMING. . . . . . . . . . 26
Address and Data Bus-Bus Control Signals-Memory Signals-In-
put/Output Signals-Other CPU Signals-Interrupt-Related Signals
-CPU Electrical Specifications-CPU Timing-MI Cycle-Memory
Data Read and Write Cycles-I/O Read and Write Cycles-
Bus Request/Acknowledge Cycle-Interrupt Request/Acknowledge
Cycle-Nonmaskable Interrupt Request Cycle-Exit From Halt In-
struction-Memory or I/O Wait States
CHAPTER 4
ADDRESSING MODES . . . . . . . . . . . . . 41
Implied Addressing-Immediate Addressing-Extended Immediate
Addressing-Register Addressing-Register Indirect Addressing-Ex-
tended Addressing-Modified Page Zero Addressing-Relative Ad-
dressing-Indexed Addressing-Bit Addressing
CHAPTER 5
INSTRUCTION SET . . . . . . . . . . . . . . 55
8-Bit Load Group-16-Bit Load Group-Exchange, Block Transfer,
and Search Group-8-Bit Arithmetic and Logical Group-General-
Purpose Arithmetic and CPU Control Group-16-Bit Arithmetic
Group-Rotate and Shift Group-Bit Set, Reset, and Test Group-
Jump Group-Input and Output Group

CHAPTER 6
FLAGS AND ARITHMETIC OPERATIONS . . . . . . . . 93
Z Flag-Sign Flag-Carry Flag-Parity/Overflow Flag
CHAPTER 7
INTERRUPT SEQUENCE . . . . . . . . . . . .
Z-80 Interrupt Inputs-NMI Interrupt-Maskable Interrupt Mode 0
-Maskable Interrupt Mode 1-Maskable Interrupt Mode 2
CHAPTER 8
INTERFACING MEMORY AND I/O DEVICES TO THE Z-80 . . . . 116
Minimum Z-80 System-Interfacing ROM and RAM-Dynamic
Memory Interfacing-Z-80 PIO Interfacing-PIO Mode 0-PIO
Mode 1-PIO Mode 2-PIO Mode 3-PIO Interrupts-PIO Initial
Conditions-Z-80 PIO Configuration
SECTION
II_Z.80 Software
CHAPTER 9
Z-80 ASSEMBLER . . . . . . . . . . . . . . 133
Machine Language-The Assembly Process-Assembly Format-
Symbolic Representation-Representation of Number Bases-Ex-
pression Evaluation-Pseudo-Operations-Assembly
CHAPTER 10
MOVING DATA-LOAD, BLOCK TRANSFER,
AND EXCHANGE GROUPS . . . . . . . . . . . . 145
8-Bit Moves-8-Bit Moves Using HL-8-Bit Moves Using Index Reg-
isters-8-Bit Moves Using the A Register and Extended Addressing-
8-Bit Moves Using the A Register and BC or DE Register Indirect-
16-Bit Moves-Immediate Loads of 16 Bits-16-Bit Transfers to and
From Memory-16-Bit Data Transfers to the Stack-16-Bit Stack Op-
erations-Block Transfer Ins tru ctions-Exchange Group
CHAPTER 11
ARITHMETIC AND LOGICAL OPERATIONS-8- AND 16-BIT
ARITHMETIC GROUP, DECIMAL ARITHMETIC . . . . . . 161
8-Bit
Arithmetic Operations
-
8-Bit
Logical Operations-8-Bit Com-
pares-8-Bit Increment
and Decrement-
16-Bit Arithmetic Opera-
tions
-General-Purpose Arithmetic
Instructions
- Decimal
Arithme-
tic Operations

CHAPTER 12
SHIFTING AND BIT MANIPULATION-ROTATE AND SHIFT,
BIT SET, RESET, AND TEST GROUPS . . . . . . . . . 174
Logical Shifts-Multiplication and Division by Shifting-Rotate-
Type Shifts-Arithmetic Shifts-The 4-Bit BCD Shifts-Bit Set, Re-
set, and Test Group-Software Multiplication and Division
CHAPTER 13
LIST AND TABLE OPERATIONS-SEARCH GROUP
Data Strings-Table Operations-List Operations
. 192
CHAPTER 14
SUBROUTINE OPERATION-JUMP, CALL, AND RETURN GROUPS . . 208
Jump Instruction
-
Subroutine
Use-Reentrancy
CHAPTER 15
1/0 AND INTERRUPT OPERATIONS-I/O AND
CPU CONTROL GROUPS .
A Register I/O Instructions-I/O Instructions Using C Register-I/O
Block Transfer
Instructions
-Software I/O Drivers-DMA Actions-
Interrupt Operations
219
CHAPTER 16
Z-80 PROGRAMMING-COMMONLY USED SUBROUTINES . . 232
Comparison Subroutine-Timing Loop-Multiply and Divide Sub-
routines-Multiple-Precision Arithmetic Routines-ASCII to Base X
Conversions-
Base
X to ASCII Conversions-Fill Data Routine-
String Comparison-Table Search Routine
SECTION
III-Z.80 Microcomputers
CHAPTER 17
ZILOG, INC .. . . . . . . . . . . . . . . . 247
Z-80 MCBTM Microcomputer Board-MCB Memory-MCB I/O
Ports-MCB Parallel I/O-MCB Serial I/O-MCB Interrupts-MCB
Configurations-MCB Monitor-Z-80 Development System-Z-80
Development System Hardware-Z-80 Development System Soft-
ware-Other Zilog Products

CHAPTER 18
OTHER Z
-
80 MICROCOMPUTER SYSTEMS . . . . . . . . 259
Technical Design Labs, Inc.-TDL ZPUTM Board-TDL Z16TM
Board - TDL System Monitor Board - TDL XitanTM Microcomputer-
TDL Software-Cromemco
, Inc.-Cromemco CPU Card -
Cromemco
Memory-Other Cromemco Boards-Cromemco Z-1 and Z
-
2 Micro-
computer Systems
-
Cromemco Software
- The Digital Group, Inc.-
Digital Group Z-80 CPU Board-Digital Group Memory Boards-
Digital Group I/O Interfaces and Devices
- Digital Group Systems-
Digital Group Software
-
Radio Shack
-
Radio Shack Hardware-
Radio Shack Software
APPENDIX A
Z-80 ELECTRICAL SPECIFICATIONS
APPENDIX B
8080 AND Z
-
80 INSTRUCTIONS COMPARED
APPENDIX C
Z-80 INSTRUCTIONS
APPENDIX D
BINARY AND HEXADECIMAL REPRESENTATION .
APPENDIX E
ASCII CHARACTER CODE .
APPENDIX F
Z-80 MICROCOMPUTER MANUFACTURERS
. 275
. 282
. 283
. 295
. 298
. 300
INDEX . . . . . . . . . . . . . . . . . 301

SECTION I
Z-80 Hardware

CHAPTER 1
Introduction
In 1971, Intel Corporation introduced the first microcomputer on
a chip, the Intel 4004. Although the 4004 was truly not a self-con-
tained computer on a single Large-Scale-Integration (LSI) chip, it
contained a great deal of logic associated with computer central
processing unit implementation. One LSI chip replaced hundreds of
circuits that were to be found in conventional minicomputers at the
time. Although the 46-instruction repertoire was not large, it was
adequate for control applications which required decision making
that could not easily be implemented in programmable-logic arrays
and in which extensive mathematical processing was not required.
The 4004 handled data 4 bits at a time and could perform 100,000
additions of two 4-bit operands per second.
The next generation of microprocessors from Intel retained the
PMOS (P-channel metal-oxide semiconductor) fabrication tech-
niques of the 4004, but offered an 8-bit wide
data bus
and a larger
instruction repertoire of 48 instructions. Designated the 8008, the
microprocessor had a faster instruction cycle time than the 4004 as
data for both instruction execution and decoding and for operands
could be handled in 8-bit slices. In addition, the 8008 could address
16,384 memory locations of 8 bits each, contained seven 8-bit regis-
ters, had memory stack capability, and had a single-level interrupt
capability. The 8008 could perform approximately 80,000 additions
of two 8-bit operands per second. The instruction set of the 8008 was
not compatible with the 4004.
The 8008 and 4004 had achieved widespread usage through the
electronics industry in a very short time after their introduction,
primarily because there was little else available in the way of micro-
processors. To achieve compatibility with the 8008 insofar as instruc-
11

tion repertoire, the Intel 8080, introduced in late 1973, included
the instruction set of the 8008 and supplemented it with 30 more
instructions. Users of the 8008 could now change to a faster, more
versatile microprocessor while not discarding 8008 software pro-
grams, since all 8008 software would presumably execute on the
8080. The 8080 was an NMOS (N-channel metal-oxide semiconduc-
tor) microprocessor that allowed faster clock rates. Additions of two
8-bit operands could now be carried out at rates of 500,000 per sec-
ond. In addition, all other instruction times were much shorter than
the 8008 as the 8080 was built around a 40-pin chip, requiring the
CPU to do much less time sharing of the data bus between data
transfers and instruction implementation.
The 8080 supplemented the hardware features of the 8008. In
place of 16,384 (16K) memory addresses, the 8080 could address
65,536 (64K). Rather than a limited 7-level memory stack, the 8080
offered a memory stack in external memory itself instead of the CPU.
A binary-coded decimal or
bcd
capability was built into the arith-
metic and logic unit in the CPU; additions of two bed operands
could now be implemented. Expanded addressing modes to permit
direct addressing of external memory was offered. Although the 78
instructions of the 8080 still seemed strange to many programmers,
the instruction set decidedly had moved away from one for pri-
marily control applications to one that was more general purpose in
nature.
In 1976, Intel brought out several variations on the 8080. The
Intel 8085 included a serial input/output capability on the micro-
processor chip itself. In addition, the 8085 had a requirement of
only a single-phase clock (the 8008 and 8080 were two-phase clocks)
and a single 5-volt power supply (the 8008 and 8080 required two
and three voltages, respectively). As the number of supporting
packages had grown impressively (such chips as a programmable
peripheral interface, interrupt controller, and crt controller) Intel
provided very powerful computing capability at faster and faster
speeds (770,000 8-bit adds per second), while still retaining com-
patability with existing software written for the 8008 and 8080.
Although the 8085 was an improvement over the 8080 in many
features, the instruction set remained very similar to the 8080. Only
two new instructions were added, one to read serial and interrupt
data, and one to write serial and interrupt data. Many of the inherent
inadequacies of the 8008 and 8080 remained.
The Zilog, Inc. Z-80 microprocessor chip has provided another
level of sophistication for the widely used 8008/8080 base. Bearing
in mind that the super computer of today is the surplus bargain of
tomorrow, the Z-80 has supplemented the instruction set and capa-
bilities of the 8080 in the same fashion as the 8080 increased the
12

capabilities of the 8008. In addition, Zilog has produced a family
of support chips that supplement the Z-80. The Z-80 is software
compatible with the 8080, allowing existing 8008 and 8080 software
to be executed on the Z-80. While the limitations of the 8008 and
8080 instructions and architecture must of necessity be retained in
the Z-80, the Z-80 offers new instructions, new addressing modes,
and new hardware features that provide more capability and versa-
tility than ever before.
800818080
Fig. 1-1
. Register comparison 8008,
8080, and Z-80.
z-80
A REGISTER FLAGS A'
FLAGS'
B
C B'
C'
D
E
D' E'
H
L
H'
L'
INTERRUPT
VECTOR I
MEMORY
REFRESH R
INDEX REGISTER IX
IY
STACK POINTER SP
PROGRAM COUNTER PC
800818080
In addition to providing the eight 8-bit CPU registers of the 8080,
the Z-80 duplicates the eight registers to offer sixteen registers. Two
index registers offer indexing capability not provided in the 8080.
An interrupt-vector register and memory-refresh register provide
special interrupt functions and dynamic memory-refresh capability.
Fig. 1-1 shows the basic register arrangement of the 8008, 8080, and
Z-80.
Z-80 I
UNUSED
98
80 Z-80
INSTRUCTIONS
30 8080
INSTRUCTIONS
48 8008
INSTRUCTIONS
256 POSSIBLE
INSTRUCTION
TYPES (ONE
BYTE OP-CODE)
Fig. 1-2 . Instruction comparison 8008 , 8080
,
and Z-80.
13

The 78 instructions of the 8080 are provided in the Z-80, but the
total number of instructions comes to 158. Many of these are logical
extensions of 8080 instructions, but many are extremely powerful
and a complete departure from the 8080. Fig. 1-2 shows the relative
differences between the 8008, 8080, and Z-80.
All Input/Output and interrupt capability of the 8080 is retained
in the Z-80. I/O is expanded, however, to operate from any CPU
register and to operate in "block" fashion, that is, to facilitate transfer
of many bytes at a time over a programmed (non-DMA) I/O chan-
nel. Interrupts include the standard external interrupt capability of
the 8080, but supplement this with a separate "nonmaskable" inter-
rupt similar to the Motorola MC6800 and MOS Technology MCS
6502. Other interrupt capability allows for interrupt vectoring any
where in memory, rather than just to eight locations in page 0, and
for up to 128 levels of interrupts, rather than eight.
The Z-80 Microcomputer Handbook is divided into three sections.
Section I covers the hardware aspects of the Z-80. Architecture, in-
terface signals and timing, addressing modes, instruction set, flags,
interrupt sequences, interface of memory and I/O devices, and DMA
operation are discussed. When applicable, differences between the
8080 and Z-80 are discussed. Section II discusses Z-80 software,
grouped in similar manner to Zilog Z-80 documentation. Section II
also provides programming examples of Z-80 code. Many times, a
short section of a program will greatly clarify the somewhat pedantic
descriptions of individual instructions. Section III discusses five
microcomputer manufacturers that have built microcomputers
around the Z-80 microprocessor chip. Appendix A provides complete
electrical specifications for the Z-80. Appendix B cross-references
8080 instructions to the Z-80 instruction set and Appendix C provides
a short description of each Z-80 instruction. Appendix D reviews
binary and hexadecimal representation while Appendix E lists
ASCII character codes. The last appendix, Appendix F, lists Z-80
Microcomputer manufacturers.
14

CHAPTER 2
Z-80 Architecture
The architecture of the Z-80 is shown in Fig. 2-1. Thirteen CPU
and system control signals are sent to or generated in the instruction
decode and CPU control portion of the microprocessor. The data bus
is eight bits wide and is the path for all data transferred between
external memory and input/output devices and CPU registers. The
address bus is sixteen bits wide. Normally the address bus would
specify an external memory address of 0 to 65535 (0 to 64K - 1)
since the Z-80 has a full complement of input/output instructions
and no "memory-mapped" input/output would be required. (In
memory-mapped input/output, a portion of the memory addresses
must be dedicated to addresses of input/output devices).
The main path for data within the CPU is an internal data bus
which connects the CPU registers, arithmetic and logical unit, data
bus control, and instruction register. The arithmetic and logical unit
performs addition, subtraction, logical functions of ANDing, ORing,
and exclusive ORing, and shifting operations between two 8-bit
operands. In addition, binary-coded decimal (bcd) operations may
be performed under control of a Decimal Adjust Accumulator in-
struction.
GENERAL-PURPOSE REGISTERS
The Z-80 registers consist of fourteen general-purpose 8-bit regis-
ters designated A, B, C, D, E, H, and L and A', B', C', D', E', H',
and L'. Only one set of seven registers and the corresponding flag
register F or F' can be active at any given time. A special Z-80 in-
struction selects A and F or A' and F', while a second instruction
selects B, C, D, E, H, L, or B', C', D', E', H', or L'. The possible com-
15

----------------------------------
Z-80 MICROPROCESSOR
INTERNAL
SYSTEM
CONTROL
SIGNALS
DATA BUS
DATA
ALU BUS
CONTROL
CPU
REGISTERS
NSTRUCTION
REGISTER
I
CPU
SYSTEM
CONTROL
SIGNALS
ADDRESS
BUS
CONTROL
INTERNAL
CONTROL
`---------------------------------'
B
D
H
IX
E
L
R
IY
SP
PC
B
D'
FLAG S'
C'
E'
Fig. 2-1 .
Z-80 Microprocessor architecture.
16-BIT
ADDRESS
BUS
binations
of A and F and the
remaining six general
-purpose registers
are shown in Fig. 2-2.
The advantage in two blocks of general-purpose registers is that
a programmer may rapidly switch from one block to another. In the
simplest case,
this provides more register storage in the CPU. Reg-
ister
storage in the CPU is to be preferred over storage in memory
as data can be accessed by a program much more rapidly from CPU
registers than from external memory. In a more sophisticated use of
the block switching capability, the unused set of registers may be
used to hold the
environment
after receiving an interrupt.
This con-
cept will be discussed in a later chapter in this section.
Just as in the 8080, the general-purpose registers are somewhat
specialized in function. Eight bits of data may be moved between
memory and any of the seven registers or from one register to the
next. Arithmetic and logical operations, however, such as adding
two operands or exclusive ORing two operands can only be done
using the A register (or A') and another register or memory location.
FLAGS
C
^--^-
^
DATA
BUS
16

A
B
D
H
F
C
E
L
Fig. 2 - 2. Register block combinations.
A
B
D
H
F
C.
E'
L'
A
B
D
H
F'
C
E
L
W H
NON PRIME
NON PRIME
NON PRIME
PRIME
PRIME
NON PRIME
PRIME
PRIME
The result of the operation always goes into the A register. In gen-
eral, then, the currently selected A register is the main register for
performing arithmetic and logical operations as shown in Fig. 2-3.
The remaining six registers are grouped into
register pairs B,C;
D,E; and H,L. For many operations in the 8008, 8080, and Z-80 the
data within the three register pairs represents a memory address.
The H,L registers, for example, originally specified a High memory
address of eight more significant bits and a Low memory address of
eight less significant bits as shown in Fig. 2-4. The same is true of
the B,C and D,E registers. In the 8080, the capability also was pro-
vided to allow the B,C and D,E to specify a memory address, giving
three register pairs that could hold a memory address
pointer to
data in memory. In general, the three register pairs will hold mem-
ory addresses as shown in Fig. 2-4, although a second use for them
is to allow
double-precision arithmetic.
8-BIT
AR ITHMETIC OR
LOGICAL RESULT
AL
U A
FL GS
OPERA ND 1
OPER
AND 2
MEMORY OPERAND
AIOR A9 B (OR 8
1
C (C')
1
OTHER GEN-
L L (n
E (E'1
ERAL PURPOSE
H (H ')
_A
L (L')
J
REGISTERS
Fig. 2-3. Arithmetic and logical operations.
17

16-BIT MEMORY ADDRESS
OR DOUBLE
- PRECISION VALUE
REGISTER PAIR
B(B 1
C(C 1
B, C
REGISTER PAIR
D, E
DID 1
E(E 1
REGISTER PAIR
L
H
H(H 1
LIL )
,
8 H IGH-ORDER BITS 8 LOW-ORDER B ITS
Fig. 2-4
. Register pairs.
Double-precision arithmetic involves adding, subtracting, incre-
menting (adding one), or decrementing (subtracting one) a 16-bit
value. Most arithmetic and logical operations in the Z-80 are oriented
towards 8-bit operations, but the Z-80 allows limited operations be-
tween the register pairs and the stack pointer and index registers IX
and IY. The general philosophy for this probably evolved from the
requirement to manipulate memory address pointers in some con-
venient fashion, since all external memory addresses are 16-bit ad-
dresses and two 8-bit operations would have to be performed if 16-
bit arithmetic were not implemented. Fig. 2-5 shows the use of the
register pairs in double-precision operations.
16-B IT RESULT
ALU
ADD, SUBTRACT,
INCREMENT
,
DECREMENT
I -
f _f
OPERAND ANDI OPERAND 2
_l-t
I
B,C REGISTER PAIR
D, E REGISTER PAIR
H, L REGISTER PAIR
SP
IX
IY
FLAG S
Fig. 2-5. Register pair double-
precision operation.
FLAG REGISTER
The flag register is selected along with the A register. At any given
time A and F or A' and F' are selected. Although the
flag
register is
a register of eight bits as are the other seven CPU registers, it is more
a collection of eight bits conveniently grouped into one register than
a general-purpose register. The bits within the flag register specify
various CPU conditions that have occurred after an arithmetic, logi-
cal, or other CPU operation. For example, it is convenient to know
if the result of the addition of two operands resulted in a zero result,
18

a positive
(
zero or greater
)
result , or a negative result
.
A zero flag
and a sign flag in the flag register may be tested by the program after
the add to determine the nature of the result . Other flags are the
carry flag (C), the carry from the high order bit of the accumulator,
the parity/overflow flag
(
P/V), specifying a parity or overflow con-
dition, the half
carry
flag (H ), which is essentially a bed
carry or
borrow from the low order bed digit ,
and the subtract flag (N), set
for bed subtract operations .
The flag register format is shown in Fig.
2-6. The interaction of CPU operations and the flags is discussed in
BIT
BIT
7 6
5 4 3 2 1 0
FLAG
I S
Z
X
H
X
PIV N
REGISTER
L CARRY FLAG
SUBTRACT FLAG
LDUAL PURPOSE PARITY/
OVERFLOW FLAG
I NDETERM I NATE
BCD HALF CARRY FLAG
INDETERMINATE
ZERO FLAG
SIGN FLAG
Fig. 2-6
.
Flag register format.
detail in a later chapter in this section. Throughout this book the
term flags, flag reigster, and condition codes will be used inter-
changeably.
SPECIAL-PURPOSE REGISTERS
The remaining CPU registers that are available to the programmer
are the I, R, IX, IY, SP, and PC registers. Two of these registers are
exactly the same as they are in the 8080, the SP, or Stack Pointer, and
PC, or Program Counter. The PC register is a 16-bit register that
holds the location of the current instruction being fetched from mem-
ory. Instructions in the Z-80 are one, two, three, or four bytes long.
If a sequence of eight instructions is being executed, as shown in
Fig. 2-7, the PC will hold the indicated values. Note that the PC
always points to the start of the next instruction, and that the CPU
will automatically increment the PC by one, two, three, or four
depending on the length of the instruction being executed. The PC
is available to the programmer only in the sense that it may be
loaded
or
stored.
No arithmetic or logical operations on the PC are
permitted.
19