Acrosser Technology AR-B1579 User manual

AR-B1579
Half Size Pentium(586)
CPU BOARD
User’s Guide
Edition: 1.2
Book Number: AR-B1579

AR-B1579 User's Guide
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Table of Contents
0. PREFACE...............................................................................................................................................................0-3
0.1 COPYRIGHT NOTICE AND DISCLAIMER......................................................................................................................... 0-3
0.2 WELCOME TO THE AR-B1579 CPU BOARD.................................................................................................................... 0-3
0.3 BEFORE YOU USE THIS GUIDE...................................................................................................................................... 0-3
0.4 RETURNING YOUR BOARD FOR SERVICE ....................................................................................................................0-3
0.5 TECHNICAL SUPPORT AND USER COMMENTS............................................................................................................0-3
0.6 ORGANIZATION................................................................................................................................................................0-4
0.7 STATIC ELECTRICITY PRECAUTIONS............................................................................................................................0-4
1. OVERVIEW.............................................................................................................................................................1-1
1.1 INTRODUCTION................................................................................................................................................................1-1
1.2 PACKING LIST ..................................................................................................................................................................1-1
1.3 FEATURES........................................................................................................................................................................1-2
2. SYSTEM CONTROLLER .......................................................................................................................................2-1
2.1 DMA CONTROLLER.......................................................................................................................................................... 2-1
2.2 KEYBOARD CONTROLLER..............................................................................................................................................2-1
2.3 INTERRUPT CONTROLLER..............................................................................................................................................2-2
2.3.1 I/O Port Address Map.................................................................................................................................................2-3
2.3.2 I/O Channel Pin Assignment....................................................................................................................................... 2-3
2.3.3 I/O Channel Signal Description...................................................................................................................................2-4
2.3.4 Real-Time Clock and Non-Volatile RAM..................................................................................................................... 2-6
2.3.5 Timer.......................................................................................................................................................................... 2-6
2.4 SERIAL PORT ................................................................................................................................................................... 2-7
2.5 PARALLEL PORT..............................................................................................................................................................2-9
3. SETTING UP THE SYSTEM...................................................................................................................................3-1
3.1 OVERVIEW........................................................................................................................................................................ 3-1
3.2 SYSTEM SETTING............................................................................................................................................................3-2
3.2.1 CRT CONNECTOR (DB1)..........................................................................................................................................3-2
3.2.2 Watchdog Transferring Select (JP6)...........................................................................................................................3-2
3.2.3 Hard Disk (IDE) Connector......................................................................................................................................... 3-3
3.2.4 PC/104 Connector...................................................................................................................................................... 3-4
3.2.5 Keyboard Connector................................................................................................................................................... 3-6
3.2.6 FDD Port Connector (CN2)......................................................................................................................................... 3-7
3.2.7 Parallel Port Connector (CN3).................................................................................................................................... 3-7
3.2.8 Serial Port .................................................................................................................................................................. 3-8
3.2.9 PS/2 Mouse Connector ............................................................................................................................................ 3-10
3.2.10 External Speaker Header (J1).............................................................................................................................. 3-10
3.2.11 Reset Header (J8)................................................................................................................................................ 3-10
3.2.12 Power Connector (J9)........................................................................................................................................... 3-11
3.2.13 LED Header ......................................................................................................................................................... 3-11
3.2.14 CPU Setting ......................................................................................................................................................... 3-11
3.2.15 DRAM Configuration............................................................................................................................................. 3-15
3.2.16 D.O.C. Memory Address Select (SW1-7).............................................................................................................. 3-15
4. INSTALLATION......................................................................................................................................................4-1
4.1 OVERVIEW........................................................................................................................................................................ 4-1
4.2 UTILITY DISKETTE ...........................................................................................................................................................4-1
4.2.1 WIN 3.1 Driver............................................................................................................................................................4-2
4.2.2 WIN 95 Driver.............................................................................................................................................................4-2
4.2.3 WINNT Driver............................................................................................................................................................. 4-3
4.2.4 OS/2 Warp 3.0 Driver.................................................................................................................................................4-3
4.3 WATCHDOG TIMER..........................................................................................................................................................4-4
4.3.1 Watchdog Timer Setting.............................................................................................................................................4-4
4.3.2 Watchdog Transferring Select (JP6)...........................................................................................................................4-5
4.3.3 Watchdog Timer Enabled........................................................................................................................................... 4-5
4.3.4 Watchdog Timer Trigger............................................................................................................................................. 4-5
4.3.5 Watchdog Timer Disabled ..........................................................................................................................................4-6
5. BIOS CONSOLE ....................................................................................................................................................5-1
5.1 BIOS SETUP OVERVIEW.................................................................................................................................................. 5-1
5.2 STANDARD CMOS SETUP...............................................................................................................................................5-2
5.3 ADVANCED CMOS SETUP...............................................................................................................................................5-3
5.4 ADVANCED CHIPSET SETUP.......................................................................................................................................... 5-6
5.5 POWER MANAGEMENT................................................................................................................................................... 5-7
5.6 PCI/PLUG AND PLAY........................................................................................................................................................ 5-8
5.7 PERIPHERAL SETUP........................................................................................................................................................5-9
5.8 AUTO-DETECT HARD DISKS......................................................................................................................................... 5-10

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5.9 PASSWORD SETTING.................................................................................................................................................... 5-10
5.10 LOAD DEFAULT SETTING.......................................................................................................................................... 5-10
5.10.1 Auto Configuration with Optimal Setting................................................................................................................ 5-10
5.10.2 Auto Configuration with Fail Safe Setting.............................................................................................................. 5-10
5.11 BIOS EXIT.................................................................................................................................................................... 5-10
5.11.1 Save Settings and Exit ......................................................................................................................................... 5-10
5.11.2 Exit Without Saving .............................................................................................................................................. 5-11
5.12 BIOS UPDATE............................................................................................................................................................. 5-11
6. SPECIFICATIONS..................................................................................................................................................6-1
7. PLACEMENT & DIMENSIONS ..............................................................................................................................7-1
7.1 PLACEMENT.....................................................................................................................................................................7-1
7.2 DIMENSIONS ....................................................................................................................................................................7-2
8. PROGRAMMING RS-485 & INDEX .......................................................................................................................8-1
8.1 PROGRAMMING RS-485 ..................................................................................................................................................8-1
8.2 INDEX................................................................................................................................................................................ 8-3

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0.PREFACE
0.1 COPYRIGHT NOTICE AND DISCLAIMER
June 1999
Acrosser Technology makes no representations or warranties with respect to the contents hereof and specifically
disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, Acrosser
Technology reserves the right to revise this publication and to make changes from time to time in the contents
hereof without obligation of Acrosser Technology to notify any person of such revisions or changes.
Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid
written license from Acrosser or an authorized sublicensor.
(C) Copyright Acrosser Technology Co., Ltd., 1999. All rights Reserved.
No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated
into any language or computer language, in any form or any means, electronic, mechanical, magnetic, optical,
chemical, manual or otherwise, without the prior written consent of Acrosser Technology.
Acrosser, AMI, IBM PC/AT, SiS, AMD, Cyrix, Intel, Windows 3.1, Windows 95, Windows NT, OS/2 Warp, IDT
Winchip, …are registered trademarks.
All other trademarks and registered trademarks are the property of their respective holders.
This document was produced with Adobe Acrobat 3.01.
0.2 WELCOME TO THE AR-B1579 CPU BOARD
This guide introduces the Acrosser AR-B1579 CPU board.
Use the information describes this card’s functions, features, and how to start, set up and operate your AR-B1579.
You also could find general system information here.
0.3 BEFORE YOU USE THIS GUIDE
If you have not already installed this AR-B1579, refer to the Chapter 3, “Setting Up the System,” in this guide.
Check the packing list, ensure the all accessories in the package.
The AR-B1579 diskette provides the newest information about the card. Please refer to the README.DOC file
of the enclosed utility diskette. It contains the latest modification and hardware & software information, and
adding the description or modification of product function after manual published.
0.4 RETURNING YOUR BOARD FOR SERVICE
If your board requires servicing, contact the dealer from whom you purchased the product for service information.
If you need to ship your board to us for service, be sure it is packed in a protective carton. We recommend that
you keep the original shipping container for this purpose.
You can help assure efficient servicing of your product by following these guidelines:
1. Include your name, address, telephone and facsimile number where you may be reached during the day.
2. A description of the system configuration and/or software at the time is malfunction.
3. A brief description is in the symptoms.
0.5 TECHNICAL SUPPORT AND USER COMMENTS
Users’ comments are always welcome as they assist us in improving the usefulness of our products and the
comprehension of our publications. They form a very important part of the input used for product enhancement
and revision.
We may use and distribute any of the information you supply in any way we believe appropriate without incurring
any obligation. You may, of course, continue to use the information you supply.
If you have suggestions for improving particular sections or if you find any errors, please indicate the manual title
and book number.
Please send your comments to Acrosser Technology Co., Ltd. or your local sales representative.
Internet electronic mail to: [email protected]

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0.6 ORGANIZATION
This information for users covers the following topics (see the Table of Contents for a detailed listing):
! Chapter 1, “Overview”, provides an overview of the system features and packing list.
! Chapter 2, “System Controller”, describes the major structure.
! Chapter 3, “Setting Up the System”, describes how to adjust the jumpers and the connector settings.
! Chapter 4, “Installation”, describes setup procedures and information on the utility diskette.
! Chapter 5, “BIOS Console”, provides the BIOS options settings.
! Chapter 6, Specifications
! Chapter 7, Placement & Dimensions
! Chapter 8, Programming RS-485 & Index
0.7 STATIC ELECTRICITY PRECAUTIONS
Before removing the board from its anti-static bag, read this section about static electricity precautions.
Static electricity is a constant danger to computer systems. The charge that can build up in your body may be
more than sufficient to damage integrated circuits on any PC board. It is, therefore, important to observe basic
precautions whenever you use or handle computer components. Although areas with humid climates are much
less prone to static build-up, it is always best to safeguard against accidents may result in expensive repairs. The
following measures should generally be sufficient to protect your equipment from static discharge:
• Touch a grounded metal object to discharge the static electricity in your body (or ideally, wear a grounded
wrist strap).
• When unpacking and handling the board or other system component, place all materials on an antic static
surface.
• Be careful not to touch the components on the board, especially the “golden finger” connectors on the bottom
of every board.

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1. OVERVIEW
This chapter provides an overview of your system features and capabilities. The following topics are covered:
! Introduction
! Packing List
! Features
1.1 INTRODUCTION
The AR-B1579 makes 300MHz, industrial computing a reality. Developed for small size and high speeding
systems, this half-size ISA card is excellent for embedded applications due to its standalone.
Great speeds are attained through the PCI-driven IDE controllers. By providing a PCI interface to these two
controllers, the AR-B1579 offers an exciting option for engineers involved in high performance projects. Also, one
BIOS is available to interface peripherals quickly and easily. The system comes with 4MB V-RAM onboard, 512KB
synchronous pipe-line burst SRAM, one RS-232C and one RS-232C/RS-485 serial port, and two 72-pin SIMM
connectors which can support up to 128MB of DRAM.
The AR-B1579 is perfect for medical and telecommunications applications, factory floor networks, use as a MMIs
for high speeding processes, or a controller for graphics intensive systems.
1.2 PACKING LIST
The accessories are included with the system. Before you begin installing your AR-B1579 board, take a moment
to make sure that the following items have been included inside the AR-B1579 package.
! The quick setup manual
! 1 AR-B1579 CPU board
! 1 Hard disk drive interface cable for 3.5” HDD
! 1 Hard disk drive interface cable for 2.5” HDD
! 1 Floppy disk drive interface cable
! 1 Parallel port interface cable and 1 RS-232C interface cable mounted on one bracket
! 1 Keyboard adapter cable
! 1 USB device adapter cable
! 3 Software utility diskettes

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1.3 FEATURES
The system provides a number of special features that enhance its reliability, ensure its availability, and improve its
expansion capabilities, as well as its hardware structure.
! Half size Pentium grade signal board computer
! Supports from 75MHz to 300MHz Pentium CPUs
! Up to 128MB DRAM system
! Up to 512KB PBSRAM L2 cache system
! On-board CRT panel display
! Supports IDE hard disk drives
! Supports floppy disk drives
! Supports 1 bi-directional parallel port
! Supports 2 serial ports (RS-232C and RS-485)
! PC/AT compatible keyboard and PS/2 mouse interface
! Programmable watchdog timer
! Flash BIOS
! Built-in status LEDs indicator
! 5V/12V power requirement
! Multi-layer PCB for noise reduction
! Dimensions : 122mmX185mm

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2. SYSTEM CONTROLLER
This chapter describes the major structures of the AR-B1579 CPU board. The following topics are covered:
! DMA Controller
! Keyboard Controller
! Interrupt Controller
! Serial Port
! Parallel Port
2.1 DMA CONTROLLER
The equivalent of two 8237A DMA controllers are implemented in the AR-B1579 board. Each controller is the four-
channel DMA device that will generate the memory addresses and control signals necessary to transfer
information directly between a peripheral device and memory. This allows high speeding information transfer with less
CPU intervention. The two DMA controllers are internally cascaded to provide four DMA channels for transfers to
8-bit peripherals (DMA1) and three channels for transfers to 16-bit peripherals (DMA2). DMA2 channel 0 provides
the cascade interconnection between the two DMA devices, thereby maintaining IBM PC/AT compatibility.
The following is the system information of DMA channels:
DMA Controller 1 DMA Controller 2
Channel 0: Spare Channel 4: Cascade for controller 1
Channel 1: IBM SDLC Channel 5: Spare
Channel 2: Diskette adapter Channel 6: Spare
Channel 3: Spare Channel 7: Spare
Table 2-1 DMA Channel Controller
2.2 KEYBOARD CONTROLLER
The 8042 processor is programmed to support the keyboard serial interface. The keyboard controller receives
serial data from the keyboard, checks its parity, translates scan codes, and presents it to the system as a byte data
in its output buffer. The controller can interrupt the system when data is placed in its output buffer, or wait for the
system to poll its status register to determine when data is available.
Data can be written to the keyboard by writing data to the output buffer of the keyboard controller.
Each byte of data is sent to the keyboard controller in series with an odd parity bit automatically inserted. The
keyboard controller is required to acknowledge all data transmissions. Therefore, another byte of data will not be
sent to keyboard controller until acknowledgment is received for the previous byte sent. The “output buffer full”
interruption may be used for both send and receive routines.

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2.3 INTERRUPT CONTROLLER
The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1579 board. They
accept requests from peripherals, resolve priorities on pending interrupts in service, issue interrupt requests to the
CPU, and provide vectors which are used as acceptance indices by the CPU to determine which interrupt service
routine to execute.
The following is the system information of interrupt levels:
IRQ8 : Real time clock
IRQ9 : Rerouting to INT 0Ah from hardware IRQ
2
IRQ10 : spare
IRQ11 : spare
IRQ12 : spare (PS/2 mouse)
IRQ13 : Math. coprocessor
IRQ14 : Hard disk adapter
IRQ15 : Reserved for watchdog
InInterrupt Level
NMI
CTRL1
IRQ 0
IRQ 1
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
CTRL2
Parity check
Description
Serial port 2
Serial port 1
Spare
Floppy disk adapter
Parallel port 1
System timer interrupt from timer 8254
Keyboard output buffer full
Figure 2-1 Interrupt Controller

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2.3.1 I/O Port Address Map
Hex Range Device
000-01F DMA controller 1
020-021 Interrupt controller 1
022-023 SiS 5598 Chipset Address
040-04F Timer 1
050-05F Timer 2
060-06F 8042 keyboard/controller
070-071 Real-time clock (RTC), non-maskable interrupt (NMI)
080-09F DMA page registers
0A0-0A1 Interrupt controller 2
0C0-0DF DMA controller 2
0F0 Clear Math Co-processor
0F1 Reset Math Co-processor
0F8-0FF Math Co-processor
170-178 Fixed disk 1
1F0-1F8 Fixed disk 0
201 Game port
208-20A EMS register 0
218-21A EMS register 1
278-27F Parallel printer port 3 (LPT 3)
2E8-2EF Serial port 4 (COM 4)
2F8-2FF Serial port 2 (COM 2)
300-31F Prototype card/Streaming Type Adapter
378-37F Parallel printer port 2 (LPT 2)
380-38F SDLC, bisynchronous
3A0-3AF Bisynchronous
3B0-3BF Monochrome display and printer port 1 (LPT 1)
3C0-3CF EGA/VGA adapter
3D0-3DF Color/Graphics monitor adapter
3E8-3EF Serial port 3 (COM 3)
3F0-3F7 Diskette controller
3F8-3FF Serial port 1 (COM 1)
Table 2-2 I/O Port Address Map
2.3.2 I/O Channel Pin Assignment
I/O Pin Signal Name Input/Output I/O Pin Signal Name Input/Output
A1 -IOCHCK Input B1 GND Ground
A2 SD7 Input/Output B2 RSTDRV Output
A3 SD6 Input/Output B3 +5V Power
A4 SD5 Input/Output B4 IRQ9 Input
A5 SD4 Input/Output B5 -5V Power
A6 SD3 Input/Output B6 DRQ2 Input
A7 SD2 Input/Output B7 -12V Power
A8 SD1 Input/Output B8 -ZWS Input
A9 SD0 Input/Output B9 +12V Power
A10 IOCHRDY Input B10 GND Ground
A11 AEN Output B11 -MEMW Output
A12 SA19 Input/Output B12 -MEMR Output
A13 SA18 Input/Output B13 -IOW Input/Output
A14 SA17 Input/Output B14 -IOR Input/Output
A15 SA16 Input/Output B15 -DACK3 Output
A16 SA15 Input/Output B16 DRQ3 Input
A17 SA14 Input/Output B17 -DACK1 Output
A18 SA13 Input/Output B18 DRQ1 Input

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A19 SA12 Input/Output B19 -REFRESH Input/Output
A20 SA11 Input/Output B20 BUSCLK Output
A21 SA10 Input/Output B21 IRQ7 Input
A22 SA9 Input/Output B22 IRQ6 Input
A23 SA8 Input/Output B23 IRQ5 Input
A24 SA7 Input/Output B24 IRQ4 Input
A25 SA6 Input/Output B25 IRQ3 Input
A26 SA5 Input/Output B26 -DACK2 Output
A27 SA4 Input/Output B27 TC Output
A28 SA3 Input/Output B28 BALE Output
A29 SA2 Input/Output B29 +5V Power
A30 SA1 Input/Output B30 OSC Output
A31 SA0 Input/Output B31 GND Ground
Table 2-3 I/O Channel Pin Assignment
I/O Pin Signal Name Input/Output I/O Pin Signal Name Input/Output
C1 -SBHE Input/Output D1 -MEMCS16 Input
C2 LA23 Input/Output D2 -IOCS16 Input
C3 LA22 Input/Output D3 IRQ10 Input
C4 LA21 Input/Output D4 IRQ11 Input
C5 LA20 Input/Output D5 IRQ12 Input
C6 LA19 Input/Output D6 IRQ15 Input
C7 LA18 Input/Output D7 IRQ14 Input
C8 LA17 Input/Output D8 -DACK0 Output
C9 -MRD16 Input/Output D9 DRQ0 Input
C10 -MWR16 Input/Output D10 -DACK5 Output
C11 SD8 Input/Output D11 DRQ5 Input
C12 SD9 Input/Output D12 -DACK6 Output
C13 SD10 Input/Output D13 DRQ6 Input
C14 SD11 Input/Output D14 -DACK7 Output
C15 SD12 Input/Output D15 DRQ7 Input
C16 SD13 Input/Output D16 +5V Power
C17 SD14 Input/Output D17 -MASTER Input
C18 SD15 Input/Output D18 GND Ground
Table 2-4 I/O Channel Pin Assignment
2.3.3 I/O Channel Signal Description
Name Description
CLK [Output] The CLK signal of the I/O channel is asynchronous to
the CPU clock.
RSTDRV [Output] This signal goes high during power-up, low line-voltage
or hardware reset
SA0 - SA19
[Input / Output] The System Address lines run from bit 0 to 19. They are latched onto the falling edge of "BALE"
LA17 - LA23
[Input/Output] The Unlatched Address line run from bit 17 to 23
SD0 - SD15
[Input/Output] System Data bit 0 to 15
BALE [Output] The Buffered Address Latch Enable is used to latch SA0
- SA19 onto the falling edge. This signal is forced high
during DMA cycles
-IOCHCK [Input] The I/O Channel Check is an active low signal which
indicates that a parity error exist on the I/O board

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Name Description
IOCHRDY
[Input, Open collector] This signal lengthens the I/O, or memory read/write cycle, and should be held low with a valid address
IRQ 3-7, 9-12, 14, 15
[Input] The Interrupt Request signal indicates I/O service request attention. They are prioritized in the following
sequence : (Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5,
6, 7 (Lowest)
-IOR [Input/Output] The I/O Read signal is an active low signal which
instructs the I/O device to drive its data onto the data
bus
-IOW [Input/Output] The I/O write signal is an active low signal which
instructs the I/O device to read data from the data bus
-MRD16 [Output] The System Memory Read is low while any of the low 1
mega bytes of memory are being used
-MEMR
[Input/Output] The Memory Read signal is low while any memory location is being read
-MWR16 [Output] The System Memory Write is low while any of the low 1
mega bytes of memory is being written
-MEMW
[Input/Output] The Memory Write signal is low while any memory location is being written
DRQ 0-3, 5-7 [Input] DMA Request channels 0 to 3 are for 8-bit data
transfers. DMA Request channels 5 to 7 are for 16-bit
data transfers. DMA request should be held high until
the corresponding DMA has been completed. DMA
request priority is in the following sequence:(Highest)
DRQ 0, 1, 2, 3, 5, 6, 7 (Lowest)
-DACK 0-3, 5-7
[Output] The DMA Acknowledges 0 to 3, 5 to 7 are the corresponding acknowledge signals for DRQ 0 to 3 and
5 to 7
AEN [output] The DMA Address Enable is high when the DMA
controller is driving the address bus. It is low when the
CPU is driving the address bus
-REFRESH
[Input/Output] This signal is used to indicate a memory refresh cycle and can be driven by the microprocessor on the I/O
channel
TC [Output] Terminal Count provides a pulse when the terminal
count for any DMA channel is reached
SBHE [Input/Output] The System Bus High Enable indicates the high byte
SD8 - SD15 on the data bus
-MASTER [Input] The MASTER is the signal from the I/O processor which
gains control as the master and should be held low for a
maximum of 15 microseconds or system memory may
be lost due to the lack of refresh
-MEMCS16
[Input, Open collector] The Memory Chip Select 16 indicates that the present data transfer is a 1-wait state, 16-bit data memory
operation
-IOCS16
[Input, Open collector] The I/O Chip Select 16 indicates that the present data transfer is a 1-wait state, 16-bit data I/O operation
OSC [Output] The Oscillator is a 14.31818 MHz signal
ZWS
[Input, Open collector] The Zero Wait State indicates to the microprocessor that the present bus cycle can be completed without
inserting additional wait cycle
Table 2-5 I/O Channel Signal Description

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2.3.4 Real-Time Clock and Non-Volatile RAM
The AR-B1579 contains a real-time clock component that maintains the date and time in addition to storing
configuration information about the computer system. It contains 14 bytes of clock and control registers and 114
bytes of general purpose RAM. Because of using CMOS technology, it consumes very little power and can be
maintained for long period of time using an internal Lithium battery. The contents of each byte in the CMOS RAM
are listed as follows:
Address Description
00 Seconds
01 Second alarm
02 Minutes
03 Minute alarm
04 Hours
05 Hour alarm
06 Day of week
07 Date of month
08 Month
09 Year
0A Status register A
0B Status register B
0C Status register C
0D Status register D
0E Diagnostic status byte
0F Shutdown status byte
10 Diskette drive type byte, drive A and B
11 Fixed disk type byte, drive C
12 Fixed disk type byte, drive D
13 Reserved
14 Equipment byte
15 Low base memory byte
16 High base memory byte
17 Low expansion memory byte
18 High expansion memory byte
19-2D Reserved
2E-2F 2-byte CMOS checksum
30 Low actual expansion memory byte
31 High actual expansion memory byte
32 Date century byte
33 Information flags (set during power on)
34-7F Reserved for system BIOS
Table 2-6 Real-Time Clock & Non-Volatile RAM
2.3.5 Timer
The AR-B1579 provides three programmable timers, each with a timing frequency of 1.19 MHz.
Timer 0 The output of this timer is tied to interrupt request 0. (IRQ 0)
Timer 1 This timer is used to trigger memory refresh cycles.
Timer 2 This timer provides the speaker tone.
Application programs can load different counts into this timer to generate various sound frequencies.

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2.4 SERIAL PORT
The ACEs (Asynchronous Communication Elements ACE1 to ACE4) are used to convert parallel data to a serial
format on the transmit side and convert serial data to parallel on the receiver side. The serial format, in order of
transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one,
one and half (five-bit format only) or two stop bits. The ACEs are capable of handling divisors of 1 to 65535, and
produce a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this 16x clock to drive the receiver logic. Also included in the ACE a completed
MODEM control capability, and a processor interrupt system that may be software tailored to the computing time
required handle the communications link.
The following table is summary of each ACE accessible register
DLAB Port Address Register
Receiver buffer (read)0 base + 0 Transmitter holding register (write)
0 base + 1 Interrupt enable
X base + 2 Interrupt identification (read only)
X base + 3 Line control
X base + 4 MODEM control
X base + 5 Line status
X base + 6 MODEM status
X base + 7 Scratched register
1 base + 0 Divisor latch (least significant byte)
1 base + 1 Divisor latch (most significant byte)
Table 2-7 ACE Accessible Registers
(1) Receiver Buffer Register (RBR)
Bit 0-7: Received data byte (Read Only)
(2) Transmitter Holding Register (THR)
Bit 0-7: Transmitter holding data byte (Write Only)
(3) Interrupt Enable Register (IER)
Bit 0: Enable Received Data Available Interrupt (ERBFI)
Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI)
Bit 2: Enable Receiver Line Status Interrupt (ELSI)
Bit 3: Enable MODEM Status Interrupt (EDSSI)
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(4) Interrupt Identification Register (IIR)
Bit 0: “0” if Interrupt Pending
Bit 1: Interrupt ID Bit 0
Bit 2: Interrupt ID Bit 1
Bit 3: Must be 0
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0

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(5) Line Control Register (LCR)
Bit 0: Word Length Select Bit 0 (WLS0)
Bit 1: Word Length Select Bit 1 (WLS1)
WLS1 WLS0 Word Length
0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits
Bit 2: Number of Stop Bit (STB)
Bit 3: Parity Enable (PEN)
Bit 4: Even Parity Select (EPS)
Bit 5: Stick Parity
Bit 6: Set Break
Bit 7: Divisor Latch Access Bit (DLAB)
(6) MODEM Control Register (MCR)
Bit 0: Data Terminal Ready (DTR)
Bit 1: Request to Send (RTS)
Bit 2: Out 1 (OUT 1)
Bit 3: Out 2 (OUT 2)
Bit 4: Loop
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(7) Line Status Register (LSR)
Bit 0: Data Ready (DR)
Bit 1: Overrun Error (OR)
Bit 2: Parity Error (PE)
Bit 3: Framing Error (FE)
Bit 4: Break Interrupt (BI)
Bit 5: Transmitter Holding Register Empty (THRE)
Bit 6: Transmitter Shift Register Empty (TSRE)
Bit 7: Must be 0
(8) MODEM Status Register (MSR)
Bit 0: Delta Clear to Send (DCTS)
Bit 1: Delta Data Set Ready (DDSR)
Bit 2: Training Edge Ring Indicator (TERI)
Bit 3: Delta Receive Line Signal Detect (DSLSD)
Bit 4: Clear to Send (CTS)
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)

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(9) Divisor Latch (LS, MS)
LS MS
Bit 0: Bit 0 Bit 8
Bit 1: Bit 1 Bit 9
Bit 2: Bit 2 Bit 10
Bit 3: Bit 3 Bit 11
Bit 4: Bit 4 Bit 12
Bit 5: Bit 5 Bit 13
Bit 6: Bit 6 Bit 14
Bit 7: Bit 7 Bit 15
Desired Baud Rate Divisor Used to Generate 16x Clock
300 384
600 192
1200 96
1800 64
2400 48
3600 32
4800 24
9600 12
14400 8
19200 6
28800 4
38400 3
57600 2
115200 1
Table 2-8 Serial Port Divisor Latch
2.5 PARALLEL PORT
(1) Register Address
Port Address Read/Write Register
base + 0 Write Output data
base + 0 Read Input data
base + 1 Read Printer status buffer
base + 2 Write Printer control latch
Table 2-9 Registers’ Address
(2) Printer Interface Logic
The parallel portion of the SMC37C669 makes the attachment of various devices that accept eight bits of parallel
data at standard TTL level.
(3) Data Swapper
The system microprocessor can read the contents of the printer’s Data Latch through the Data Swapper by reading
the Data Swapper address.

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(4) Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the Printer Status Buffer. The bit
definitions are described as follows:
XXX
12345670
-ERROR
SLCT
PE
-ACK
-BUSY
Figure 2-2 Printer Status Buffer
NOTE: X presents not used.
Bit 7: This signal may become active during data entry, when the printer is off-line during printing, or when the
print head is changing position or in an error state. When Bit 7 is active, the printer is busy and can not
accept data.
Bit 6: This bit represents the current state of the printer’s ACK signal. A0 means the printer has received the
character and is ready to accept another. Normally, this signal will be active for approximately 5
microseconds before receiving a BUSY message stops.
Bit 5: A1 means the printer has detected the end of the paper.
Bit 4: A1 means the printer is selected.
Bit 3: A0 means the printer has encountered an error condition.

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(5) Printer Control Latch & Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the address of printer
control swapper. Bit definitions are as follows:
XX
12345670
STROBE
AUTO FD XT
INIT
SLDC IN
IRQ ENABLE
DIR(write only)
Figure 2-3 Bit’s Definition
NOTE: X presents not used.
Bit 5: Direction control bit. When logic 1, the output buffers in the parallel port are disabled allowing data driven
from external sources to be read; when logic 0, they work as a printer port. This bit is write only.
Bit 4: A1 in this position allows an interrupt to occur when ACK changes from low state to high state.
Bit 3: A1 in this bit position selects the printer.
Bit 2: A0 starts the printer (50 microseconds pulse, minimum).
Bit 1: A1 causes the printer to line-feed after a line is printed.
Bit 0: A0.5 microsecond minimum highly active pulse clocks data into the printer. Valid data must be present for
a minimum of 0.5 microseconds before and after the strobe pulse.