ADLINK Technology PXIe-3935 User manual

Advance Technologies; Automate the World.
PXIe-3935
PXIe Express Embedded Controller
User’s Manual
Manual Rev.: 2.00
Revision Date: Mar. 24, 2017
Part No: 50-17052-1000

ii
Revision History
Revision Release Date Description of Change(s)
2.00 2017/3/24 Initial Release

Preface iii
PXIe-3935
Preface
Copyright 2017 ADLINK TECHNOLOGY, INC.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the Euro-
pean Union's Restriction of Hazardous Substances (RoHS) direc-
tive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manu-
facturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.

iv Preface
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
NOTE:
NOTE:
Additional information, aids, and tips that help users per-
form tasks.
CAUTION:
Information to prevent minor physical injury, component
damage, data loss, and/or program corruption when try-
ing to complete a task.
WARNING:
Information to prevent serious physical injury, compo-
nent damage, data loss, and/or program corruption
when trying to complete a specific task.

Table of Contents v
PXIe-3935
Table of Contents
Revision History.......................................................................ii
Preface.................................................................................... iii
List of Figures....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 2
1.2 Specifications....................................................................... 3
1.3 Front Panel I/O & Indicators ................................................ 7
1.3.1 PXIe Trigger Connector..............................................8
1.3.2 DisplayPort Connectors..............................................9
1.3.3 GPIB Connector .......................................................10
1.3.4 Reset Button.............................................................11
1.3.5 LED Indicators..........................................................11
1.3.6 USB 2.0 Ports...........................................................12
1.3.7 Gigabit Ethernet Ports..............................................13
1.3.8 COM Port..................................................................14
1.3.9 USB 3.0 Ports...........................................................15
1.3.10 Onboard Connections and Settings..........................16
2 Getting Started ................................................................. 17
2.1 Package Contents ............................................................. 17
2.2 Operating System Installation............................................ 17
2.2.1 Driver Installation......................................................19
2.2.2 Installation Environment...........................................19
2.2.3 Installing the PXIe-3935 ...........................................21
2.2.4 Replacing the Hard Drive or Solid State Drive .........22
2.2.5 Replacing the Battery Backup..................................23

vi Table of Contents
2.2.6 Clearing CMOS.........................................................23
2.2.7 Initiating Backup BIOS Flash....................................24
A Appendix: PXIe Trigger I/O Function Reference............ 25
A.1 Data Types......................................................................... 25
A.2 Function Library................................................................. 26
A.2.1 TRIG_Init ..................................................................26
A.2.2 TRIG_Close..............................................................27
A.2.3 TRIG_SetSoftTrg......................................................27
A.2.4 TRIG_Trigger_Route................................................28
A.2.5 TRIG_Trigger_Clear.................................................30
A.2.6 TRIG_GetSoftTrg......................................................31
A.2.7 TRIG_Trigger_Route_Query ....................................31
A.2.8 TRIG_GetDriverRevision..........................................33
B Appendix: BIOS Setup...................................................... 35
B.1 Starting the BIOS............................................................... 35
B.2 Main Setup......................................................................... 37
B.3 Advanced Setup................................................................. 37
B.4 Boot Setup......................................................................... 38
B.5 Security Setup.................................................................... 38
B.6 Save & Exit Setup.............................................................. 39
Important Safety Instructions.............................................. 41
Getting Service..................................................................... 45

List of Figures vii
PXIe-3935
List of Figures
Figure 1-1: PXIe-3935 Functional Block Diagram..............................3
Figure 1-2: Front Panel......................................................................7
Figure 1-3: PXIe Trigger SMB Jack ...................................................8
Figure 1-4: LED Indicators...............................................................11
Figure 1-5: COM Port.......................................................................14
Figure 1-6: PXIe-3985 Onboard Configuration ................................16

viii List of Figures
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List of Tables ix
PXIe-3935
List of Tables
Table 1-1: Display Port Pin Assignment .........................................10
Table 1-2: GPIB Pin Description.....................................................11
Table 1-3: LED Indicator Legend....................................................12
Table 1-4: USB 2.0 Port Pin Assignment........................................13
Table 1-5: PXIe-3935 Ethernet Port Pin Assignments....................13
Table 1-6: D-Sub 9p COM Port Signal Functions...........................15
Table 1-7: Onboard Configuration Legend .....................................16
Table B-1: BIOS Hot Key Functions................................................36
Table B-2: BIOS Main Setup Menu.................................................37
Table B-3: BIOS Advanced Setup Menu.........................................38
Table B-4: BIOS Boot Setup Menu .................................................38
Table B-5: BIOS Security Setup Menu............................................39

x List of Tables
This page intentionally left blank.

Introduction 1
PXIe-3935
1 Introduction
The ADLINK PXIe-3935 PXI Express embedded controller, based
on the Intel® Celeron® 2000E 2.2GHz processor, pairs superior
performance with an unprecedented price point. Specifically con-
ceived for hybrid PXI Express-based testing systems, the ADLINK
PXIe-3935 delivers a rugged and stable platform for a wide variety
of testing and measurement applications.
The PXIe-3935 provides ample interface flexibility, including two
DisplayPort connectors, allowing connection to two monitors, dual
USB 3.0 connections for high speed peripheral devices, dual
Gigabit Ethernet ports with one for LAN connection and the other
for controlling LXI instruments, four USB 2.0 ports for peripheral
devices and USB instrument control, a Micro-D GPIB connector
for GPIB instrument connection, and one RS-232/422/485 D-
SUB9 connector for hybrid PXI-based testing systems control.
ADLINK's PXIe-3935 significantly reduces maintenance burdens
with easily replaceable battery and upgradable storage and
SODIMM modules. Backup BIOS also eases recovery in the event
of a main BIOS crash.
NOTE:
NOTE:
Memory addressing over 4GB is OS-dependent, such that a
32-bit operating system may be unable to address memory
space over 4GB. To fully utilize memory, 64-bit operating sys-
tems are required.

2 Introduction
1.1 Features
Ideal balance between performance and price point
Intel® Celeron® 2000E 2.2GHz processor
Dual channel DDR3L SODIMM up to 16GB 1600MHz
8 GB/s maximum system throughput
Dual display port support
2.5" HDD or SSD support
SATA 3Gb/s
AHCI support
Integrated I/O
Dual Gigabit Ethernet ports
Two USB3.0 Ports
Four USB 2.0 Ports
Built-in GPIB (IEEE488) controller
Dual DisplayPort connector
One COM port (D-sub9 serial)
Trigger I/O for advanced PXITM trigger functions
Dual BIOS support for backup

Introduction 3
PXIe-3935
1.2 Specifications
Figure 1-1: PXIe-3935 Functional Block Diagram
Processor
Intel® Celeron® 2000E 2.20GHz processor for maximum
computing power
DMI (Direct Media Interface) with 5 GT/s of bandwidth in
each direction
Front Panel
Connectors
GPIB
USB 2.0 x4
GbE
GbE
COM port
SMB
DisplayPort x2
USB 3.0 x2
GPIB GPIB controller
GPIB controller
I210
Digital
Display I/F
USB 2.0
USB 3.0
SATA
LPC-COM Port
Trigger Signal Trigger Bus
Controller
Trigger Bus
Gen2 2Links x8 +
x16
Gen2 4Links x4
PXIe Connector
PCIe Gen2.0
48 Ianes
swtich
LPC PCIe x1
PCH
HM86
GbE PHY
I217
PCIe x1
Intel FDI DMI
PCIe Gen2 x16
DDR3
1600MHz
DDR3
1600MHz
PCIe x1
PCIe x1
Channel A
SODIMM
Channel B
SODIMM
Haswell Intel
Celeron 2000E
2.5” SATA
Interposer
Board
GbE I/F
GbE I/F
or

4 Introduction
Chipset
Mobile Intel®HM86
Memory
2x standard 204-pin DDR3L SODIMM sockets
Support for 1333/1600MHz RAM up to 16 GB total
Support for non-ECC unbuffered memory
Video
DisplayPort supports up to 3840x 2160 @60Hz resolution
DVI (with passive DisplayPort-to-DVI adapter) supports res-
olutions up to 1920 x 1200 @60Hz
Hard Drive
Built-in 2.5” 500GB SATA hard drive or 240GB SATA solid state
hard drive.
I/O Connectivity
Dual Gigabit Ethernet through two RJ-45 connectors with speed/
link/active LED indicators on the front panel, with both supporting
Wake on LAN.
NOTE:
NOTE:
The externally accessible SODIMM socket can accept replace-
ment DDR3L DRAM DIMM modules. PXIe-3935 specifications
and stability guarantees are only supported when ADLINK-pro-
vided DDR3L DRAM DIMM modules are used.
NOTE:
NOTE:
DisplayPort adapters for other standards are supported, with
maximum available resolution dependent on the adapter cho-
sen

Introduction 5
PXIe-3935
USB
Four USB 2.0 and two USB 3.0 ports on the front panel.
COM port
One RS-232/422/485 D-SUB9 connector.
GPIB
Onboard IEEE488 GPIB controller through Micro-D 25-pin con-
nector on the front panel.
Trigger I/O
One SMB connector on the front panel to route an external trigger
signal to/from PXIe trigger bus
Dimensions (3U PXI module)
3U/4-slot PXI standard.
80.94 W x 128.7 H x 212.9 D mm (3.15 x 5.01 x 8.3 in.)
Weight
1.0kg (exclusive of packaging)
Environmental
Shock and Vibration
Functional shock 30 G, half-sine, 11 ms pulse duration
Operating temperature with SSD 0 to 55°C
Operating temperature with HDD 0 to 50°C
Storage temperature -20 to 70°C
Relative humidity , non-condensing 5 to 95%

6 Introduction
Random vibration:
Operating 5 to 500 Hz, 0.21 Grms, 3 axes
Non-operating 5 to 500 Hz, 2.46 Grms, 3 axes
Certification
Electromagnetic compatibility:
EMC/EMI: CE, FCC Class A
CE Compliance EN 61326-1
The PXIe-3935 meets the essential requirements of applicable
European Directives.
Power Requirements
NOTE:
NOTE:
Environmental & Shock and Vibration values are only guaran-
teed with use of an ADLINK-provided SSD/HDD
Voltage Rail +3.3V +5V +12V Total (W)
Maximum power consumption 3.3 38 1.2 42.5
Idle power consumption 3.3 22.5 1.2 27

Introduction 7
PXIe-3935
1.3 Front Panel I/O & Indicators
Figure 1-2: Front Panel

8 Introduction
The PXIe-3935 provides the following I/O and indicators, as
labeled on the front panel.
PXI Trigger Connector (SMB jack)
2X DisplayPort Connectors
GPIB Connector (Micro D-Sub 25P)
Reset Button
LED indicators
4X Type-A USB 2.0
connectors
2X Gigabit Ethernet
2X USB 3.0
1X COM port (D-sub9 serial)
1.3.1 PXIe Trigger Connector
Figure 1-3: PXIe Trigger SMB Jack
The PXIe trigger connector is a SMB jack, used to route external
trigger signals to or from the PXIe backplane. Trigger signals are
TTL-compatible and edge sensitive. The PXIe-3935 provides four
Trigger
Ground

Introduction 9
PXIe-3935
trigger routing modes from/to the PXIe trigger connector to syn-
chronize PXIe modules, including
From a selected trigger bus line to PXIe trigger connector
From the PXIe trigger connector to a selected trigger bus
line
From software trigger to a selected trigger bus line
From software trigger to PXIe trigger connector
All trigger modes are programmable by the provided driver. Please
refer to Section A: PXIe Trigger I/O Function Reference for further
information.
1.3.2 DisplayPort Connectors
Supporting monitor connection, with, if connecting to VGA/DVI/
HDMI monitors, installation of requisite adapters required. Dual
display function is also supported
.
Pin Signal Pin Signal
1 CN_DDPx0+ 11 GND
2 GND 12 CN_DDPx3-
3 CN_DDPx0- 13 CN_DDPx_AUX_SEL
4 CN_DDPx1+ 14 CN_DDPx_CONFIG2
5 GND 15 CN_DDPx_AUX+
19 1
2
20

10 Introduction
Table 1-1: Display Port Pin Assignment
1.3.3 GPIB Connector
The GPIB connector on PXIe-3935 is a micro D-sub 25P connec-
tor, controlling external bench-top instruments. Connection to
other instruments requires the ACL-IEEE488-MD1-A cable. The
on-board GPIB controller provides:
Full compatibility with IEEE 488 standard
Up to 1.5MB/s data transfer rates
Onboard 2 KB FIFO for read/write operations
Driver APIs compatible with NI-488.2 driver software
Connection with up to 14 instruments
6 CN_DDPx1- 16 GND
7 CN_DDPx2+ 17 CN_DDPx_AUX-
8 GND 18 CN_DDPx_HPD
9 CN_DDPx2- 19 GND
10 CN_DDPx3+ 20 +V3.3_DDPx_PWR
Pin Signal Description Pin Signal Description
1 DIO1# GPIB Data 1 14 DIO5# GPIB Data 5
2 DIO2# GPIB Data 2 15 DIO6# GPIB Data 6
Pin Signal Pin Signal
113
14 25