ADLINK Technology PXIe-3987 User manual

Leading EDGE COMPUTING
PXIe-3987/3977/3937
PXI Express Embedded Controller
User’s Manual
Manual Rev.: 1.1
Revision Date: December 24, 2019
Part No: 50-17056-1010

ii Revision History
Leading EDGE COMPUTING
Revision History
Revision Release Date Description of Change(s)
1.00 2019-10-22 Initial release
1.1 2019-12-24
Add support for Intel® Core™ i5-
7440EQ/i3-7100E processors; update
BIOS and driver sections

Preface iii
PXIe-3987/3977/3937
Preface
Copyright © 2019 ADLINK Technology Inc.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect,
special, incidental, or consequential damages arising out of the
use or inability to use the product or documentation, even if
advised of the possibility of such damages.
ADLINK is committed to fulfill its social responsi-
bility to global environmental preservation
through compliance with the European Union's
Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have
enforced measures to ensure that our products,
manufacturing processes, components, and raw
materials have as little impact on the environment as possible.
When products are at their end of life, our customers are encour-
aged to dispose of them in accordance with the product disposal
and/or recovery programs prescribed by their nation or company.
Battery Labels (for products with battery)
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iv Preface
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California Proposition 65 Warning
WARNING: This product can expose you to chemicals
including acrylamide, arsenic, benzene, cadmium,
Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox-
ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and
vinyl materials, which are known to the State of California to cause
cancer, and acrylamide, benzene, cadmium, lead, mercury,
phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and
vinyl materials, which are known to the State of California to cause
birth defects or other reproductive harm. For more information go
to www.P65Warnings.ca.gov.
Trademarks
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
NOTE:
NOTE:
Additional information, aids, and tips that help users perform
tasks.
CAUTION:
Information to prevent minor physical injury, component dam-
age, data loss, and/or program corruption when trying to com-
plete a task.
WARNING:
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.

Table of Contents v
PXIe-3987/3977/3937
Table of Contents
Revision History...................................................................... ii
Preface.................................................................................... iii
Table of Contents.................................................................... v
List of Figures........................................................................ ix
List of Tables.......................................................................... xi
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 2
1.2 Specifications....................................................................... 3
1.3 I/O and Indicators ................................................................ 7
1.3.1 Front Panel ................................................................. 7
1.3.2 GPIB Connector ....................................................... 10
1.3.3 Reset Button............................................................. 11
1.3.4 LED Indicators .......................................................... 11
1.3.5 USB 2.0 Ports........................................................... 12
1.3.6 Gigabit Ethernet Ports .............................................. 13
1.3.7 USB 3.0 Ports........................................................... 14
1.3.8 COM Port.................................................................. 14
1.3.9 Onboard Connections and Settings.......................... 15
2 Getting Started ................................................................. 17
2.1 Package Contents ............................................................. 17
2.2 Operating System Installation............................................ 18
2.2.1 Installation Environment ........................................... 19
2.2.2 Installing the PXIe-3987/3977/3937 ......................... 20
2.2.3 Replacing the Hard Drive or Solid State Drive ......... 23
2.2.4 Replacing the Battery Backup .................................. 24

vi Table of Contents
Leading EDGE COMPUTING
2.2.5 Clearing CMOS......................................................... 25
3 Driver Installation.............................................................. 27
A Appendix: PXI Trigger I/O Functions...............................29
A.1 Data Types......................................................................... 29
A.2 Function Library ................................................................. 31
A.2.1 TRIG_Init .................................................................. 31
A.2.2 TRIG_Close .............................................................. 31
A.2.3 TRIG_SetSoftTrg ...................................................... 32
A.2.4 TRIG_Trigger_Route ................................................ 33
A.2.5 TRIG_Trigger_Clear ................................................. 35
A.2.6 TRIG_GetSoftTrg...................................................... 35
A.2.7 TRIG_Trigger_Route_Query .................................... 36
A.2.8 TRIG_GetDriverRevision .......................................... 38
B Appendix: BIOS Setup.......................................................39
B.1 Entering the BIOS .............................................................. 39
B.2 Navigation .......................................................................... 40
B.3 Menu Structure .................................................................. 41
B.4 Main ................................................................................... 42
B.4.1 BIOS Information ...................................................... 42
B.4.2 Processor Information............................................... 42
B.4.3 PCH Information ....................................................... 43
B.4.4 System Management................................................ 43
B.4.5 System Date and Time ............................................. 46
B.5 Advanced ........................................................................... 47
B.5.1 CPU Configuration.................................................... 47
B.5.2 Memory Configuration .............................................. 49
B.5.3 Graphics Configuration ............................................. 49
B.5.4 USB Configuration .................................................... 50
B.5.5 TPM 2.0 Configuration.............................................. 51
B.5.6 Onboard Devices Configuration................................ 52

Table of Contents vii
PXIe-3987/3977/3937
B.5.7 PCI and PCIe Configuration ..................................... 53
B.5.8 Advanced Power Management ............................... 53
B.5.9 Network Stack Configuration .................................... 54
B.5.10 Hardware Health Configuration ................................ 54
B.5.11 PXIe Links Control Configuration ............................. 54
B.6 Security.............................................................................. 55
B.6.1 Secure Boot.............................................................. 55
B.7 Boot ................................................................................... 56
B.7.1 CSM.......................................................................... 57
B.7.2 UEFI Hard Disk Drive BBS Priorities ........................ 57
B.8 Save & Exit ........................................................................ 58
C Appendix: Dual BIOS........................................................59
D Appendix: Legacy Boot Mode Settings...........................61
Important Safety Instructions.............................................. 63
Getting Service...................................................................... 65

viii Table of Contents
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List of Figures ix
PXIe-3987/3977/3937
List of Figures
Figure 1-1: Functional Block Diagram................................................ 3
Figure 1-2: Front Panel ...................................................................... 7
Figure 1-3: PXI Trigger SMB Jack ..................................................... 8
Figure 1-4: DisplayPort Connector..................................................... 9
Figure 1-5: GPIB Connector............................................................. 10
Figure 1-6: LED Indicators ............................................................... 11
Figure 1-7: COM Port....................................................................... 14
Figure 1-8: Onboard Configuration .................................................. 15
Figure B-1: BIOS Setup Navigation.................................................. 40

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List of Tables xi
PXIe-3987/3977/3937
List of Tables
Table 1-1: Front Panel Legend ......................................................... 7
Table 1-2: DisplayPort Pin Assignment ............................................ 9
Table 1-3: GPIB Pin Description ..................................................... 10
Table 1-4: LED Indicator Legend .................................................... 11
Table 1-5: USB 2.0 Port Pin Assignment........................................ 12
Table 1-6: Ethernet Port Pin Assignments...................................... 13
Table 1-7: Ethernet Status LED Descriptions ................................. 13
Table 1-8: D-sub COM Port Signal Functions................................. 14
Table 1-9: Onboard Configuration Legend ..................................... 15
Table B-1: BIOS Hot Key Functions................................................ 40

xii List of Tables
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Introduction 1
PXIe-3987/3977/3937
1 Introduction
The ADLINK PXIe-3987/3977/3937 PXI Express embedded con-
troller is based on the seventh generation Intel®Core™ processor
specifically designed for PXI Express-based testing systems. A
rugged and stable operating environment is provided for a variety
of testing and measurement applications.
Combining state-of-the-art Intel®Core™ processors and up to
32GB of DDR4 2400MHz memory, the PXIe-3987/3977/3937 uti-
lizes multiple computing engines on a single processor, enabling
execution of four independent tasks simultaneously. With a config-
urable PCIe switch, the PXIe-3987/3977/3937 can support four
links x4 or two links x8 x16 PXI Express link capability, with maxi-
mum system throughput of up to 16 GB/s (PCI Express 3.0).
PXI Express-based testing systems typically make up a PXI
Express platform and diversified standalone instruments for com-
plex testing tasks. The PXIe-3987/3977/3937 series provides
ample interfaces, including two DisplayPort connectors, allowing
connection to two monitors, dual USB 3.0 connections for high
speed peripheral devices, dual Gigabit Ethernet ports, one for LAN
connection and the other for controlling LXI instruments, four USB
2.0 ports for peripheral devices and USB instrument control, an
SMB connector for configurable input/output routing of signal to/
from PXI Trigger Bus on PXI Express chassis, and a Micro-D
GPIB connector for GPIB instrument connection, for hybrid PXI-
based testing system control.
NOTE:
NOTE:
Memory addressing over 4 GB is OS-dependent, such that a
32-bit operating system may be unable to address memory
space over 4GB. To fully utilize memory, 64-bit operating sys-
tems are required.

2Introduction
Leading EDGE COMPUTING
1.1 Features
PXI-5 PXI Express Hardware Specification Rev.1.0
7th Generation Intel®Core™ processors
PXIe-3987: Intel® Core™ i7-7820EQ 3.0/3.7 GHz
(Turbo), 45W/35W (cTDP, 4C/GT2)
PXIe-3977: Intel® Core™ i5-7440EQ 2.9/3.6 GHz
(Turbo), 45W/35W (cTDP, 4C/GT2)
PXIe-3937: Intel® Core™ i3-7100E 2.9 GHz,
35W (2C/GT2)
Dual Channel DDR4 SO-DIMM
Up to 32 GB 2400 MHz
Maximum System Throughput 16 GB/s
PXI Express Link Capability
4-link Configuration: x4 x4 x4 x4
2-link Configuration: x16 x8
Preinstalled 240 GB SATA SSD
Supports 2.5” HDD or SSD
SATA 6.0 Gb/s
Supports AHCI
Integrated I/O
Dual Gigabit Ethernet ports
Two USB 3.0 Ports
Four USB 2.0 Ports
Built-in GPIB (IEEE488) controller
Dual DisplayPort connectors
One COM port (D-sub9 serial)
Trigger I/O for advanced PXITM trigger functions
OS
Microsoft Windows 10 64-bit

Introduction 3
PXIe-3987/3977/3937
1.2 Specifications
Figure 1-1: Functional Block Diagram
Processor
7th Generation Intel®Core™ processor
DMI (Direct Media Interface) 3.0 with 8 GT/s bandwidth in
each direction
Chipset
Mobile Intel®QM175/HM175 chipset
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4Introduction
Leading EDGE COMPUTING
Memory
Two standard 260-pin DDR4 SO-DIMM sockets
Supports 2133/2400 MHz RAM up to 32 GB total
Supports non-ECC, unbuffered memory
Video
DisplayPort resolution up to 3840 x 2160 @ 60 Hz
DVI (with passive DisplayPort-to-DVI adapter) resolution up
to 1920 x 1200 @ 60 Hz
Storage
Built-in 2.5” 500 GB SATA hard drive or 240 GB SATA solid state
hard drive.
Ethernet Connectivity
Dual Gigabit Ethernet controllers through two RJ-45 connectors
with speed/link/active LED on the faceplate, with both supporting
Wake on LAN.
USB
Four USB 2.0 and two USB 3.0 ports on the faceplate.
GPIB
Onboard IEEE488 GPIB controller through Micro-D 25-pin con-
nector on the faceplate.
NOTE:
NOTE:
The externally accessible SO-DIMM socket can accept
replacement DDR4 DRAM DIMM modules.
PXIe-3987/3977/3937 specifications and stability guarantees
are only supported when ADLINK-provided DDR4 DRAM SO-
DIMM modules are used.
NOTE:
NOTE:
DisplayPort adapters for other standards are available, with
maximum available resolution dependent on the adapter

Introduction 5
PXIe-3987/3977/3937
Trigger I/O
One SMB connector on the faceplate to route an external trigger
signal to/from PXI trigger bus.
Dimensions (3U PXI module)
3U/4-slot PXI standard
Weight
1.0 kg (exclusive of packaging)
Environmental
Shock and Vibration
Functional shock 30 G, half-sine, 11 ms pulse duration
Random vibration:
Operating: 5 to 500 Hz, 0.21 Grms, 3 axes
Non-operating: 5 to 500 Hz, 2.46 Grms, 3 axes
Condition Range
Operating temperature with SSD 0 to 55°C
Operating temperature with HDD 0 to 50°C
Storage temperature -20 to 70°C
Relative humidity, non-condensing 5 to 95%
NOTE:
NOTE:
Environmental, shock, and vibration values are only valid with
use of an ADLINK-provided SSD/HDD

6Introduction
Leading EDGE COMPUTING
Certifications
Electromagnetic compatibility:
EN 61326-1 (IEC 61326-1): Class A emissions; Basic
immunity
EN 55011 (CISPR 11): Group 1, Class A emissions
EN 55032 2015/AC: 2016 Class A
EN 55032 2015/AC: 2016 Class B
EN 55024 2010+ A1: 2015
EN 61000-3-2:2014: Class A
EN 61000-3-3:2013: Class A
EN 55024:2010+A1:2015: Immunity
FCC 47 CFR Part 15 Subpart A (Class A)
FCC 47 CFR Part 15 Subpart B (Class B)
ICES-001 Class A
ICES-003 Issue 6-2016
AS/NZS CISPR 11: Group 1, Class A emissions
AS/NZS CISPR 32: 2015 (Ed 2.0)/C1:2016: Class B
The PXIe-3987/3977/3937 meets the essential requirements of
applicable European Directives.
Power Requirements
Typical Consumption DC +3.3V DC +5V DC +12V
Typical operation
(Measured while W10 is idle) 5A 2.5A 2A
Heavy operation
(Measured while W10 is under heavy
CPU and storage utilization)
5A 2.8A 8A

Introduction 7
PXIe-3987/3977/3937
1.3 I/O and Indicators
1.3.1 Front Panel
Figure 1-2: Front Panel
Table 1-1: Front Panel Legend
AReset Button FGPIB Connector
(Micro D-Sub 25P)
B2X DisplayPort G2X Gigabit Ethernet
C2X USB 3.0 HPXI Trigger
D4X Type-A USB 2.0 ILED indicators
ECOM port (D-sub9 serial)
A
C
G
B
D
F
H
E
I

8Introduction
Leading EDGE COMPUTING
PXI Trigger Connector
Figure 1-3: PXI Trigger SMB Jack
The PXI trigger connector is an SMB jack, used to route external
trigger signals to or from the PXI backplane. Trigger signals are
TTL-compatible and edge sensitive. The PXIe-3987/3977/3937
provides four trigger routing modes from/to the PXI trigger connec-
tor to synchronize PXI modules, including
From a selected trigger bus line to PXI trigger connector
From the PXI trigger connector to a selected trigger bus line
From software trigger to a selected trigger bus line
From software trigger to PXI trigger connector
All trigger modes are programmable by the provided driver.
Trigger
Ground