ADLINK Technology PXIe-9834 User manual

Leading EDGE COMPUTING
PXIe-9834
4CH 16-bit 80MS/s PXIe Digitizer
User’s Manual
Manual Rev.: 1.0
Revision Date: September 12, 2019
Part No: 50-17057-1000

ii
Leading EDGE COMPUTING
Revision History
Revision Release Date Description of Change(s)
1.0 September 12, 2019 Initial release

Preface iii
PXIe-9834
Preface
Copyright © 2019 ADLINK Technology Inc.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, spe-
cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsi-
bility to global environmental preservation
through compliance with the European Union's
Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental pro-
tection is a top priority for ADLINK. We have
enforced measures to ensure that our products,
manufacturing processes, components, and raw
materials have as little impact on the environment as possible.
When products are at their end of life, our customers are encour-
aged to dispose of them in accordance with the product disposal
and/or recovery programs prescribed by their nation or company.

iv Preface
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ᘄ㟁ụㄳᅇᨲ

Preface v
PXIe-9834
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
NOTE:
NOTE:
Additional information, aids, and tips that help users perform
tasks.
CAUTION:
Information to prevent minor physical injury, component dam-
age, data loss, and/or program corruption when trying to com-
plete a task.
WARNING:
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.

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Table of Contents vii
PXES-2785
Table of Contents
Preface .................................................................................... iii
List of Figures ........................................................................ ix
List of Tables.......................................................................... xi
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 2
1.3 Specifications....................................................................... 2
1.3.1 Analog Input ............................................................... 2
1.3.2 Accuracy..................................................................... 3
1.3.3 System Noise ............................................................. 3
1.3.4 Crosstalk, DC to 10MHz ............................................. 3
1.3.5 Spectral Characteristics.............................................. 4
1.3.6 Timebase.................................................................... 6
1.3.7 Triggers ...................................................................... 7
1.3.8 Mechanical and Environmental .................................. 9
1.3.9 Power Consumption ................................................... 9
1.4 Software Support ............................................................... 10
1.4.1 MAPS Core............................................................... 11
1.4.2 MAPS/LV, LabVIEW Support ................................... 14
1.4.3 MAPS/C, C & C++ Support ...................................... 14
1.5 Device Layout and I/O Connectors.................................... 15
2 Getting Started ................................................................. 19
2.1 Installation Environment .................................................... 19
2.2 Package Contents ............................................................. 20
2.3 Installing the Module.......................................................... 21
3 Operations ........................................................................ 23

viii Table of Contents
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3.1 Functional Block Diagram .................................................. 23
3.2 Analog Input Channel ........................................................ 23
3.2.1 Analog Input Front-End Configuration ...................... 23
3.2.2 Input Range and Data Format .................................. 24
3.2.3 DMA Data Transfer...................................................26
3.3 Trigger Source ................................................................... 27
3.3.1 Software Trigger ....................................................... 28
3.3.2 External Digital Trigger ............................................. 28
3.3.3 Analog Trigger .......................................................... 29
3.3.4 PXI Trigger Bus ........................................................ 30
3.3.5 PXI Star .................................................................... 30
3.3.6 PXIe Differential Trigger ........................................... 30
3.4 Trigger Modes.................................................................... 31
3.4.1 Post Trigger Mode .................................................... 31
3.4.2 Delayed Trigger Mode .............................................. 32
3.4.3 Pre-Trigger Mode...................................................... 32
3.4.4 Middle Trigger Mode.................................................33
3.4.5 Acquisition with Re-Triggering .................................. 34
3.5 Timebase ........................................................................... 35
3.5.1 Internal Sampling Clock............................................35
3.5.3 External Reference Clock ......................................... 36
3.6 Acquisition Timing Control ................................................. 37
3.7 Synchronizing Multiple Modules ........................................ 39
3.7.1 Multi-module Synchronization Interfaces..................43
A Appendix: Calibration....................................................... 45
A.1 Calibration Constant .......................................................... 45
A.2 Auto-Calibration ................................................................. 46
Important Safety Instructions.............................................. 49
Getting Service ..................................................................... 53

List of Figures ix
PXES-2785
List of Figures
Figure 1-1: Typical Frequency Response, 1Minput impedance 4
Figure 1-2: Typical Frequency Response, 50input impedance . 5
Figure 1-3: ADLINK MAPS Architecture ..................................... 10
Figure 1-4: ADLINK Connection Explorer (ACE) ........................ 12
Figure 1-5: ADLINK Connection Explorer Soft Front Panel ........ 13
Figure 1-6: PXIe-9834 Dimensions............................................. 15
Figure 1-7: PXIe-9834 Front Panel ............................................. 16
Figure 3-1: Functional Block Diagram......................................... 23
Figure 3-2: Analog Input Architecture ......................................... 23
Figure 3-3: Linked List of PCI Address DMA Descriptors ........... 27
Figure 3-4: Trigger Architecture .................................................. 27
Figure 3-5: External Digital Trigger ............................................. 28
Figure 3-6: Analog Trigger Conditions ....................................... 29
Figure 3-7: Post-Trigger Acquisition ........................................... 31
Figure 3-8: Delayed Trigger Mode Acquisition............................ 32
Figure 3-9: Pre-Trigger Mode Acquisition ................................... 32
Figure 3-10: Middle Trigger Mode Acquisition .............................. 33
Figure 3-11: Re-Trigger Mode Acquisition .................................... 34
Figure 3-12: Timebase Architecture.............................................. 35
Figure 3-13: Varying Sampling Rates via Scan Interval Counter.. 37
Figure 3-14: Non-synched Digitizer Modules................................ 39
Figure 3-15: External Instrument Synchronization........................ 40
Figure 3-16: Module-based Synchronization ................................ 41
Figure 3-17: PXIe Instrumentation Signals ................................... 42
Figure 3-18: Trigger Architecture .................................................. 43
Figure 3-19: PXI_CLK10 as 10MHz Reference ............................ 44
Figure A-1: Auto-Calibration Block Diagram ............................... 46
Figure A-2: Auto-Calibration Flow ............................................... 47

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List of Tables xi
PXIe-9834
List of Tables
Table 1-1: Analog Input Channel Characteristics ............................. 2
Table 1-2: Accuracy.......................................................................... 3
Table 1-3: System Noise................................................................... 3
Table 1-4: Crosstalk, DC to 10MHz .................................................. 3
Table 1-5: Spectral Characteristics................................................... 4
Table 1-6: Timebase Specifications.................................................. 6
Table 1-8: External Reference Clock ................................................ 7
Table 1-9: Triggers............................................................................ 7
Table 1-10: External Digital Trigger Input ........................................... 8
Table 1-11: Onboard Reference (Calibration)..................................... 8
Table 1-12: Specifications................................................................... 9
Table 1-13: Power Consumption ........................................................ 9
Table 1-14: PXIe-9834 I/O Array Legend ......................................... 17
Table 3-1: Input Range and Data Format ....................................... 24
Table 3-2: Input Range FSR and -FSR Values............................... 25
Table 3-3: Input Range Midscale Values........................................ 25
Table 3-4: Counter Parameters and Description ............................ 38

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Introduction 1
PXIe-9834
1 Introduction
The ADLINK PXIe-9834 PXI Express digitizer delivers high speed,
high quality data acquisition, with each of four input channels sup-
porting up to 80MS/s sampling with 16-bit resolution A/D con-
verter. This provides simultaneous recording of signals on all
channels with no inter-channel phase delay, and the extremely
large onboard memory enables long recording times even at the
highest sampling rates.
The PXIe-9834 features flexible input, ±10V (only for 1M), ±5V,
±1V and ±0.5V along with software selectable 50or 1Minput
impedance. Four high resolution 16-bit A/D converters combined
with low-noise, high bandwidth analog front-end enable highly
accurate signal acquisition. Providing extremely large onboard
memory, the PCI Express 4 lane interface supports data stream-
ing even at the highest sampling rates. The PXIe-9834 is also
auto-calibrated with an onboard reference circuit compensating
the offset and gain error of acquired analog input signals.
The PXIe-9834 is, accordingly, ideal for applications such as radar
signal acquisition, fiber optic detection, and many others.
1.1 Features
XUp to 80MS/s sampling
X4 simultaneous analog inputs
XHigh resolution 16-bit ADC
XUp to 40 MHz bandwidth for analog input
X1GB onboard storage
XProgrammable input voltage of ±0.5V, ±1V, ±5V, or ±10V
X10 or 20MHz onboard digital filter
XSupport for external reference clock (10MHz)
XScatter-Gather DMA data transfer for high speed data
streaming
XPXI/PXIe instrumentation signals supported for triggers and
timebase
XFull auto-calibration

2 Introduction
Leading EDGE COMPUTING
1.2 Applications
XTesting/monitoring for Energy Management applications,
including:
ZPartial discharge
ZPower line/device monitoring
XNon-destructive testing
XRadar acquisition
XLiDAR
1.3 Specifications
1.3.1 Analog Input
Table 1-1: Analog Input Channel Characteristics
Item Specification Comment
Channels 4 single-ended
Connector
type SMA
Input
coupling DC or AC, software selectable
ADC
resolution 16-Bit
Input range ±0.5 V, ±1 V, ± 5V, or ± 10V ±10V range support only for
1Minput impedance
Bandwidth
(-3dB) 40MHz
Maximum
input
overload
7Vrms For 50: ±0.5V or ±1V or ±
5V input range
±10V For 1M: ±0.5V or ±1V
±30V For 1M: ±5V or ±10V
Input
impedance
50or 1M,
software selectable
Digital filter 10MHz or 20MHz,
software selectable

Introduction 3
PXIe-9834
1.3.2 Accuracy
Table 1-2: Accuracy
1.3.3 System Noise
Table 1-3: System Noise
1.3.4 Crosstalk, DC to 10MHz
Table 1-4: Crosstalk, DC to 10MHz
Input
Range
Offset Error
Gain Error
50ΩInput
Impedance
1MΩInput
Impedance
±0.5V ±0.8mV ±0.8mV
±0.6%
±1V ±0.8mV ±1.2mV
±5V ±1.5mV ±4.0mV
±10V N/A ±8mV
Input Range System Noise
±0.5V 0.1mVrms
±1V 0.15mVrms
±5V 1mVrms
±10V 1.5mVrms
Input Range Crosstalk Comment
±0.5V <-80dB 1MHz sine wave, 90% of
full scale range
±1V, ±5V, ±10V <-90dB 1MHz sine wave, 90% of
full scale range

4 Introduction
Leading EDGE COMPUTING
1.3.5 Spectral Characteristics
Table 1-5: Spectral Characteristics
Figure 1-1: Typical Frequency Response, 1MΩinput impedance
Index Specification Comment
SINAD 68dB ±0.5V, ±1V, ±5V
65dB ±10V
THD -78dB For all ranges
SFDR 78dB For all ranges
SNR 69dB ±0.5V, ±1V, ±5V
65dB ±10V
NOTE:
NOTE:
Values reflect 50and 1Minput impedance with digital filter
off.

Introduction 5
PXIe-9834
Figure 1-2: Typical Frequency Response, 50Ωinput impedance

6 Introduction
Leading EDGE COMPUTING
1.3.6 Timebase
Table 1-6: Timebase Specifications
Sample Clock Detail Comment
Timebase options
Internal: Onboard
oscillator
External: CLK IN (front
panel SMA connector)
External reference clock:
CLK IN (front
panel SMA con-
nector)
PXI_10M (PXIe
backplane
10MHz refer-
ence clock)
The reference clock
supplies an onboard PLL
circuit and generates
80MHz for ADC.
Sampling clock
frequency
Internal 80MS/s
maximum, ranges from
1.22KS/s to 80MS/s
1.22kS/s to 80MS/s
External reference clock:
10MHz
Internal onboard
oscillator accuracy < ± 25ppm

Introduction 7
PXIe-9834
Table 1-8: External Reference Clock
1.3.7 Triggers
Table 1-9: Triggers
External Reference
Clock Specification
Clock input range 0.45Vpp to 5Vpp
Clock input coupling AC
Clock input impedance 50
Duty cycle tolerance 45% to 55%
Reference clock
frequency range 10MHz ± 2KHz
Trigger Source & Mode
Trigger source
Internal: software trigger
External:
XExternal digital trigger from TRG IN (front panel)
XAnalog trigger from any of analog input channels
XPXI Trigger Bus[0..7]
XPXI STAR Trigger
XPXIe_DSTARB
Trigger modes
XPost-trigger
XDelay trigger
XPre-trigger
XMiddle trigger
XRe-trigger for post-trigger and delay trigger
modes

8 Introduction
Leading EDGE COMPUTING
Table 1-10: External Digital Trigger Input
Table 1-11: Onboard Reference (Calibration)
External Digital Trigger Input
Sources TRG IN, front panel SMA connector
Compatibility 3.3 V TTL, 5 V tolerant
Input high threshold (VIH) 2.0 V
Input low threshold (VIL) 0.8 V
Maximum input overload -0.5 V to +5.5 V
Trigger polarity Rising or falling, software selectable
Trigger pulse width 20 ns minimum
Onboard Reference (Calibration)
Calibration Specification
Onboard reference +1.8V, +0.9V, +0.45V
Temperature coefficient 5.0 ppm/°C
Warm-up time 15 minutes (recommended)