ADLINK Technology DAQ/PXI-20 Series User manual

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Advance Technologies; Automate the World.
Manual Rev. 2.00
Revision Date: April 20, 2006
Part No: 50-11020-1030
DAQ/PXI-201x/200x
4-CH, Simultaneous, High Performance
Multi-Function Data Acquisition Card
User’s Manual

Copyright 2006 ADLINK TECHNOLOGY INC.
All Rights Reserved.
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, spe-
cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Trademarks
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.

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Please contact us should you require any service or assistance.
ADLINK TECHNOLOGY INC.
Web Site: http://www.adlinktech.com
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Table of Contents i
Table of Contents
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 2
1.2 Applications ......................................................................... 3
1.3 Specifications....................................................................... 4
1.4 Software Support ............................................................... 13
Programming Library .................................................... 13
DAQ-LVIEW PnP: LabVIEW® Driver ........................... 13
D2K-OCX: ActiveX Controls ......................................... 14
2 Installation ........................................................................ 15
2.1 Contents of Package ......................................................... 15
2.2 Unpacking.......................................................................... 15
2.3 DAQ/PXI-20XX Layout ...................................................... 17
2.4 PCI Configuration .............................................................. 18
3 Signal Connections.......................................................... 19
3.1 Connectors Pin Assignment .............................................. 19
3.2 Analog Input Signal Connection ........................................ 24
Types of signal sources ................................................ 24
Single-Ended Measurements ....................................... 24
Differential Measurements ............................................ 25
4 Operation Theory ............................................................. 27
4.1 A/D Conversion.................................................................. 27
DAQ/PXI-2010 AI Data Format ..................................... 28
DAQ/PXI-2005/2006/2016 AI Data Format ................... 30
Software conversion with polling data transfer acqui-sition
mode (Software Polling) ..................................... 30
Programmable scan acquisition mode .......................... 31
Trigger Modes ............................................................... 33
4.2 D/A Conversion.................................................................. 42
Software Update ........................................................... 43
Timed Waveform Generation ........................................ 44
Trigger Modes ............................................................... 45
4.3 Digital I/O ........................................................................... 51
4.4 General Purpose Timer/Counter Operation....................... 52
Timer/Counter functions basics .................................... 52
General Purpose Timer/Counter modes ....................... 53

ii Table of Contents
4.5 Trigger Sources ................................................................. 57
Software-Trigger ........................................................... 57
External Analog Trigger ................................................ 57
4.6 User-controllable Timing Signals ....................................... 61
DAQ timing signals ....................................................... 63
Auxiliary Function Inputs (AFI) ...................................... 64
System Synchronization Interface ................................ 67
AI_Trig_Out and AO_Trig_Out ..................................... 69
5 Calibration ......................................................................... 71
5.1 Loading Calibration Constants........................................... 71
5.2 Auto-calibration .................................................................. 71
5.3 Saving Calibration Constants............................................. 72

List of Tables iii
List of Tables
Table 1-1: -3dB small signal bandwidth ..................................... 5
Table 1-2: System Noise ........................................................... 5
Table 1-3: CMRR: (DC to 60Hz) ................................................ 7
Table 3-1: 68-pin VHDCI-type pin assignment ........................ 19
Table 3-2: 68-pin VHDCI-type Connector Legend ................... 20
Table 3-3: SSI connector (JP3) pin assignment for DAQ-20XX 22
Table 3-4: Legend of SSI connector ........................................ 22
Table 4-1: Bipolar analog input range and the output digital code on
DAQ/PXI-2010 (Note that the last 2 digital codes are
SDI<1..0>) .............................................................. 29
Table 4-2: Unipolar analog input range and the output digital code
on DAQ/PXI-2010 (Note that the last 2 digital codes are
SDI<1..0>) .............................................................. 29
Table 4-3: Bipolar analog input range and the output digital code on
the DAQ/PXI-2005/2006/2016 ................................ 30
Table 4-4: Unipolar analog input range and the output digital code
on the DAQ/PXI-2005/2006/2016 ........................... 30
Table 4-5: Bipolar output code table (Vref=10V if internal reference
is selected) ............................................................. 43
Table 4-6: Unipolar output code table (Vref=10V if internal reference
is selected) ............................................................. 43
Table 4-7: Analog trigger SRC1 (EXTATRIG) ideal transfer charac-
teristic ..................................................................... 58
Table 4-8: Summary of user-controllable timing signals and the cor-
responding functionalities ....................................... 62
Table 4-9: Auxiliary function input signals and the corresponding
functionalities .......................................................... 65
Table 4-10: Summary of SSI timing signals and the corresponding
functionalities as the master or slave ..................... 67

iv List of Figures
List of Figures
Figure 2-1: PCB Layout of the DAQ-20XX................................. 17
Figure 2-2: PCB Layout of the PXI-20XX................................... 17
Figure 3-1: Single-Ended connections ....................................... 25
Figure 3-2: Ground-referenced source and differential input ..... 25
Figure 3-3: Floating source and differential input....................... 26
Figure 4-1: Synchronous Digital Inputs Block Diagram.............. 28
Figure 4-2: Synchronous Digital Inputs timing ........................... 28
Figure 4-3: Scan Timing............................................................. 32
Figure 4-4: Pre-trigger (trigger occurs after at least M scans ac-
quired) ..................................................................... 34
Figure 4-5: Pre-trigger scan acquisition (trigger occurs when a con-
version is in progress).............................................. 34
Figure 4-6: Pre-trigger with M_enable = 0 (Trigger occurs before M
scans) ...................................................................... 35
Figure 4-7: Pre-trigger with M_enable = 1 ................................. 35
Figure 4-8: Middle trigger with M_enable = 1............................. 36
Figure 4-9: Middle trigger (trigger occurs when a scan is in progress)
37
Figure 4-10: Post trigger .............................................................. 38
Figure 4-11: Delay trigger ............................................................ 39
Figure 4-12: Post trigger with re-trigger ....................................... 40
Figure 4-13: Scatter/gather DMA for data transfer....................... 42
Figure 4-14: Typical D/A timing of waveform generation (Assuming
the data in the data buffer are 2V, 4V, -4V, 0V)....... 45
Figure 4-15: Post trigger waveform generation (Assuming the data in
the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 46
Figure 4-16: Delay trigger waveform generation (Assuming the data in
the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) 47
Figure 4-17: Re-triggered waveform generation (Assuming the data in
the data buffer are 2V, 4V, 2V, 0V).......................... 47
Figure 4-18: Finite iterative waveform generation with Post-trigger and
DLY2_Counter = 0 (Assuming the data in the data buffer
are 2V, 4V, 2V, 0V).................................................. 48
Figure 4-19: Infinite iterative waveform generation with Post-trigger
and DLY2_Counter = 0 (Assuming the data in the data
buffer are 2V, 4V, 2V, 0V)........................................ 49
Figure 4-20: Stop mode I (Assuming the data in the data buffer are 2V,
4V, 2V, 0V) .............................................................. 50

List of Figures v
Figure 4-21: Stop mode II ............................................................ 51
Figure 4-22: Stop mode III ........................................................... 51
Figure 4-23: Mode 1 Operation.................................................... 53
Figure 4-24: Mode 2 Operation.................................................... 54
Figure 4-25: Mode 3 Operation.................................................... 54
Figure 4-26: Mode 4 Operation.................................................... 55
Figure 4-27: Mode 5 Operation.................................................... 55
Figure 4-28: Mode 6 Operation.................................................... 56
Figure 4-29: Mode 7 Operation.................................................... 56
Figure 4-30: Mode 8 Operation.................................................... 57
Figure 4-31: Analog trigger block diagram................................... 58
Figure 4-32: Below-Low analog trigger condition......................... 59
Figure 4-33: Above-High analog trigger condition ....................... 59
Figure 4-34: Inside-Region analog trigger condition .................... 60
Figure 4-35: High-Hysteresis analog trigger condition................. 60
Figure 4-36: Low-Hysteresis analog trigger condition.................. 61
Figure 4-37: External digital trigger.............................................. 61
Figure 4-38: DAQ signals routing................................................. 62

Introduction 1
1 Introduction
The DAQ/PXI-20XX is an advanced data acquisition card based
on the 32-bit PCI architecture. High performance designs and the
state-of-the-art technology make this card ideal for data logging
and signal analysis ap-plications in medical, process control, etc.

2Introduction
1.1 Features
The DAQ/PXI-20XX Advanced Data Acquisition Card provides the
fol-lowing advanced features:
X32-bit PCI-Bus, plug and play
X4-channel simultaneous differential analog inputs
XDAQ/PXI-2010: 14-bit Analog input resolution with sampling
rate up to 2MS/s
XDAQ/PXI-2005: 16-bit Analog input resolution with sampling
rate up to 500KS/s
XDAQ/PXI-2006: 16-bit Analog input resolution with sampling
rate up to 250KS/s
XDAQ/PXI-2016: 16-bit Analog input resolution with sampling
rate up to 800kS/s
XProgrammable bipolar/unipolar analog input
XProgrammable gain (x1, x2, x4, x8 for all DQ-20XX)
XDAQ/PXI-2010: Total 8K samples A/D FIFO
XDAQ/PXI-2005/2006/2016: Total 512 samples A/D FIFO
XVersatile trigger sources: software trigger, external digital
trigger, analog trigger and trigger from System Synchroniza-
tion Interface (SSI).
XA/D Data transfer: software polling & bus-mastering DMA
with Scatter/Gather functionality
XFour A/D trigger modes: post-trigger, delay-trigger, pre-trig-
ger and middle-trigger
X2 channel DA outputs with waveform generation capability
X2K samples output data FIFO for DA channels
XDA Data transfer: software update and bus-mastering DMA
with Scatter/Gather functionality
XSystem Synchronization Interface (SSI)
XA/D/DA fully auto-calibration
XCompletely jumper-less and software configurable

Introduction 3
1.2 Applications
XAutomotive Testing
XCable Testing
XTransient signal measurement
XATE
XLaboratory Automation
XBiotech measurement

4Introduction
1.3 Specifications
Analog Input (AI)
XNumber of channels: 4 differential
XA/D converter:
Z2010: LTC1414 or equivalent
Z2005: A/D7665 or equivalent
Z2006: A/D7663 or equivalent
Z2016: A/D7671 or equivalent
XMax sampling rate:
Z2010: 2MS/s
Z2016: 800kS/s
Z2005: 500kS/s
Z2006: 250kS/s
XResolution:
Z2010: 14 bits, no missing code
Z2005/2006/2016:16 bits, no missing code
XFIFO buffer size:
Z2010:8K samples
Z2005/2006/2016: 512 samples
XProgrammable input range:
ZBipolar: ±10V, ±5V, ±2.5V, ±1.25V
ZUnipolar: 0~10V, 0~5V, 0~2.5V, 0~1.25V
XOperational common mode voltage range: ±11V
XOvervoltage protection:
ZPower on: continuous ±30V
ZPower off: continuous ±15V
XInput impedance: 1GΩ/100pF

Introduction 5
X-3dB small signal bandwidth: (Typical, 25°C)
XLarge signal bandwidth (1% THD): 300 kHz
XSystem Noise: (Typical)
Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB)
2010
±10V 1170 kHz 0~10V 1090 kHz
±5V 1050 kHz 0~5V 1020 kHz
±2.5V 800 kHz 0~2.5V 790 kHz
±1.25V 530 kHz 0~1.25V 530 kHz
2005
±10V 1160 kHz 0~10V 1210 kHz
±5V 1050 kHz 0~5V 1050 kHz
±2.5V 780 kHz 0~2.5V 770 kHz
±1.25V 520 kHz 0~1.25V 530 kHz
2006
±10V 630 kHz 0~10V 640 kHz
±5V 620 kHz 0~5V 620 kHz
±2.5V 540 kHz 0~2.5V 540 kHz
±1.25V 410 kHz 0~1.25V 420 kHz
2016
±10V 840kHz 0~10V 900kHz
±5V 825kHz 0~5V 800kHz
±2.5V 710kHz 0~2.5V 690kHz
±1.25V 530kHz 0~1.25V 530kHz
Table 1-1: -3dB small signal bandwidth
Device Input Range System noise Input Range System noise
2010
±10V 0.6 LSBrms 0~10V 0.8 LSBrms
±5V 0.6 LSBrms 0~5V 0.8 LSBrms
±2.5V 0.6 LSBrms 0~2.5V 0.9 LSBrms
±1.25V 0.6 LSBrms 0~1.25V 0.9 LSBrms
2005
±10V 1.2 LSBrms 0~10V 1.9 LSBrms
±5V 1.2 LSBrms 0~5V 2.0 LSBrms
±2.5V 1.3 LSBrms 0~2.5V 2.1 LSBrms
±1.25V 1.3 LSBrms 0~1.25V 2.2 LSBrms
Table 1-2: System Noise

6Introduction
2006
±10V 1.0 LSBrms 0~10V 1.5 LSBrms
±5V 1.0 LSBrms 0~5V 1.6 LSBrms
±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms
±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms
2016
±10V 1.6 LSBrms 0~10V 2.9 LSBrms
±5V 1.8 LSBrms 0~5V 3.2 LSBrms
±2.5V 1.8 LSBrms 0~2.5V 3.2 LSBrms
±1.25V 1.9 LSBrms 0~1.25V 3.4 LSBrms
Device Input Range System noise Input Range System noise
Table 1-2: System Noise

Introduction 7
XCMRR: (DC to 60Hz, Typical)
XTime-base source:
ZInternal 40MHz or External clock Input (fmax: 40MHz,
fmin: 1MHz, 50% duty cycle)
XTrigger modes:
ZPost-trigger, Delay-trigger, Pre-trigger and Middle-trigger
XData transfers:
ZProgrammed I/O, and bus-mastering DMA with scatter/
gather
XInput coupling: DC
XOffset error:
ZBefore calibration: ±60mV max
ZAfter calibration: ±1mV max
XGain error:
Device Input Range CMRR Input Range CMRR
2010
±10V 90 dB 0~10V 89 dB
±5V 92 dB 0~5V 92 dB
±2.5V 95 dB 0~2.5V 94 dB
±1.25V 97 dB 0~1.25V 97 dB
2005
±10V 86 dB 0~10V 85 dB
±5V 88 dB 0~5V 88 dB
±2.5V 91 dB 0~2.5V 90 dB
±1.25V 93 dB 0~1.25V 93 dB
2006
±10V 87 dB 0~10V 86 dB
±5V 89 dB 0~5V 88 dB
±2.5V 91 dB 0~2.5V 91 dB
±1.25V 93 dB 0~1.25V 93 dB
2016
±10V 85dB 0~10V 86dB
±5V 88dB 0~5V 88dB
±2.5V 91dB 0~2.5V 92dB
±1.25V 95dB 0~1.25V 95dB
Table 1-3: CMRR: (DC to 60Hz)

8Introduction
ZBefore calibration: ±0.6% of output max
ZAfter calibration: ±0.1% of output max for DAQ/PXI-
2010, ±0.03% of output max for DAQ/PXI-2005/2006/
2016

Introduction 9
Analog Output (AO)
XNumber of channels: 2 channel voltage output
XDA converter: LTC7545 or equivalent
XMax update rate: 1MS/s
XResolution: 12 bits
XFIFO buffer size:
Z1k samples per channel when both channels are
enabled for timed DA output, and 2k samples when only
one channel is used for timed DA output
XData transfers:
ZProgrammed I/O, and bus-mastering DMA with scatter/
gather
XOutput range:
ZBipolar: ±10V or ±AOEXTREF
ZUnipolar: 0~10V or 0~AOEXTREF
XSettling time: 3µS to 0.5 LSB accuracy
XSlew rate: 20V/µS
XOutput coupling: DC
XProtection: Short-circuit to ground
XOutput impedance: 0.3Ωtypical
XOutput driving current: ±5mA max.
XStability: Any passive load, up to 1500pF
XPower-on state: 0V steady-state
XPower-on glitch: ±1.5V/500uS
XRelative accuracy:
Z±0.5 LSB typical, ±1 LSB max
XDNL:
Z±0.5 LSB typical, ±1.2 LSB max
XOffset error:
ZBefore calibration: ±80mV max
ZAfter calibration: ±1mV max
XGain error: