ADLINK Technology PXI-2020 User manual

Advance Technologies; Automate the World.
Manual Rev. 2.01
Revision Date: October 4, 2010
Part No: 50-17032-2010
PXI-2020/2022
8/16-CH 16-Bit 250 KS/s
Simultaneous Sampling Card
User’s Manual

Copyright 2010 ADLINK TECHNOLOGY INC.
All Rights Reserved.
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, spe-
cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Trademarks
NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK
TECHNOLOGY INC.
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.

Getting Service from ADLINK
Contact us should you require any service or assistance.
ADLINK Technology, Inc.
Address: 9F, No.166 Jian Yi Road, Chungho City,
Taipei County 235, Taiwan
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Ampro ADLINK Technology, Inc.
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Address: No. 1357, "Anupama", Sri Aurobindo Marg, 9th Cross,
JP Nagar Phase I, Bangalore - 560078, India
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Email: [e-mail]

Table of Contents i
Table of Contents
Table of Contents..................................................................... i
List of Tables.......................................................................... iii
List of Figures........................................................................ iv
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 2
1.2 Applications ......................................................................... 3
1.3 Specifications....................................................................... 3
1.4 Performance ........................................................................ 8
2 Getting Started ................................................................... 9
2.1 Installation Environment ...................................................... 9
2.2 Package Contents ............................................................. 10
2.3 Mechanical Drawing and I/O Connectors .......................... 11
2.4 Installing the module.......................................................... 14
2.5 Software Support ............................................................... 15
Programming Library .................................................... 15
2.6 PCI Configuration .............................................................. 16
3 Signal Connections.......................................................... 17
3.1 Connectors Pin Assignment .............................................. 17
3.2 Analog Input Signal Connection ........................................ 20
Types of Signal Sources ............................................... 20
Input Connect Configurations - Differential Input Mode 21
4 Function Block and Operation Theory........................... 23
4.1 Overall Function Block Diagram ........................................ 23
4.2 Basic AI Acquisition ........................................................... 24
Analog Input Path ......................................................... 24
Basic Acquisition Timing ............................................... 24
AI Data Format ............................................................. 26
4.3 ADC Sampling Rate and TIMEBASE Control.................... 28
Internal Oscillator .......................................................... 28
External Clock through Front Panel .............................. 28
External Clock from PXI Interfaces ............................... 29
Sampling Rate Control .................................................. 30

ii Table of Contents
Timebase Exporting ...................................................... 30
4.4 Trigger Sources ................................................................. 31
Software Trigger ........................................................... 31
External Digital Trigger ................................................. 31
PXI Star Trigger ............................................................ 32
PXI Trigger Bus ............................................................ 32
Trigger Signal Exporting ............................................... 33
4.5 User-controllable Timing Signals ....................................... 34
DAQ timing signals ....................................................... 35
Auxiliary Function Inputs (AFI) ...................................... 36
4.6 Trigger Modes.................................................................... 37
Post-trigger Acquisition ................................................. 37
Pre-trigger Acquisition .................................................. 37
Middle-trigger Acquisition ............................................. 38
Delay-trigger Acquisition ............................................... 39
4.7 Synchronizing Multiple Modules ........................................ 40
SSI_TIMEBASE ............................................................ 41
4.8 General Purpose Timer/Counter Operation ....................... 43
Timer/Counter Functions Basics ................................... 43
General Purpose Timer/Counter Modes ....................... 44
5 Calibration......................................................................... 49
5.1 Loading Calibration Constants........................................... 49
5.2 Auto-calibration .................................................................. 50
5.3 Saving Calibration Constants............................................. 50
Important Safety Instructions............................................... 51

List of Tables iii
List of Tables
Table 1-1: Basic Specifications .................................................. 3
Table 1-2: Triggers .................................................................... 4
Table 1-3: Digital I/O .................................................................. 5
Table 1-4: General Purpose Timer/Counter .............................. 5
Table 1-5: Timebase System ..................................................... 6
Table 1-6: Auto Calibration ........................................................ 6
Table 1-7: General ..................................................................... 7
Table 1-8: Power Requirements ................................................ 7
Table 1-9: Performance ............................................................. 8
Table 2-1: SMB Connector ...................................................... 12
Table 2-2: TRG IO, as an Input Port ........................................ 12
Table 2-3: TRG IO, as an Output Port ..................................... 13
Table 2-4: CLK IN .................................................................... 13
Table 2-5: CLK OUT0/OUT1, as an Output Port ..................... 13
Table 3-1: PXI-2020/2022 68-pin VHDCI-type Pin Assignment 17
Table 3-2: 68-pin VHDCI-type Connector Legend ................... 18
Table 4-1: Basic Counters ....................................................... 25
Table 4-2: Bipolar Analog Input Range and Output Digital Code 27
Table 4-3: Summary of User-controllable Timing Signals and Corre-
sponding Functionalities ......................................... 35
Table 4-4: SSI Timing .............................................................. 40

iv List of Figures
List of Figures
Figure 2-1: PXI-2020/2022 PCB Layout..................................... 11
Figure 3-1: Ground-referenced Source and Differential Input.... 21
Figure 3-2: Floating Source and Differential Input ..................... 22
Figure 4-1: PXI-2022 Functional Block Diagram........................ 23
Figure 4-2: PXI-2020/2022 Analog Input Path ........................... 24
Figure 4-3: Basic Acquisition Timing of PXI-2020/2022............. 26
Figure 4-4: PXI-2022 Timebase Source and Architecture. ........ 28
Figure 4-5: Configuring Different Sampling Rate of PXI-2022. .. 30
Figure 4-6: PXI-2020/2022 Trigger Sources .............................. 31
Figure 4-7: External Digital Trigger Polarity and Pulse Width Re-
quirement................................................................. 32
Figure 4-8: TRG IO Output Signal Timing.................................. 33
Figure 4-9: DAQ Signal Routing................................................. 34
Figure 4-10: Post-trigger Acquisition............................................ 37
Figure 4-11: Pre-trigger Mode Operation ..................................... 37
Figure 4-12: Pre-trigger Mode Operation ..................................... 38
Figure 4-13: Middle-trigger Mode Operation ................................ 38
Figure 4-14: Delay-trigger Mode Operation ................................. 39
Figure 4-15: SSI Mode Operation ................................................ 41
Figure 4-16: Mode 1 Operation.................................................... 44
Figure 4-17: Mode 2 Operation.................................................... 45
Figure 4-18: Mode 3 Operation.................................................... 45
Figure 4-19: Mode 4 Operation.................................................... 46
Figure 4-20: Mode 5 Operation.................................................... 46
Figure 4-21: Mode 6 Operation.................................................... 47
Figure 4-22: Mode 7 Operation.................................................... 47
Figure 4-23: Mode 8 Operation.................................................... 48

Introduction 1
1 Introduction
ADLINK's PXI-2020/2022 are simultaneous-sampling multi-func-
tion DAQ cards to meet a wide range of application requirements
for PXI systems. The devices can simultaneously sample 8/16 AI
channels with differential input configurations in order to achieve
maximum noise elimination. If more analog input channels are
required, multiple cards can be synchronized through the PXI Trig-
ger bus. The PXI-2020/2022 feature digital triggering, 4-CH pro-
grammable digital I/O lines, and 2-CH 32-bit general-purpose
timer/counter. The auto-calibration functions adjust the gain and
offset to be within specified accuracies such that you do not have
to adjust trim pots to calibrate the cards.
Flexible Triggering
The PXI-2020/2022 feature flexible triggering options such as a
software trigger, external digital trigger and triggers from the PXI
Star trigger and trigger bus. These versatile trigger sources allow
you to configure the PXI-2020/2022 to fit your application needs.
Post-trigger, delay-trigger, pre-trigger and middle-trigger modes
are also available to acquire data around the trigger event. The
PXI-2020/2022 also feature repeated trigger acquisition, so you
can acquire data in multiple segments with successive trigger
events at extremely short rearming intervals.
Multiple-Module Synchronization
The versatile trigger options provided by the PXI backplane allow
the PXI-2020/2022 to achieve multi-module synchronization in a
simplified way. Utilizing the PXI Trigger bus, the PXI-2020/2022
can output trigger signals and the timebase to the PXI trigger bus
when configured as a master, or receive trigger signals and the
timebase from the PXI trigger bus when configured as a slave.
Moreover, when the PXI-2020/2022 are plugged into a peripheral
slot of a PXI system, they can also receive triggers or the time-
base from the PXI Star trigger controller slot. The precision 10
MHz clock that comes from the PXI backplane can also be used
as one of the timebase sources. Combining these PXI trigger fea-
tures with the interface of the PXI-2020/2022 makes it very easy to
synchronize multiple modules.

2Introduction
Calibration
The PXI-2020/2022 includes a precision on-board reference with
very low temperature drift. This feature not only provides a stable
calibration source for auto-calibration but also maintains stable
acquisition accuracy over a wide temperature range. The auto-
mated calibration process can be done through software without
need for any manually adjustments. Once the calibration process
has completed, the calibration information will be stored in the on-
board EEPROM so that the values can be loaded and used as
needed by the board.
1.1 Features
The PXI-2020/2022 Simultaneous Data Acquisition Card provides
the following advanced features:
Supports 3.3V and 5V PCI signal
PXI specification Rev 2.2 compliant
8/16-CH differential analog inputs
Bipolar analog input
Programmable gains of x1, x4
Scatter gather DMA transfer for AI continuously data acqui-
sition
4-CH TTL digital input/output
2-CH 32-bit general purpose timer/counters
Digital triggering
Fully auto calibration
Multiple cards synchronization through PXI trigger bus
Onboard 16 K sample memory for data storage

Introduction 3
1.2 Applications
Automotive Testing
Cable Testing
Transient signal measurement
ATE
Laboratory Automation
Biotech measurement
1.3 Specifications
Basic Specifications
Analog Input[1]
Model Number PXI-2020 PXI-2022
Number of channels: (pro-grammable) 8 differential 16 differential
A/D converter : AD7685 or equivalent
Maximum sampling rate: 250 kS/s (each channel)
Resolution: 16 bits
Input coupling: DC
Programmable input range: ±10V, ±2.5V
Operational common mode voltage
range: ±8V
Overvoltage protection: Power on: Continuous ±30V
Power off: Continuous ±30V
FIFO buffer size: 16 K samples (8192 x 32 bits)
Data transfers: Polling Mode, Bus-mastering DMA with
scatter/gather
Input impedance 1 GΩ
Trigger mode: Pre-Trigger, Post-Trigger, Middle-Trigger,
Delay-Trigger
Time-base source Internal 80Mhz
Table 1-1: Basic Specifications

4Introduction
Triggers
Trigger Specifications
Model Name PXI-2020/2022
Trigger Sources
(refer to section 4.4 for details)
(1)Software
(2)AFI [0..7]
(3)PXI Star Trigger
(4)PXI Trigger Bus[5] (SSI)
(5)SMB Trigger I/O (please refer to chapter
2.3 for details)
*GA 3-8 can use (1), (2), (4), (5) as output
signals. GA2 can use all options.
Trigger Mode Pre-Trigger, Post-Trigger, Middle-Trigger,
Delay-Trigger
AFI (Auxiliary Function Interface)
Number of Channel 8 input/output (refer to pin legend definition)
Compatibility Output 3.3 V TTL
Input Logic Levels Input low voltage: 0.8 V (max)
Input high voltage: 2.0 V(min)
Output Logic Levels Output low voltage: 0.4 V (max)
Output high voltage: 2.8 V (min)
Output Driving Capacity ±24 mA
Maximum Input Overload -0.5 V to +5.5 V
Trigger Condition Rising or Falling, software selectable
Minimum Pulse Width 12.5 ns
Power-on State Input, pull-low with 10KΩresistor
Data Transfer Polling mode
PXI Star Trigger
Receive Trigger from PXI Star Trigger
Compatibility Output 3.3 V TTL
Pulse Duration 12.5 ns
Pulse Logic Rising or Falling edge, software selectable
PXI Trigger Bus[0..7]
Receive Trigger from PXI Trigger Bus line 5
Compatibility Input 3.3 V or 5 V TTL
Output 3.3 V TTL
Pulse Duration 12.5 ns
Pulse Logic Rising or Falling edge, software selectable
Table 1-2: Triggers

Introduction 5
Digital I/O
General Purpose Timer/Counter (GPTC)
Digital I/O Specifications
Model Name PXI-2020/2022
Number of Channel 4 input/output
Compatibility Input 3.3 V or 5 V TTL
Output 3.3 V TTL
Input Logic Levels Input low voltage: 0.8 V (max)
Input high voltage: 2.0 V(min)
Output Logic Levels Output low voltage: 0.4 V (max)
Output high voltage: 2.8 V (min)
Output Driving Capacity ±24 mA
Power-on State Input, pull-low with 10KΩresistor
Data Transfer Polling mode
Table 1-3: Digital I/O
General Purpose Specifications
Model Name PXI-2020/2022
Number of Channels 2 up/down counter/timers (by AFI)
Resolution 32-bit
Compatibility Input 3.3 V or 5V TTL
Output 3.3 V TTL
Base clock available 20 MHz
Data Transfer Polling mode
Table 1-4: General Purpose Timer/Counter

6Introduction
Timebase System
Auto Calibration
Timebase Specifications
Model Name PXI-2020/2022
Timebase Source (1) Internal: onboard 80MHz oscillator
(2) External from hardware IO
Sampling Rate Range
Timebase divided by 32-bit counter.
TIMEBASE(80MHz) divider to the achieve
equivalent sampling rate of DAQ. The equa-
tion is:
Sampling rate = TIMEBASE / ScanIntrv
The value of TIMEBASE depends on the
card type. Take PXI-2022 (250KS/s) as an
example, the ScanIntrv = 320 results in
250KS/s and ScanIntrv = 640 results in
125KS/s, and so on.
Internal Timebase Accuracy <±25ppm (typical)
External Timebase Clock
Sources (External from hardware IO)
(refer to section 4.3 for details)
(1) PXI_10M
(2) AFI [0..7]
(3) PXI Trigger BUS[0]
(4) PXI Star Trigger
(5) SMB_CLK
Dedicate External Clock Input From IO Connector
Clock Type Digital TTL
Input Frequency Range 1MHz ~ 20MHz
Input Coupling DC
Input Compatibility Input 3.3V or 5V TTL
Table 1-5: Timebase System
Auto Calibration Specifications
Model Name PXI-2020/2022
Onboard reference +5.000 V
Recommended warm-up time: 15 minutes
Temperature drift ±3 ppm°C (ADR02 5V Reference Chip)
Stability 50 ppm/1000hrs
(ADR02 5V Reference Chip)
Table 1-6: Auto Calibration

Introduction 7
General
Power Requirements
General Specifications
Model Name PXI-2020/2022
Dimensions Single 3U PXI module, 100mm by 160mm
(not including connector)
Connector 68-pin VHDCI-type female
Operating Environment
Ambient temperature: 0 to 55°C
Relative humidity: 10% to 90% non-con-
densing
Storage Environment
Ambient temperature: -20 to 80°C
Relative humidity: 5% to 95% non-condens-
ing
Table 1-7: General
Power Specifications
Model Name PXI-2020/2022
+3.3 V 1.5 A (typical)
+5 V 1.3 A (typical)
+12 V 0.35 A (typical)
Table 1-8: Power Requirements

8Introduction
1.4 Performance
Notes for Table 1-9:
SFDR, SINDA, THD, SNR, ENOB Data are based on below
condition
Gain = 1
0.9803771 KHz input tone, 18 Vpp input amplitude, 257
Sine waves, 65536 points
9.99832 KHz input tone, 18 Vpp input amplitude, 2621
Sine waves, 65536 points
Analog Input Measurement[1]
Model Number PXI-2020/2022
Function Result under 25°C ± 5°C
Offset Error (gain = 1) ±0.6 mV (Typical)
Gain Error (gain = 1) ±0.02% (Typical)
–3dB small signal bandwidth gain = 1 : 1 MHz
gain = 4 : 700 KHz
System Noise gain = 1 : 0.5 mVrms
gain = 4 : 0.2 mVrms
CMRR*(2) (DC) gain = 1 : 80 dB
gain = 4 : 80 dB
Spurious-free dynamic range (SFDR) 87 dB
Signal-to-noise and distortion ratio
(SINAD) 82 dB
Total harmonic distortion (THD) –85 dB
Signal-to-noise ration (SNR) 84 dB
Effective number of bits (ENOB) 13.3 bits
Table 1-9: Performance

Getting Started 9
2 Getting Started
This chapter describes the proper installation environment, instal-
lation procedures, its package contents and basic information user
should be aware of. The PXI-2020/2022 performs an automatic
configuration of the IRQ, and port address. The PCI_SCAN soft-
ware utility can be used to read the system configuration.
NOTE: Diagrams and images of equipment mentioned are used for
reference only. Actual system configuration and specs may
vary.
2.1 Installation Environment
Whenever unpacking and preparing to install any equipment
described in this manual, please refer to the Important Safety
Instructions chapter of this manual. Only install equipment in well
lit areas on flat, sturdy surfaces with access to basic tools such as
flat and cross head screwdrivers, preferably with magnetic heads
as screws and standoffs are small and easily misplaced.
Recommended Installation Tools
Philips (cross-head screwdriver)
Flat-head screwdriver
Anti-static wrist strap
Anti-static mat
The PXI-2020/2022 contains several electro-static sensitive com-
ponents that can be easily be damaged by static electricity. The
equipment should be handled on a grounded anti-static mat and
the operator should wear an anti-static wristband during the
unpacking and installation procedure. Please also inspect the
components for apparent damage. Improper shipping and han-
dling may cause damage to the components. Be sure this is no
shipping and handling damage on the components before continu-
ing. CAUTION The equipment must be protected from static dis-
charge and physical shock. Never remove any of the socketed
parts except at a static-free workstation. Use the anti-static bag
shipped with the product to handle the equipment and wear a
grounded wrist strap when servicing.

10 Getting Started
2.2 Package Contents
Before continuing, check the package contents for any damage
and check if the following items are included in the packaging:
PXI-2020/2022 Simultaneous Data Acquisition Card
ADLINK All-in-one DVD
Software Installation Guide
PXI-2020/2022 User’s Manual.
Caution Do not install or apply power to equipment that is damaged
or if there is missing/incomplete equipment. Retain the ship-
ping carton and packing materials for inspection. Please
contact your ADLINK dealer/vendor immediately for assis-
tance. Obtain authorization from your dealer before returning
any product to ADLINK.

Getting Started 11
2.3 Mechanical Drawing and I/O Connectors
Figure 2-1: PXI-2020/2022 PCB Layout
The ADLINK PXI-2020/2022 is packaged in a Euro-card form fac-
tor compliant with PXI specifications measuring 160 mm in length
and 100 mm in height (not including connectors). The connector
types and functions are described as follows.

12 Getting Started
SMB Connector
SMB Connector 1: TRG IO
SMB Connector 2: Sync CLK_OUT1
SMB Connector 3: Sync CLK_OUT0
SMB Connector 4: CLK IN
Connector Direction Type Description/Function
TRG IO Input
Output SMB The TRG IO is a bidirectional port for external digi-
tal trigger input or output.
CLK OUT1 Output SMB
The CLK OUTOUT 1 is a 50Ω, DC-coupled output;
CLK_OUT0 and CLK_OUT1 is from the same
source.
CLK OUT0 Output SMB
The CLK OUTPUT 0 is a 50Ω, DC-coupled output;
CLK_OUT0 and CLK_OUT1 is from the same
source.
CLK IN Input SMB The CLK IN is a 50Ω, AC-coupled external time-
base input.
Table 2-1: SMB Connector
TRG IO, as an Input Port
Connector type SMB
Compatibility 3.3 V LVTTL(Low Voltage), 5 V tolerant
Input Logic Level Input Low voltage: 0.8V (max)
Input high voltage: 2.0 (min)
Maximum Input Overload -0.5 V to +5.5 V
Trigger Polarity Rising edge or falling edge (Software pro-
grammable)
Minimum Pulse Width 12.5 ns
Table 2-2: TRG IO, as an Input Port