Agilent Technologies 16517A Service manual

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User’s Reference
Publication number 16517-97009
February 2000
For Safety information, Warranties, and Regulatory
information, see the pages behind the Index
Copyright Agilent Technologies 1987-2000
All Rights Reserved
Agilent Technologies
16517A/18A 4-GSa/s Timing
and 1-GSa/s Synchronous State
Logic Analyzer

The Agilent Technologies 16517A 4-GSa/S Timing and 1-GSa/S State Logic Analyzer
ii

In This Book
The User’s Reference contains field and
feature definitions. Use this part of the
manual set for information on what the
menu fields do, what they are used for,
and how the features work.
The User’s Reference is divided into
chapters covering general product
information and probing. In addition,
there are separate chapters for each
analyzer menu, a chapter for markers, a
chapter for error messages, and a chapter
for instrument specifications.
You have the choice of using the analyzer
as either a synchronous state analyzer or
a timing analyzer. Some menus in the
analyzer will change depending on the
acquisition mode used. For example,
because a timing analyzer does not use
external clocks, the external clock
assignment fields in the Format menu will
not be available.
If a menu field is only available to a
particular acquisition mode, the field is
designated (Timing only) or (State only)
after the field name. If no designation is
shown, the field is available for both state
and timing.
General Information
1
Probing
2
The Format Menu
3
The Trigger Menu
4
The Listing Menu
5
The Waveform Menu
6
The Compare Menu
7
The Chart Menu
8
Markers and
Stop Measurement
9
Skew Adjust
10
Error Messages
11
Specifications and
Characteristics
12
Index
Installation and Service
13
iii

iv

Contents
1 General Information
User Interface 1–4
Configuration Capabilities 1–5
Accessories Supplied 1–6
Accessories Available 1–6
2 Probing
Probing 2–2
Probing System Description 2–4
Probing Accessories 2–6
Probing Considerations 2–9
Orientation Between Probe Tip and Interface 2–10
3TheFormatMenu
Synchronous State Acquisition Mode 3–3
Conventional Timing Acquisition Mode 3–4
Select Clock Field (State Only) 3–5
Set Sample Offset Field (State Only) 3–6
Pod Threshold Field 3–8
Label Polarity Fields 3–9
Bit Assignment Fields 3–10
Activity Indicators 3–12
Symbols Field 3–12
4TheTriggerMenu
Trigger Sequence Levels 4–4
Modify Trigger Field 4–6
Contents–1

Pre-defined Trigger Macros 4–9
Using Macros to Create a Trigger Specification 4–11
Timing Trigger Macro Library 4–12
State Trigger Macro Library 4–15
Creating a User Level 4–17
Resource Terms 4–25
Assigning Resource Term Names and Values 4–27
Label and Base fields 4–31
Acquisition Control 4–32
Trigger Position Field 4–33
Sample Period Field (Timing only) 4–34
Samples/Clock Field(State only) 4–34
Armed By Field 4–37
5TheListingMenu
Markers Field 5–3
Data Roll Field 5–3
Label and Base Fields 5–4
Show States All/Ext Clock (State only) 5–5
Sample Offset Field (State only) 5–6
Specify Patterns Field 5–6
Acquisition Control Field 5–6
6TheWaveformMenu
Acquisition Control Field 6–3
Accumulate Field 6–4
Seconds Per Division Field 6–5
Delay Field 6–6
Sample Period Display (Timing only) External Clock Period Display (State
only) 6–7
Markers Field 6–8
Contents
Contents–2

Waveform Display 6–9
Display Location Reference Line 6–10
External-Clock Indicators (State only) 6–11
Blue Bar Field 6–12
Channel Mode Field 6–14
Module and Label Fields 6–16
Action Insert/Replace Field 6–17
Delete and Delete All Fields 6–18
Waveform Size Field 6–19
Sample Offset Field (State only) 6–20
Reset Statistics Field 6–20
7TheCompareMenu
Reference Listing Field 7–4
Difference Listing Field 7–5
Copy Listing to Reference Field 7–7
Find Error Field 7–8
Compare Full / Compare Partial Field 7–9
Mask Field 7–10
Specify Stop Measurement Field 7–11
Data Roll Field 7–14
Bit Editing Field 7–15
Label and Base Fields 7–16
8TheChartMenu
The Y Markers 8–4
Markers Field 8–5
Rescale 8–6
Axis Control Field 8–8
Accumulate Field 8–11
Contents
Contents–3

9 Markers and Stop Measurements
Markers Field 9–3
Pattern Markers 9–4
Find X-pattern / O-pattern Field (Listing and Chart) 9–5
Occurrence Counter Field (Listing and Chart) 9–5
From Trigger / Start / X Marker Field 9–6
X-pat / O-pat Occurrence Fields (Waveform menu) 9–7
Center Screen Field (Waveform and Chart) 9–7
X to O Display Field (Waveform and Chart) 9–7
Specify Patterns Field 9–8
Stop Measurement Field 9–10
Clear Pattern Field 9–11
Time Markers 9–12
Trig to X / Trig to O Fields 9–13
Marker Label / Base and Display (Waveform menu) 9–13
Statistics Markers 9–14
Reset Statistics Field (Waveform menu) 9–15
Clear Statistics Field (Chart menu) 9–15
10 Skew Adjust
To Calibrate the Data Acquisition Module 10–2
To Adjust the Channel-to-Channel Skew 10–3
Connect the Logic Analyzer 10–3
Set Up the Logic Analyzer 10–4
To Save or Discard the Skew Factors 10–6
Contents
Contents–4

11 Error Messages
Error Messages 11–3
Warning Messages 11–4
Advisory Messages 11–7
Skew Adjust and Performance Verification Messages 11–8
12 Specifications and Characteristics
Specifications 12–3
Characteristics 12–4
13 Installation and Service
To Inspect the Module 13–3
To Prepare the Mainframe 13–3
To Configure a One-card Module 13–5
To Configure a Multi-card Module 13–5
To Install the Module 13–7
To Test the Module 13–8
To Perform the Self-tests 13–9
Access the Self-tests 13–9
Perform the Functional Tests 13–10
Perform the Skew Adjustments and Tests 13–11
Exit the Self-tests 13–12
To Return Assemblies 13–13
To Clean the Logic Analyzer Module 13–13
Index
Contents
Contents–5

Contents–6

1
General Information

Logic Analyzer Description
The Agilent Technologies 16517A/18A Synchronous Timing Analyzer
module is part of a family of general-purpose logic analyzers. The
16517A/18A is a multi-card module that is used with the Agilent
Technologies 16500 mainframes and the Agilent Technologies 16501A
Expansion Frame.
The Agilent Technologies 16500 mainframe is designed for use by
digital and microprocessor hardware and software designers. The
16500 mainframe has GPIB, RS-232-C, and Ethernet LAN interfaces
for hard copy printouts, postprocessing of measurement data, and
control by a host computer.
The 16517A/18A analyzer can be configured in the following ways:
•The 16517A master can run as a single-card module or have up to
four 16518A expansion cards added for a multi-card module.
•Channel width varies from 16 channels on the 16517A master, up
to 80 channels when four 16518A expansion cards are added.
•Channel memory depth is 64 Kbytes in both full-channel state and
timing modes or 128 Kbytes in half-channel timing mode.
Timing Modes
The 16517A/18A has two timing modes. In full-channel timing mode,
data is sampled at up to 2 GHz. In half-channel timing mode, data is
sampled at 4 GHz.
Synchronous State Mode
In the full-channel state mode, a synchronous external clock running
at speeds up to 1 GHz can be used as the sample clock. In addition,
the sample point can be offset to ensure a sample where you know
data is valid.
1–2

Not only can you sample at the external clock transitions, but you can
set the analyzer to oversample, in powers of two, up to 32x, or, up to a
maximum of 2 GHz sample rate. Each point of oversampling is
precisely distributed evenly within the external clock period.
Triggering
Defining a trigger specification is as easy as picking a predefined
macro from a trigger macro library. Trigger macros can be used by
themselves or in combination with each other. Resource terms
include four global patterns, two global edges, and one level
dependent timer/counter. By using trigger macros, or defining your
own trigger specification, the user-friendly and flexible triggering
architecture lets you create a large array of trigger sequencing or
qualification needed.
Acquisition Control
Data storage can begin at either the start, center, end, or a
user-defined point within memory. In addition, if the data of interest
occurs a relatively long time after trigger, you can delay storage after a
trigger by a user-defined amount. With all the acquisition control
available, you can fill acquisition memory very efficiently.
Measurement Display
Measurement data is displayed as waveforms or state data listings.
State data can be compared bit by bit to a user-defined reference
image. In the state listing, you can choose to display either sample
clock transitions or both sample clock and oversampling clock
transitions. In the timing waveform display, you can show state values
integrated in the waveform.
General Information
1–3

User Interface
The Agilent Technologies 16500 Logic Analysis System has four easy-to-use
user interface devices: the knob, the touchscreen, the optional mouse
(standard in the 16500C), and the optional keyboard.
The knob on the front panel is used to move the cursor on certain menus, to
increment or decrement numeric fields, and to roll the display.
The touchscreen fields can be selected by touch or with the optional mouse.
To activate a touchscreen field by touch, simply touch the screen over any
dark blue box on the display with your finger until the field changes color.
Then remove your finger from the screen to activate your selection. The area
under your finger when you remove it from the screen is the area selected.
To activate a field with the mouse, position the cursor (+) of the mouse over
the desired field and press the left button of the mouse.
The keyboard can control all instrument functions by using special function
keys, the arrow keys, and the ENTER key. Alphanumeric entry is simply
typed in.
All user interface devices are discussed in more detail in the Agilent
Technologies 16500 User’s Reference.
General Information
User Interface
1–4

Configuration Capabilities
The logic analyzer can be configured as a single- or multi-card module. The
number of data channels range from 16 channels using just the 16517A, up to
80 channels when four 16518A expansion cards are connected. A
half-channel acquisition mode is available which reduces the channel width
by half, but doubles memory depth from 64 Kbits to 128 Kbits per channel.
The configuration guide below illustrates the channel width and memory
depth combinations in all acquisition modes.
Table 1-1
Conventional Timing Modes
One-Card
Module
Two-Card
Module
Three-Card
Module
Four-Card
Module
Five-Card
Module
Full Channel 16 channels
64 Kbits Deep 32 channels 64 Kbits Deep 48 channels 64 Kbits Deep 64 channels 64 Kbits Deep 80 channels 64 Kbits Deep
Half Channel 8 channels
128 Kbits Deep 16 channels 128 Kbits Deep 24 channels 128 Kbits Deep 32 channels 128 Kbits Deep 40 channels 128 Kbits Deep
Table 1-2
Synchronous State Mode
One-Card
Module
Two-Card
Module
Three-Card
Module
Four-Card
Module
Five-Card
Module
Full Channel 16 channel
64 Kbits Deep 32 channel 64 Kbits Deep 48 channel 64 Kbits Deep 64 channel 64 Kbits Deep 80 channel 64 Kbits Deep
General Information
Configuration Capabilities
1–5

Accessories Supplied
The table below lists the accessories supplied with your logic analyzer. If any
of these accessories are missing, contact your nearest Agilent Technologies
sales office. If you need additional accessories, refer to Accessories for
Agilent Logic Analyzers .
Table 1-3 Accessories Supplied
Accessory Quantity
Probe Pod 2
Probe Accessory Kit 1
Cable Assembly 1
Operating system disks 1
User’s Reference 1
Accessories Available
There are a number of accessories available that will make your measurement
tasks easier and more accurate. You will find these listed in Accessories for
Agilent Logic Analyzers, available from your Agilent Technologies Sales
Office.
General Information
Accessories Supplied
1–6

2
Probing

Probing
This chapter describes the probing system used by the 16517A/18A
logic analyzer. It also contains information about the probing
accessories, how to connect them to the probing system, and how to
connect the probing system to the target system.
Probing Options
You can connect the logic analyzer to your system under test in one of
the following ways:
•The standard general purpose probing (provided).
•Agilent Technologies E2445A User-Definable Interface (optional).
•Microprocessor and bus specific interfaces (optional).
General-Purpose Probing
General-purpose probing involves connecting the logic analyzer
probes directly to your target system without using any interface.
General purpose probing does not limit you to specific hook up
schemes as, for example, the probe interface does. General-purpose
probing uses grabbers that connect to both through hole and surface
mount components.
General-purpose probing is the standard probing option provided with
the logic analyzer. There is a full description of its components and
use later in this chapter.
2–2

In addition to the supplied probing system, the logic analyzer can be
connected to a target system using the following probing options:
The E2445A User-Definable Interface
The optional E2445A User-Definable Interface module allows you to
connect the logic analyzer to the microprocessor in your target system
using a breadboard which you custom wire to your system.
The 16517-27601 SMA Adapter
The optional SMA adapter allows you to connect the individual probes
to SMA cables.
Microprocessor and Bus Specific Interfaces
The 16517A/18A does not support inverse assembly. In addition, the
16517A/18A requires that any preprocessor used be a non- terminated
preprocessor. The analyzer requires a clear connection with no
termination.
Microprocessors are supported by universal interfaces or
preprocessor interfaces, or in some cases both. There are a number of
microprocessor and bus specific interfaces available as optional
accessories listed in Accessories for Agilent Logic Analyzers.
Universal interfaces are aimed at initial hardware turn-on, and will
provide fast, reliable, and convenient connections to the
microprocessor system.
Preprocessor interfaces are aimed at hardware turn-on and
hardware/software integration, and will provide the following:
•All clocking and demultiplexing circuits needed to capture the
system’s operation.
•Additional status lines to further decode the operation of the CPU.
•Bus interfaces to support bus analysis for GPIB, RS-232-C, RS-449,
SCSI, VME, VXI, ISA, EISA, MCA, FDDI, Futurebus+, JTAG, SBus,
PCI, and PCMCIA.
Probing
2–3