Akai S612 User manual

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MIDI DIGITAL SAMPLER
MODEL
SAMPLER DISK DRIVE
MODEL

ABBREVIATION FOR SERVICE MANUAL
MODEL S612
ABBREVIATION EXPLANATION ABBREVIATION EXPLANATION
ALTER ALTERnating MON MONitor
BUSDIR BUS DIRection RFSH ReFreSH
CASSR CASSette Read RXD Receive Data
CASSW CASSette Write RD RdaD
CH CHannei SHOT one SHOT
cs Chip Select SIN Signal INput
DUB over DUB SLTSL SLoT SeLect
IORQ I/O ReQuest TRANS TRANSpose
LOOP LOOPing TRIG TRIGger
Ml Machin cycle 1TXD Transmit Data
MREQ Memoly REQuest V.REF V.REFerence
MIDI Musical instrument Digital Interface WR WRite
MODEL MD280
ABBREVIATION EXPLANATION ABBREVIATION EXPLANATION
B/A channel B/channel AMTON MoTor ON
C/D Command/Data QD Quick Disk
CE Chip Enable RD ReaD
CRC Cyclic Redandancy Check Character RDDT ReaD DaTa
CS Chip Select RTSA Request To Send A
CTSA Clear To Send ARTSB Request To Send B
Dsystem Data bus RXCA Receive Clock A
DCDA Data Carrier Detect ARXDA Receive Data A
DCDB Data Carrier Detect BSIO Serial Input Output
DIR DIRection SLTSL SLoT SeLect
DTRB Data Terminal Ready BTXCA Transmit Clock A
IEI Interrupt Enable In TXDA Transmit Data A
IORQ Input/Output ReQuest WR WRite
Ml Machine cycle 1WRDT WRite DaTa
MDST Media SeT WRGA WRite GAte
MERQ MEmory ReQuest WRPR WRite PRotect
MFM Modified Frequency Modulation d> system clock

AKAI satuKE mmun
TIONAL)
This additional Schematic Diagram is made for the Main
PCB of model S612.
Use this additional Schematic Diagram with the model
S612 Service Manual which published previously.
DIGITAL SAMPLER
MODEL
ADC0809 [8 BIT A/D CONVERTER]
(IC58)
START CLOCK
<L
IN 0
IN I
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
AO
AI
A2
ADDRESS
LATCH ENABLE
Vcc GND REF (+) REF OUTPUT
(-) ENABLE
BA9201 [8 BIT D/A CONVERTER]
(IC90 to 95)
DATA IN
I1.
D7D6 D5 D4 D3 D2 Dl DO
<2>

TC74C174P [HEX D-FFs]
(IC61.62, 63)
TC74HC74 [DUAL DFLIP-FLOP] TC74HC175P [QUAD D-FFs]
(IC 17to 19) (IC60)
10 10 20 20 30 30 4D 40 50 50 60 60 CLR2 02 CLK 2PR 210 ?0 20 30 30 40 40
/SHS) (7>—(fi) (iqHF) (I5> FUNCTION TABLE
iINPUTS [OUTPUTS
FUNCTION TABLE
TC74HC138P [3 to 8DEMULTIPLEXER]
(IC11, 12)
INPUTS OUTPUTS |
PR CLR CLK DQ0
LHXX H L
HLX X LH
L L XXH- H-
HHtHHL
HHtLLH
HHLXQO 00
OATA
OUTPUTS
TC74HC1 39P [DUAL 2to 4DEMULTIPLEXERS]
(IC2)
ENABLE 2G
DATA
OUTPUTS
TC74HC157P [2 to 1DATA SELECTORS]
(IC32, 33)
FUNCTION TABLE
INPUTS OUTPUTS
ENABLE SELECT
G1 G2> C8AYO Y1 Y2 Y3 Y4 Y5 Y6 Y7
~X lUT ~X X-HHHHHHHH
LXX XXHHHHHHHH
HLL LLLHHHHHHH
HLL LHHLHHHHHH
HLL HLHHLHHHHH
HLL HHHHHLHHHH
HLH L L HHHHLHHH
HLH LHHHHHHLHH
HLH HLHHHHHHLH
HLH HHHHHHHHHL
FUNCTION TABLE
INPUTS OUTPUTS
ENABLE SELECT
GBAYO Y1 Y2 Y3
HX X H H HH
LLL L HHH
LLHHLH H
LHLH H LH
LHHHHHL
TC74HC245P [QCTAL 3STATE TRANSCEIVER]
(IC25)
DIR At A2 A3 A4 A5 A6 A7 AS GND
TC74HC259P [8 BIT ADDRESSABLE LATCHES] (IC42, 43)
nui >
I.ArCH SEI
TC74HC373 [3 STATE OCTAL D-TYPE LATCH]
I(IC21
)
FUNCTION TABLE
LLBdata to Abus
LHAdata to Bbus
HXIsolation
FUNCTION TABLE
gill

TC74HC4040P [12-STAGE BINARY COUNTER]
(IC23, 24)
UADD-FFs]
FUNCTION TABLE
”INPUTS "" OUTPUTS
CLOCK (io)
CLEAR QL
4HC245P [QCTAL 3STATE TRANSCEIVER]
FUNCTION TABLE
FUNCTION TABLE
OUTPUTS:
ENABLE
G1 G2* :
select:
4HC259P [8 BIT ADDRESSABLE LATCHES] (IC42, 43) X: DON’T CARE
,uPD710540P [PROGRAMMABLE
^PD8253C-2 INTERVAL TIMER]
(IC5, 6, 7, 8)
//PD780C [8 BIT CPU]
(IC1)
16 BIT ADDRESS
BUS WRITE CONTROL
FUNCTION TABLE BEAD CONTROL
INPUTS CHIP SELECT
OUTPUTS DATA BUS
ENABLE CLOCK 16BIT ADDRESS BUS ADDRESS BUS
COUNTER CLOCK
COUNTER OUT
COUNTER SATE
COUNTER CLOCK
BBIT DATA BUS COUNTER OUT COUNTER CLOCK
COUNTER GATE
COUNTER GATE
LATCH STL COUNTER OUT
REFRESH
MACHINE CYCLE ONE
C74HC373 [3 STATE OCTAL D-TYPE LATCH]
C21) //PD8255 AC-2
(IC4 1
)
8USR0 ©
INTERRUPT REQUEST
LATCH
ENABLE NON MASKABLE
INTERRUPT WAIT CONTROL
HUSAK fj)
HALT STATE -.10} HALT BUS AC KNOW (FORE
QS) MR EO
MEMORY BEQUEST WRITE CONTROL LEO DISPLAY DRIVE
LEO DISPLAY DRIVE
inbut/output reoufst
:
IORQ READ CONTROL
-PD8237 AC-5 (IC9, 10) READ CONTROL WRITE CONTROL
[PROGRAMBLE DMA CONTROLHR] CHIP SELECT
I/O READ
ADDRESS BUS
AOORCSS BUS
CLEAR OUTPUT STATE
HALL OUTPUTS ="L”
LNO CHANGE
LADVANCE TO NEXT STATE
Control
Inputs Operation
GDIR
L L Bdata to Abus
LHAdata to Bbus
HXIsolation
Xc
(V) 07 Vcc ©
©D6 WR 0}
©06 RO ©
©D4 CS (21
)
©D3 A l©
®DZ AO ©
(7)Dl CLK2 (w
(J) 00 OUT 2@
(5) CLK oGATE 2
©OUT 0CLK 1©
©GATE 0GATEl ©
g) GND GUT |(J3)
rER FACE]

-L:-X~-ratr,;",: tig~~|~
FUNCTION TABLE
(INPUTS OUTPUTS
|ENABLE |SELECT
G1 G2* CBAYO Y1 Y2 Y3 Y4 Y5 Y6 Y7
XHXXXHHHHHHHH
LX X X XHHHHHHHH
HL L ALLHHHHHHH
HL L 1HHLHHHHHH
HLLHLH H LHHHHH
HL L HHHH H LHHHH
HLHLLHH H HLHHH
HLHLHHRHHHLHH
HLHHLHH H H H HLH
HLHHH H HHHHHHL
FUNCTION TABLE
INPUTS OUTPUTS
ENABLE
G
SELECT
BAYO Y1 Y2 Y3
HXXHHH H
LL L LHHH
L L H H LH H
LHLH H LH
LHHHH H L
FUNCTION TABLE
jINPUTS
Select Strobe
GY
XHL
L L A
HL B
FUNCTION TABLE
INPUT OUTPUTS
QA ~QD
Clear CK Enable Output control
G1 G2 M|N
LIT LL-ID ~4D
LHX--
XH
HXXX-LLLL
-HXZ
XH
GDIR
LLBdata to Abus
LHAdata to Bbus
HXIsolation
TC74HC259P [8 BIT ADDRESSABLE LATCHES] (IC42, 43)
FUNCTION TABLE
CLOCK CLEAR OUTPUT STATE
XHALL OUTPUTS =”L"
fLNO CHANGE
_1LADVANCE TO NEXT STATE
X: DON’T CARE
m
TC74HC373 [3 STATE OCTAL D-TYPE LATCH]
(IC21)
LATCH
ENABLE
OUTPUT 10 10 2D 20 3Q 3D 4D 40 GND
CONTROL
TC74HC374 [3 STATE OCTAL D-TYPE FLIP-FLOP]
(IC54)
Vcc 60 8D 70 70 60 6D 50 50 CLOCK FUNCTION TABLE
Output
Control Clock Data Output
LtHH
LTLL
LLXQo
HX X Z
APD780C [8 BIT CPU]
(IC1)
I6BIT ADDRESS BUS
REFRESH
MACHINE CYCLE ONE
RESET
BUS REOUEST
WAIT CONTROL
BUS ACKNOWIEDBE
WRITE CONTROL
READ CONTROL
^PD8237 AC-5 (IC9, 10)
[PROGRAMBLE DMA CONTROLER]
ADDRESS BUS
END OF PROCESS
ADDRESS BUS
+SV
DATA BUS
DMA ACKNOWIEOGE
DATA BUS
//PD710540P [PROGRAMMABLE
fiPD8253C-2 INTERVAL TIMER]
(IC5, 6, 7, 8)
-E5V
WRITE CONTROL
READ CONTROL
CHIP SELECT
ADDRESS BUS
COUNTER CLOCK
COUNTER OUT
COUNTER GATE
COUNTER CLOCK
COUNTER SATE
COUNTER OUT
/iPD8255 AC-2 [INTER FACE]
(IC41)
OPERATION
BUTTON

(IC32, 33
TC74HC
(IC55)
14)
G
ENABLE
LLBdata to Abus
LHAdata to Bbus
HXIsolation
o
o
I
EFUNCTION TABLE
Output
Control
Latch
Enable
GData 373
Output
LHHH
LHLH
LLXQo
HXXZ
KFUNCTION TABLE
Output
Control Clock Data Output
LtHH
LtLL
LLXQo
HXXZ

JACK
JACK
POWER