Akm Ak4537 User manual

ASAHI KASEI [AK4537]

MS0202-E-04 2005/04

- 1 -

GENERAL DESCRIPTION

The AK4537 targeted at PDA and other low-power, smallsizeapplications. It features a 16-bit stereo

CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits

include a Microphone-Amplifier and an ALC (Auto Level Control)circuit. The AK4537 isavailable ina

52-QFN, utilizing less board space thancompetitive offerings.

FEATURES

1. Resolution: 16bits

2. Recording Function

xStereo Mic Input

xStereo LineInput

x1st MIC Amplifier : +20dB or 0dB

x2nd Amplifier with ALC

+27.5dB a-8dB, 0.5dB Step (MIC input)

+12dB a-23.5dB,0.5dBStep(LINE input)

xADC Performance : S/(N+D) : 79dB,DR, S/N : 83dB (MIC input)

S/(N+D) : 88dB,DR, S/N : 91dB (LINE input)

3. Playback Function

xDigital De-emphasis Filter (tc=50/15Ps,fs=32kHz, 44.1kHz, 48kHz)

xDigital Volume (0dB a-127dB, 0.5dB Step, Mute)

xStereoHeadphone-Amp

-S/(N+D) : 70dB,S/N: 90dB

- Output Power : 15mW@16:(HVDD=3.3V)

- Click Noise Free atPower ON/OFF

xMono Speaker-Amp with ALC

- S/(N+D) : 64dB@150mW, S/N : 90dB

- BTL Output

- Output Power : 400mW@8:(BEEP Input,HVDD=3.3V)

300mW@8:(MIN Input, ALC2=OFF, HVDD=3.3V)

xMono and Stereo BeepInputs

xMono LineOutput

- Differential Output

- Performance :S/(N+D) : 89dB, S/N : 95dB

xStereoLine Output

- Performance :S/(N+D) : 88dB, S/N : 92dB

4. Power Management

5.Master Clock

(1)PLL Mode

xFrequencies : 11.2896MHz, 12MHz and12.288MHz

xInput Level :CMOS

(2) External Clock Mode

xFrequencies : 2.048MHz a12.288MHz

6. Output MasterClockFrequencies : 32fs/64fs/128fs/256fs

7. Sampling Rate:

(1)PLL mode

x8kHz,11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz,48kHz

(2)External Clock mode

x8kHz a48kHz

8. Control mode: 4-wire Serial / I2C Bus

9.Master/Slave mode

16-Bit '6 StereoCODEC with MIC/HP/SPK-AMP

AK4537

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MS0202-E-04 2005/04

- 2 -

10. AudioInterface Format : MSB First, 2’s compliment

xADC : I2S, 16bitMSB justified

xDAC : I2S, 16bitMSB justified, 16bit LSBjustified

11. Ta = -10a70qC

12. Power Supply: 2.4V a3.6V (typ. 3.3V)

13. Power Supply Current

xAVDD+DVDD : 19mA

xPVDD : 1.2mA

xHVDD(HP-AMP=ON, SPK-AMP=OFF) : 4mA

xHVDD (HP-AMP=OFF,SPK-AMP=ON): 7mA

12. Package : 52pin QFN (AK4534 pin compatible)

Block Diagram

ALC1

(IPGA)

AVDDAVSS

MICOUTL LIN1

LRCK

BICK

SDTO

SDTI

PDN

DSP

and

uP

DVDDDVSS

HVDD

HVSS

VCOM

MUTET

xxxx

ALC2

MOUT-

HPL

xxx

PMHPL

HP-AMP

HPR

xxx

PMHPR

HP-AMP

Control

Register

Interface

Audio

PMSPK

SPK-

AMP

SPP

SPN

I2C

CSN/CAD1

CCLK/SCL

CDTI/SDA

CDTO

PMMO

CAD0

MOUT+

XTI/MCKI

XTO

MCKO

VCOC

PVDD

PVSS

MIX

MPEMICPower

Supply

EXT/MICR

xxx

INT/MICL

xxx

MIC-AMP

0dBor20dB

MPIMICPower

Supply

M/S

HPF

ADC

PMDAC

DATT

SMUTE

DAC

MIN MOUT2

MIX

PLL

PMPLL PMXTL

BEEPLBEEPR

PMBPS

BEEPM

PMBPM

LIN2

ALC1

(IPGA)

RIN1

LOUT

ROUT

RIN2

MIC-AMP

0dB or20dB

MICOUTR

PMMICR

ATT

PMLO

ATT

PMMICL

PMMICR orPMIPGR

PMMICLorPMIPGLPMADLorPMADR

MIX

PMMIX

MIX

PMMICL

Figure 1. Block Diagram

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ASAHI KASEI [AK4537]

MS0202-E-04 2005/04

- 3 -

Ordering Guide

AK4537VN 10 a+70qC 52pin QFN (0.4mmpitch)

AKD4537 Evaluation board for AK4537

Pin Layout

EXT/MICR

RIN1

52 51

150 49 48 47 46 45 44 43 42 39

38

37

36

35

34

33

32

31

30

29

2423222120191817161514

2

3

4

5

6

7

8

9

10

11

AK4537VN

Top View

MPE

MPI

INT/MICL

VCOM

AVSS

AVDD

PVDD

PVSS

CCLK/SCL

DVDD

DVSS

XTO

XTI/MCKI

M/S

SPP

SPN

HVDD

HVSS

HPR

HPL

BEEPL

BEEPR

BEEPM

LIN2

RIN2

MOUT+

MOUT-

LOUT

MOUT2

12VCOC

25

28 NC

41

MIN

CSN/CAD1

PDN

CDTI/SDA

CDTO

I2C

SDTI

SDTO

LRCK

BICK

MCKO

NC

13 26 27

40

NC

ROUT

LIN1

CAD0

MUTET

MICOUTL

MICOUTR

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MS0202-E-04 2005/04

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Comparison with AK4534

1. Function

Function AK4534 AK4537

Line Input No Yes (Stereo)

Mic Input Mono Stereo

IPGAMono Stereo

StereoLine Output No Yes

SPK-Amp Gain Select No Yes

MOUTGain Select No Yes

Pathfrom IPGA Lch to Analog

Output No Yes

2. Pin

pin# AK4534 AK4537

1 MICOUT MICOUTL

2 TST1 MICOUTR

3 EXT EXT/MICR

6 INT INT/MICL

42 TST2 ROUT

43 TST3 LOUT

46 TST4 RIN2

47 TST5 LIN2

51 AIN LIN1

52 NC RIN1

3.Register

Addr Contents

00HPMIPGL (IPGA Lch Power Control)isadded.

PMLO (Stereo Line Output Power Control)isadded.

01HSPKG (SPK-AmpOutput Power Select) isadded.

02HMOGN (MOUT GainSelect)isadded.

MICM(IPGA Lch oMOUT) is added

03HPSLO (Stereo Line Output Power Save Mode Select) isadded.

MICL (IPGA LchoLOUT/ROUT, HP-Amp, SPK-Amp) is added.

05HHPLM, HPRM(HP-Amp Mono Output Select) isdeleted.

HPM (HP-Amp Mono Output Select) isadded.

07HIPGAC (IPGA Control) isadded.

0EH ATTM (IPGA Lch oMOUTATT Select) is added.

ATTS2-0 (IPGA Lch oLOUT/ROUT, HP-Amp,SPK-Amp ATT Select) isadded.

0FH IPGAR6-0 (RchIPGA Control)is added.

10HPMADR (ADC Rch Power Control)isadded.

PMMICR (MIC-ampRch Power Control)isadded.

PMIPGR (IPGA Rch Power Control)isadded.

INL (IPGA Lch Input Select) isadded.

INR (IPGA Rch Input Select) isadded.

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MS0202-E-04 2005/04

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PIN/FUNCTION

No. Pin NameI/O Function

1 MICOUTL O MIC-Amp Lch Output Pin

2 MICOUTR O MIC-Amp Rch Output Pin

EXT I External Microphone Input Pin (Mono Input) (PMMICRbit = “0”)

3 MICR I Stereo Microphone Rch Input Pin (PMMICRbit =“1”)

4 MPE O MIC Power SupplyPin for ExternalMicrophone / Stereo Microphone Rch

5 MPI O MIC Power SupplyPin for InternalMicrophone / Stereo Microphone Lch

EXT I InternalMicrophone Input Pin (Mono Input) (PMMICL bit =“0”)

6 MICR I Stereo Microphone Lch Input Pin (PMMICL bit = “1”)

7 VCOM O Common Voltage Output Pin, 0.45 x AVDD

Bias voltage of ADC inputs and DAC outputs.

8 AVSS - Analog Ground Pin

9 AVDD - Analog Power SupplyPin

10 PVDD - PLL Power SupplyPin

11 PVSS - PLL Ground Pin

12 VCOC O Output Pin for Loop Filterof PLL Circuit

Thispin should be connected toPVSSwith one resistor and capacitor in series.

13 NC- No Connect.

Thispin should be left floating.

14 CAD0 I ChipAddress 0 Select Pin

15 PDN I Power-DownMode Pin

“H”:Power up, “L”: Power downreset and initializes the control register.

CSNI ChipSelectPin (I2C = “L”)

16 CAD1 I ChipAddress 1 Select Pin(I2C = “H”)

CCLK I Control DataClock Pin (I2C = “L”)

17 SCLI Control DataClock Pin (I2C = “H”)

CDTI I Control DataInput Pin (I2C = “L”)

18 SDA I/O Control DataInput Pin (I2C = “H”)

19 CDTO O Control DataOutput Pin (I2C = “L”)

20 I2C I Control Mode Select Pin

“H”:I2C Bus, “L”: 4-wireSerial

21 SDTI I Audio Serial DataInput Pin

22 SDTO O Audio Serial DataOutput Pin

23 LRCKI/O Input / Output Channel Clock Pin

24 BICKI/O Audio Serial DataClock Pin

25 MCKO O MasterClock Output Pin

26 NC- No Connect.

Thispin should be left floating.

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MS0202-E-04 2005/04

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No. Pin NameI/O Function

27 NC- No Connect.

Thispin should be left floating.

28 DVDD - DigitalPower Supply Pin

29 DVSS - DigitalGround Pin

30 XTO O X’talOutput Pin

XTI I X’talInput Pin

31 MCKI I External MasterClock Input Pin

32 M/S I Master/ Slave Mode Pin

“H” : Master Mode, “L” :Slave Mode

33 SPP O Speaker Amp Positive Output Pin

34 SPNO Speaker Amp Negative Output Pin

35 HVDD - Headphone Amp Power Supply Pin

36 HVSS - Headphone Amp Ground Pin

37 HPRO Rch Headphone Amp Output Pin

38 HPL O Lch Headphone Amp Output Pin

39 MUTET O MuteTimeConstant Control Pin

ConnectedtoHVSS pin witha capacitor for mute timeconstant.

40 MINI ALC Input Pin

41 MOUT2O Analog Mixing Output Pin

42 ROUT O Rch Stereo LineOutput Pin

43 LOUT O Lch StereoLine Output Pin

44 MOUTO Mono LineNegative Output Pin

45 MOUT+ O Mono LinePositive Output Pin

46 RIN2 I Rch Analog Input 2 Pin (LINE Input)

47 LIN2 I Lch Analog Input 2 Pin (LINE Input)

48 BEEPM I Mono Beep Signal InputPin

49 BEEPR I Rch Stereo Beep Signal InputPin

50 BEEPL I Lch StereoBeepSignal Input Pin

51 LIN1 I Rch Analog Input 1 Pin (MIC Input)

52 RIN1 I Lch Analog Input 1 Pin (MIC Input)

Note:Allinput pins except analog input pins (INT, EXT, LIN1, RIN1, MIN, BEEPM, BEEPL, BEEPR, LIN2 and RIN2)

should not be left floating.

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ASAHI KASEI [AK4537]

MS0202-E-04 2005/04

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ABSOLUTE MAXIMUM RATINGS

(AVSS, DVSS, PVSS, HVSS=0V;Note 1)

Parameter Symbol minmax Units

Power Supplies: Analog AVDD 0.3 4.6 V

DigitalDVDD

0.3 4.6 V

PLL PVDD

0.3 4.6 V

Headphone-Amp/ Speaker-Amp HVDD 0.3 4.6 V

|AVSS – PVSS|(Note 2) 'GND1 - 0.3 V

|AVSS – DVSS| (Note 2) 'GND2 - 0.3 V

|AVSS – HVSS| (Note 2) 'GND3 - 0.3 V

Input Current,Any Pin ExceptSupplies IIN - r10 mA

Analog Input Voltage VINA 0.3 AVDD+0.3 V

Digital Input Voltage VIND 0.3 DVDD+0.3 V

Ambient Temperature (powered applied) Ta 10 70 qC

Storage Temperature Tstg65 150 qC

Note1. All voltages withrespect to ground.

Note2. AVSS,DVSS, PVSS and HVSS must beconnected tothe sameanalog ground plane.

WARNING: Operation at or beyond these limits mayresult inpermanent damage tothe device.

Normal operation isnot guaranteed atthese extremes.

RECOMMENDEDOPERATING CONDITIONS

(AVSS,DVSS,PVSS, HVSS=0V; Note1)

Parameter Symbol min typ max Units

Power Supplies Analog AVDD 2.4 3.3 3.6 V

(Note 3) DigitalDVDD 2.4 3.3 AVDD V

PLL PVDD 2.4 3.3 AVDD V

HP /SPK-Amp HVDD 2.4 3.3 AVDD V

Note1. All voltages withrespect to ground.

Note3. The powerup sequence between AVDD, DVDD, HVDD and PVDD isnot critical.

It isrecommended thatDVDD and PVDD are the samevoltage as AVDD inorder toreduce the current at power

down mode.

* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

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MS0202-E-04 2005/04

- 8 -

ANALOG CHARACTERISTICS

(Ta=25qC;AVDD, DVDD, PVDD, HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs;

Signal Frequency=1kHz; 16bit Data; Measurementfrequency=20Hz a20kHz; unless otherwise specified)

Parameter min typ max Units

MIC Amplifier:

Input Resistance 20 30 40

k:

Gain(MGAIN bit = “0”) -0 -dB

(MGAIN bit = “1”) - 20 - dB

MICPower Supply:

Output Voltage (Note 4) 2.22 2.47 2.72 V

Output Current - - 1.25 mA

Input PGA Characteristics:

Input Resistance (LIN1, RIN1 pins) 5 10 15 k:

(Note 5) (LIN2, RIN2 pins) 30 60 90 k:

StepSize 0.1 0.5 0.9 dB

GainControl Range (LIN1, RIN1 pins) 8 - +27.5 dB

(LIN2, RIN2 pins)

23.5 - +12 dB

ADC Analog Input Characteristics: ALC1=OFF

Resolution 16 Bits

(Note 7) 0.168 0.198 0.228 Vpp

Input Voltage (Note 6) (Note 8) 1.68 1.98 2.28 Vpp

(Note 7) 71 79 - dBFS

S/(N+D) (1dBFS) (Note 8) - 88 - dBFS

(Note 7) 75 83 - dB

D-Range (60dBFS, A-weighted) (Note 8) - 91 - dB

(Note 7) 75 83 - dB

S/N (A-weighted) (Note 8) - 91 - dB

(Note 7) 75 90 - dB

Interchannel Isolation (Note 8) - 100 - dB

(Note 7) - 0.1 0.5 dB

Interchannel GainMismatch (Note 8) - 0.1 0.5 dB

DAC Characteristics:

Resolution - - 16 Bits

Stereo Line Output Characteristics: RL=10k:, DAC oLOUT, ROUT

Output Voltage (Note 9) 1.74 1.94 2.14 Vpp

S/(N+D) (-3dBFS) 78 88 - dBFS

S/N (A-weighted) 85 92 - dB

Interchannel Isolation - 100 - dB

Interchannel GainMismatch - 0.1 0.5 dB

Load Resistance 10 - - k:

Load Capacitance - - 30 pF

Note4. Output voltage isproportional to AVDD voltage. Vout =0.75 x AVDD.

Note5. When IPGA Gainischanged, this typical value changes between 8k:and 11k:(LIN1, RIN1), 48k:and 66k:

(LIN2, RIN2).

Note6. Input voltage is proportional toAVDD voltage. Vin = 0.06 x AVDD)@MicIn, Vin = 0.6 x AVDD(typ)@Line In.

Note7. MIC Gain=20dB, IPGA=0dB, ALC1=OFF, INT(MICL)/EXT(MICR) oIPGA oADC

Note8. IPGA=0dB, ALC1=OFF, LIN2/RIN2 oIPGA oADC

Note9. Output voltage isproportional to AVDD voltage. Vout =0.588 x AVDD.

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Parameter min typ max Units

Mono Line OutputCharacteristics:RL=20k:,DAC oMOUT+/MOUT-

Output Voltage (Note 10) MOGN=1, -17dB -0.31 -Vpp

MOGN=0, +6dB

3.56 3.96 4.36

Vpp

S/(N+D) (-3dBFS) MOGN=1, -17dB - 76 -

dBFS

MOGN=0, +6dB

79 89 -

dBFS

S/N (A-weighted) MOGN=1, -17dB - 79 -

dB

MOGN=0, +6dB

85 95 -

dB

Load ResistanceMOGN=1, -17dB 2 --k:

MOGN=0, +6dB 20 --

k:

Load Capacitance - - 30 pF

Headphone-Amp Characteristics: RL=22.8:, DAC oHPL/HPR, DATT=0dB

Output Voltage (Note 11) 1.54 1.92 2.30 Vpp

S/(N+D) (3dBFS) 60 70 - dBFS

S/N (A-weighted) 80 90 - dB

Interchannel Isolation 70 85 - dB

Interchannel GainMismatch - 0.1 0.5 dB

Load Resistance 20 - - :

Load Capacitance (C1 in Figure 2) - - 30 pF

(C2 in Figure 2) - - 300 pF

Speaker-Amp Characteristics: RL=8:, BTL, DAC oMOUT2 oMINoSPP/SPN, ALC2=OFF

Output Voltage SPKG= “0” (Po=150mW)2.47 3.09 3.71 Vpp

(Note 12) SPKG= “1” (Po=300mW)- 4.38 - Vpp

SPKG= “0” (Po=150mW)50 64 - dB

SPKG= “1” (Po=300mW)- 20 - dB

S/(N+D) (Po=250mW)- 60 - dB

S/N (A-weighted) 82 90 - dB

Load Resistance 8 - - :

Load Capacitance - - 30 pF

Note10. Output voltage isproportional to AVDD voltage. Vout =1.2 x AVDD at Full-differentialoutput.

Vout = 0.6 x AVDD atSingle-end Output.

Note11. Output voltage isproportional to AVDD voltage. Vout =0.582 x AVDD.

Note12. Output voltage isproportional to AVDD voltage.

Vout = 0.936 x AVDD(typ)@SPKG= “0”, 1.327 x AVDD(typ)@SPKG= “1” at Full-differentialoutput.

HPL/HPR pin

HP-Amp

47PF

C1

xxxx

16:

C2

6.8:

Figure 2. Headphone-ampoutput circuit

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MS0202-E-04 2005/04

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Parameter min typ max Units

BEEP Input: BEEPL, BEEPR, BEEPM pin

MaximumInput Voltage (Note 13) - - 1.98 Vpp

FeedbackResistance 14 20 26

k:

MonoInput: MINpin

MaximumInput Voltage (Note 14) - - 1.98 Vpp

Input Resistance (Note 15) 12 24 36 k:

Mono Output:RL=10k:, DAC oMIX oMOUT2

Output Voltage (Note 16) - 1.94 - Vpp

Load Resistance 10 - - k:

Load Capacitance (Note 17) - - 30 pF

Power Supplies

Power Up (PDN = “H”)

All Circuit Power-up:

AVDD+DVDD (Note 18) -19 29 mA

PVDD- 1.2 2 mA

HVDD: HP-AMPNormal Operation

No Output (Note 19) - 4 6 mA

HVDD: SPK-AMPNormal Operation

No Output (Note 20) - 7 18 mA

Power Down (PDN = “L”) (Note 21)

AVDD+DVDD -10 100 PA

PVDD - 10 100 PA

HVDD -10 100 PA

Note13. BEEP-AMPcan’t output more thanthismaximumvoltage.

Note14. MaximumInput Voltage isproportional to AVDD voltage. Vin = 0.6 x AVDD.

Note15. When ALC2Gainis changed, thistypical value changes between 22k:and 26k:.

Note16. Output Voltage isproportional toAVDD voltage. Vout = 0.588 x AVDD.

Note17. When the output pin drivesa capacitive load, aresistor shouldbe added in series between the output pin and

capacitive load.

Note18. PMMICL=PMMICR=PMADL=PMADR=PMDAC=PMMO=PMLO=PMSPK=PMHPL=PMHPR=PMVCM=

PMPLL=PMXTL=PMBPM=PMBPS= “1”, MCKO= “1” and MasterMode. AVDD=13mA(typ.),

DVDD=6mA (typ.).

AVDD=10mA(typ.), DVDD=6mA(typ.)atPMMICL=PMADL=PMDAC=PMMO=PMLO=PMSPK=PMHPL

=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM=PMBPS=“1”,PMMICR=PMADR=PMIPGR=“0”,

MCKO= “1” and Master Mode.

AVDD=10mA (typ.), DVDD=4mA (typ.) at MCKO= “0” in Slave Mode.

Note19. PMMICL=PMMICR=PMADL=PMADR=PMDAC=PMMO=PMLO=PMHPL=PMHPR=PMVCM=PMPLL=

PMXTL=PMBPM=PMBPS= “1” andPMSPK=“0”.

Note20. PMMICL=PMMICR=PMADL=PMADR=PMDAC=PMMO=PMLO=PMSPK=PMVCM=PMPLL=PMXTL=

PMBPM=PMBPS= “1” andPMHPL=PMHPR= “0”.

Note21. All digitalinput pins are fixed to DVDD or DVSS.

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FILTER CHARACTERISTICS

(Ta=10 a70qC; AVDD, DVDD, PVDD, HVDD=2.4 a3.6V; fs=44.1kHz; DEM=OFF)

Parameter Symbol min typ max Units

ADC Digital Filter (DecimationLPF):

Passband (Note22)

r0.1dB PB 0 - 17.4 kHz

1.0dB - 20.0 - kHz

3.0dB - 21.1 - kHz

Stopband SB 27.0 - - kHz

Passband RipplePR - - r0.1 dB

Stopband Attenuation SA 65 - - dB

Group Delay(Note 23) GD - 17.0 - 1/fs

Group DelayDistortion 'GD - 0 -

Ps

ADC Digital Filter (HPF):

FrequencyResponse (Note 22) 3.0dB FR - 3.4 - Hz

0.5dB - 10 - Hz

0.1dB - 22 - Hz

DAC Digital Filter:

Passband (Note22)

r0.1dB PB 0 - 20.0 kHz

6.0dB - 22.05- kHz

Stopband SB 24.1 - - kHz

Passband RipplePR - - r0.06 dB

Stopband Attenuation SA 43 - - dB

Group Delay(Note 23) GD - 16.8 - 1/fs

DAC Digital Filter + SCF:

FrequencyResponse: 0 a20.0kHz FR -

r0.5 - dB

BOOST Filter: (Note 24)

MIN 20Hz FR - 5.74 - dB

100Hz - 2.92 - dB

1kHz - 0.0 - dB

MID 20Hz FR - 5.94 - dB

100Hz - 4.71 - dB

1kHz - 0.14 - dB

MAX 20Hz FR - 16.04- dB

100Hz - 10.55- dB

FrequencyResponse

1kHz - 0.3 - dB

Note22. The passband and stopband frequencies scale withfs (systemsampling rate).

For example, ADC isPB=0.454*fs (@-1.0dB), DAC isPB=0.454*fs (@-0.01dB).

Note23. The calculated delaytimecaused by digitalfiltering. Thistimeis from the input of analog signal tosetting of the

16-bit dataof both channelsfrom the input registerto theoutput register of the ADC. Thistimeincludes the

group delay of the HPF. For the DAC, this timeis from setting the 16-bit dataof both channels from theinput

registerto the output of analog signal.

Note24. These frequencyresponses scalewith fs. If ahigh-level and low frequencysignal isinput, the analog output clips

to the full-scale.

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DC CHARACTERISTICS

(Ta=10 a70qC; AVDD, DVDD, PVDD, HVDD=2.4 a3.6V)

Parameter Symbol min typ Max Units

High-LevelInput Voltage VIH 70%DVDD - -V

Low-Level Input Voltage VIL - - 30%DVDD V

Input Voltage at AC Coupling (Note 25) VAC 50%DVDD - -V

High-LevelOutput Voltage (Iout=200PA) VOH DVDD0.2 - - V

Low-Level Output Voltage

(Except SDA pin: Iout=200PA) VOL - - 0.2 V

(SDA pin: Iout=3mA)VOL - - 0.4 V

Input Leakage Current Iin- - r10 PA

Note25. When AC coupled capacitor isconnectedtoMCKI pin.

SWITCHING CHARACTERISTICS

(Ta=10 a70qC; AVDD, DVDD, PVDD, HVDD=2.4 a3.6V; CL=20pF)

Parameter Symbolmin typ maxUnits

Master Clock Timing

CrystalResonator Frequency 11.2896 - 12.288 MHz

External Clock Frequency fCLK 2.048 - 12.288 MHz

Pulse Width Low tCLKL 0.4/fCLK - - ns

Pulse Width High tCLKH 0.4/fCLK - - ns

AC Pulse Width (Note 26) tACW0.4/fCLK - - ns

MCKO Output

Frequency fMCK0.256 - 12.288 MHz

DutyCycle:except fs=32kHz dMCK40 50 60 %

fs=32kHz at 256fs (Note 27) dMCK- 33 - %

LRCK Timing

Frequencyfs 8 - 48 kHz

DutyCycleSlave modeDuty 45 - 55 %

Mastermode Duty - 50 - %

Audio Interface Timing

Slave mode

BICK Period tBCK312.5 - - ns

BICK Pulse Width Low tBCKL 130 - - ns

PulseWidth High tBCKH 130 - - ns

LRCK Edgeto BICK “n” (Note 28) tLRB 50 - - ns

BICK “n” to LRCK Edge (Note 28) tBLR 50 - - ns

LRCKto SDTO (MSB) (Except I2Smode) tLRS - - 80 ns

BICK “p” toSDTO tBSD - - 80 ns

SDTI HoldTimetSDH 50 - - ns

SDTI Setup TimetSDS 50 - - ns

Master mode

BICK Frequency(BF bit= “0”) fBCK- 64fs - Hz

(BF bit = “1”) fBCK -32fs - Hz

BICK DutydBCK- 50 - %

BICK “p” toLRCK tMBLR 80 - 80 ns

BICK “p” toSDTO tBSD80 - 80 ns

SDTI HoldTimetSDH 50 - - ns

SDTI Setup TimetSDS 50 - - ns

Note26. Pulse width toground level when MCKI isconnected toa capacitor in series and a resistor isconnected to

ground (Refer toFigure 4).

Note27. PMPLL bit = “1”.

Note28. BICKrising edge must not occur at the sametimeas LRCKedge.

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Parameter Symbol min typ max Units

Control Interface Timing (4-wire Serial mode):

CCLKPeriodtCCK 200 - - ns

CCLK Pulse Width Low tCCKL 80 - - ns

Pulse Width High tCCKH 80 - - ns

CDTI Setup TimetCDS 40 - - ns

CDTI Hold TimetCDH 40 - - ns

CSN “H” TimetCSW 150 - - ns

CSN“p” toCCLK “n” tCSS 50 - - ns

CCLK“n” to CSN“n” tCSH50 - - ns

CDTO DelaytDCD - - 50 ns

CSN“n” toCDTO Hi-Z tCCZ- - 70 ns

Control Interface Timing(I2C Bus mode):

SCL Clock FrequencyfSCL - - 100 kHz

Bus Free TimeBetween Transmissions tBUF 4.7 - - Ps

StartCondition HoldTime(prior tofirst clock pulse) tHD:STA4.0 - - Ps

Clock Low Time tLOW 4.7 - - Ps

Clock High TimetHIGH 4.0 - - Ps

Setup Timefor Repeated Start Condition tSU:STA4.7 - - Ps

SDA Hold Timefrom SCL Falling (Note 29) tHD:DAT0 - - Ps

SDA Setup Timefrom SCL Rising tSU:DAT 0.25 - - Ps

Rise Timeof Both SDA and SCL Lines tR- - 1.0 Ps

Fall Timeof BothSDA and SCL Lines tF - - 0.3 Ps

Setup Timefor Stop Condition tSU:STO4.0 - - Ps

Pulse Widthof SpikeNoise Suppressed by Input Filter tSP 0 - 50 ns

Reset Timing

PDN PulseWidth(Note 30) tPD 150 - - ns

PMADL or PMADR “n” to SDTO valid(Note 31) tPDV - 2081 - 1/fs

Note29. Datamust be heldlong enough tobridge the 300ns-transition timeof SCL.

Note30. The AK4537 can be reset by the PDN pin = “L”.

Note 31. This is the countof LRCK“n” from the PMADL or PMADR bit= “1”.

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Timing Diagram

1/fCLK

MCLK

tCLKHtCLKL

VIH

VIL

1/fs

LRCKVIH

VIL

tBCK

BICK

tBCKHtBCKL

VIH

VIL

MCKO

dMCKdMCK

50%DVDD

fMCK

Figure 3. Clock Timing

MCKI Input MeasurementPoint

A

GND

tACWtACW

A

GND

1/fCLK

1000pF

100k

:

VAC

Figure 4. MCKI ACCoupling Timing

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LRCK VIH

VIL

tBLR

BICK VIH

VIL

tLRS

SDTO 50%DVDD

tLRB

tBSD

tSDS

SDTI VIL

tSDH

VIH

Figure 5. Audio Interface Timing (Slave mode)

LRCK VIH

VIL

BICK 50%DVDD

SDTO 50%DVDD

tBSD

tSDS

SDTI VIL

tSDH

VIH

tMBLR dBCK

Figure 6. Audio Interface Timing (Master mode)

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CSN VIH

VIL

tCSS

CCLK

tCDS

VIH

VIL

CDTI VIH

tCCKHtCCKL

tCDH

VIL

C1 C0 R/W

CDTO Hi-Z

Figure 7. WRITE/READ Command Input Timing

CSN VIH

VIL

tCSH

CCLK VIH

VIL

CDTI VIH

tCSW

VIL

D1 D0

CDTO Hi-Z

D2

Figure 8. WRITE DataInput Timing

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CSN VIH

VIL

CCLK VIH

VIL

CDTI VIH

VIL

A0

CDTO

A1

50%DVDD

tDCD

D7 D6

Hi-Z

Figure 9. READ DataOutputTiming 1

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CSN VIH

VIL

tCSH

CCLK VIH

VIL

CDTI VIH

tCSW

VIL

CDTO 50%DVDDD2 D1 D0

tCCZ

Hi-Z

Figure 10. READ Data Output Timing 2

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StopStartStartStop

tHIGH

tHD:DAT

SDA

SCL

tBUF tLOW tR tF

tSU:DAT

VIH

VIL

tHD:STA tSU:STA

VIH

VIL

tSU:STO

tSP

Figure 11. I2C Bus Mode Timing

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CSN VIH

VIL

tPDV

SDTO

tPD

50%DVDD

PDN VIL

Figure 12. Power Down & Reset Timing

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OPERATION OVERVIEW

Master Clock Source

The AK4537 requires a masterclock (MCLK). This master clock is input tothe AK4537 by connecting a X’taloscillator

toXTI and XTO pins or by inputting an external CMOS-levelclock to the XTI pin or by inputting anexternal clock that

isgreater than 50% of the DVDD level tothe XTI pin through a capacitor.

Whenusing a X’tal oscillator, there shouldbe capacitors between XTI/XTO pins and DVSS. When using an external

clock, there are two choices: direct, where anexternal clock isinput directlytothe XTI pin and indirect, where the

external clock isinput through a capacitor.

Master Clock Status PMXTL bitMCKPD bit

X’talOscillator (Figure 13) Oscillator ON 1 0

Oscillator OFF 0 1

External Clock Direct Input (Figure 14) Clock isinput to MCKI pin. 0 0

MCKIpin is fixed to“L”. 0 0/1

MCKI pin isfixed to“H”. 0 0

MCKI pin isHi-Z 0 1

ACCoupling Input (Figure 15) Clock isinput to MCKI pin. 1 0

Clock isn’t input toMCKI pin. 0 1

Table 1. MasterClock Status by PMXTL bit and MCKPD bit

(1)X’tal Oscillator

XTI

XTOAK4537

25k:

MCKPD = "0"

PMXTL= "1"

C

Figure 13. X’talmode

Note: The capacitorvaluesdepend ontheX’tal oscillatorused.(C: typ. 10 a30pF)

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(2) ExternalClock Direct Input

XTI

XTOAK4537

25k:

MCKPD= "0"

PMXTL= "0"

External

Clock

Figure 14. ExternalClock mode (Input : CMOSLevel)

Note:Thisclock level must not exceed DVDD level.

(3) AC Coupling Input

XTI

XTOAK4537

25k:

MCKPD= "0"

PMXTL= "1"

External

Clock

C

Figure 15. ExternalClock mode (Input :t50%DVDD)

Note: This clock level must not exceedDVDD level. (C: 0.1PF)

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AKM AK4537 User manual

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