Alinco DJ-G1T User manual

DJ-G1T/E
Service Manual
CONTENTS
• SPECIFICATIONS
1) General...................................................................2
2) Transmi er
.............................................................2
3) Receiver..................................................................2
• CIRCUIT DESCRIPTION
1) Receiver Sys em.............................................3 _ 5
2) Transmi er Sys em ........................................ 5 ,6
3) PLL Circui ...............................................................6
4) VCO Circui .......................................................6 - 7
5) DTMF Circui ...........................................................7
6) Tone Squelch Circui ..............................................7
7) Terminal Func ion of Microprocessor ......... 8-10
8) Terminal Func ion of IC302 .................................11
9) Terminal Func ion of IC303.................................12
• SEMICONDUCTOR DATA
1) BU4094..................................................................13
2) CM8870CFIT.........................................................14
3) M5218FP............................................................... 15
4) M5237ML.............................................................. 15
5) M67748L............................................................... 16
6) MB 1505................................................................ 16
7) MX265.................................................................. 17
8) MJM386................................................................ .18
9) RN5VL45C............................................................18
10) X24C08S14-3.0T.................................................18
11) TK10930VTL.........................................................19
12)Transis or, Diode and LED Ou line Drawings...20
13) . LCD Connec ion..........................................21 -22
• EXPLODED VIEW
1) Fron View 1..........................................................23
2) Fron View 2.........................................................24
3) Rear View ............................................................25
4) Charge Uni ..........................................................26
5) LCD......................................................................27
• PARTS LIST
RF Uni ..........................................................28-30
IF Uni ............................................................31 - 33
CPU Uni ........................................................33 - 34
VCO Uni ...............................................................35
Charge Uni ...........................................................35
Key Uni ..................................................................36
PTT Uni ................................................................36
TSQ Uni ................................................................ 36
Mechanical Par s..................................................37
Packing.................................................................. 37
• ADJUSTMENT
1) DJ-G1T Adjus men .............................................38
2) DJ-G1E Adjus men .............................................39
3) Adjus men Poin s................................................40
• PC BOARD VIEW
1) RF Uni Side A......................................................41
2) RF Uni Side B......................................................42
3) IF Uni Side A........................................................43
4) IF Uni Side B........................................................44
5) CPU Uni Side A................................................... 45
6) CPU Uni Side B................................................... 46
7) VCO Uni ...............................................................47
8) KEY Uni ................................................................ 48
9) Charge Uni ...........................................................48
10) PTT Uni ................................................................ 48
• CIRCUIT DIAGRAM
1) RF Uni ...................................................................49
2) IF Uni ....................................................................50
3) CPU Uni ................................................................51
4) KEY Uni ...............................................................52
5) Charge Uni ......................................................... 52
6) CTCSS Uni .........................................................52
• BLOCK DIAGRAM...........................................................53
E ALINCO ELECTRONICS INC

SPECIFICATIONS
1) General
Frequency Coverage:
Modula ion:
An enna Impedance:
An enna Connec or:
Power Supply Vol age:
TX Curren @7.2VDC HI/MID/LOW:
©13.8VDC HI:
RX Curren @AF 200mW 8ÎÎ:
Squelched:
Ba ery Save Mode:
Frequency S abili y:
Dimensions W x H x D:
Weigh :
2) Transmi er
Ou pu Power HI:
MID:
LOW:
Modula ion:
Max. Devia ion:
Spurious Emission:
Microphone Impedance:
3) Receiver
Receiving Sys em:
IF1s /2nd:
Sensi ivi y (12dB SINAD):
Selec ivi y -6dB:
-60dB
Spurious Ra io:
Audio Ou pu (@10% dis or ion):
RX: 108.000- 173.995MHz (T version)
RX:440.000 ~ 449.995MHz (T version)
TX:144.000 - 147.995MHz (T version)
RX:144.000 - 145.995MHz (E version)
RX:430.000 - 439.995MHz (E version)
TX:144.000 - 145.995MHz (E version)
F3E
A3 (receive only)
50£2
BNC
7.2-12.0V DC max.13.8VDC
approx. i 0A/0.8A/0.4A
approx. 1.6A
approx. 120mA
approx. 55mA
approx. 25mA ave.
5p.p.m.
50mm x 116mm x 37mm
360gr.
approx. 5W (13.8VDC) 1.5W (7.2V)
approx. 1W
approx. 0.2W
Variable Reac ance
+/ -5kHz
no more han -60dB
2kQ
Double Conv. Super-He erodyne
30.85MHz/455kHz
TX Band Cen er max. -16dBp.
RX Subband Cen er (abou 440MHz) max. -10dB(i
no less han 12kHz
no more han 30kHz
no more han -60dB
min. 200mW 8ii
2

CIRCUIT DESCRIPTION
1 ) Receiver Sys em
1. Fron End
The receiver sys em is he double superhe erodyne.
The firs IF is 30.85MHz and he second IF is 455kHz.
108.00MHz~ 173.995MHz.
The receive signal is passed hrough a low-pass fil er (L1, L2, L4, C3, C4,
C5 and C7), resona or circui (L12, varicap D7 and D8), and inpu o he RF
amplifier (Q6). The signal from Q6 is passed hrough resona or circui (L13,
varicap D10 and D11), resona or circui (L15, varicap D13, D14), led o he
firs mixer Q8 and he signal is conver ed ino he 30.85MHz. The resona or
circui (L12, L13, L15, varicap D7, D8, D10, D11, D13 and D14) is con rolled
by P/D vol age. The bandwid h charac eris ics is ob ained he frequency of
108.00MHz~173.995MHz. The diodes (D9, D12, D15 and D22) are ON a
108.00MHz~ 139.995MHz, and hey are OFF a 144.00MHz~173.995MHz.
Local oscilla or signal from VCO is injec ed o he base of mixer (Q8). The
radio uses he upper side superhe erodyne.
420.00MHz~ 479.995MHz
The receive signal is passed hrough a high-pass fil er (L10, L11, C31, C32
and C33), band swi ch (D16B), rap circui (L18, C57, C58 and C59) and
inpu o he RF amplifier (Q12). The signal from Q12 is passed hrough
resona or circui s (L19 and C60), (L20, C64 and C65), led o he firs mixer
Q13 and he signal conver ed in o 30.85MHz. Local oscilla or signal is
passed hrough he buffer amplifier (Q17), and injec ed o he base of mixer
(Q13). The radio uses he upper side superhe erodyne a 420.00MHz~
429.995MHz, and uses he lower side superhe erodyne a 430.00MHz-
479.995MHz.
2. IF Circui
3. Demodula or Circui
800.00MHz-999.99MHz (DJ-G1E only)
The receive signal is passed hrough a high-pass fil er (L10, L11, C31, C32
and C33), (prin ed coil, C67 and C69) and inpu o he RF amplifier (Q14).
The signal from Q14 is led o he firs mixer Q15 and he signal conver ed
ino he 30.85MHz. Local oscilla or signal is inpu o he doubler amplifier
(Q16), and injec ed o he base of mixer (Q15). The radio uses he lower
side superhe erodyne.
The receive signal is mixed wi h he local signal in he mixer o gain he
difference frequency of 30.85MHz. The unwan ed frequency band of he
firs IF signal is elimina ed by he monoli hic crys al fil er (FL302), and led o
IF amplifier Q301.
FM and AM demodula ors are buil in he IC301(TK 10930). The AM circui
becomes ac ive when Pin 14 of IC301 goes low.
The IF signal is amplified by he firs IF amplifier of Q301, and inpu o Pin24
of IC301, where i is mixed wi h he second local oscilla or signal
(30.395MHz, X303) and so is conver ed in o he second IF signal (455kHz).

The 455kHz second IF signal is ou pu from Pin3 of IC301, and unwan ed
frequency band of he second IF signal is elimina ed by a ceramic fil er
(FL301). The resul ing signal is led o he Pin5 and 7 of IC301.
4. Audio Circui
5. Squelch Circui
Demo ulator of FM
The second IF signal of Pin7 of IC301 is led o he in ernal limi er amplifier,
quadra ure de ec ion circui . The audio signal is ou pu from Pin 12 of IC301.
Demo ulator of AM
The second IF signal of Pin5 of IC301 is led o he in ernal AM amplifier, AM
de ec ion circui . The audio signal is ou pu from Pin 13 of IC301.
The AGC circui is used o ob ain a s able audio ou pu level even if he inpu
level is changed. The forward AGC signal is ou pu from Pin 18 of IC301,
and inpu o he AGC amplifier (Q326). The gain of he firs IF amplifier is
con rolled by he AGC signal.
FM Mo e
The audio signal from Pin12 of IC301, which is pre-emphasized on ransmi 
ing, is led o he emphasis circui (R334 and C338) and compensa ed for
he audio frequency charac eris ics. The audio signal is amplified by AF
amplifier (Q306), led o he audio H.P.F. (Q310, C346, C347 and R346).
The audio signal is inpu o he volume (VR311), and inpu o he power
amplifier Pin3 of IC305, and ou pu from Pin6 o drive he speaker.
AM Mo e
When you selec he AM mode, swi ching ransis ors Q324, Q308 and Q309
become ON, and hen Pin14 of IC301 goes o Low (AM de ec ion circui is
ac ive), Q307 is ac ive and Q306 is no ac ive. The audio signal from Pin13
of IC301 is amplified by AF preamplifier (Q307), led o he audio H.P.F.
(Q310, C346, C347 and R346), as well as in he FM mode, hen inpu o he
volume (VR311) and he power amplifier o drive he speaker.
Note
The IC301 (TK10930) of he FM de ec ion circui is ac ive even in he AM
mode, FM de ec or circui is ac ive. Q306 connec s he base of he FM
audio preamplifier Q309 o he ground so ha he FM audio signal by he FM
de ec ion is cu .
The noise in he audio signal from Pin 12 of de ec ion IC, IC301 is passed
hrough he squelch con rol variable resis or (VR311) and inpu o he noise
fil er amplifier consis ing of C323, C322, C325, R317 and R316, in ernal
noise amplifier IC301. The desired noise of he audio signal is ou pu from
Pin20 of IC301 and so amplified by noise amplifier (Q305). The amplified
noise signal is rec ified by D302 and hen inpu o Pin21 of IC301. When he
vol age of Pin21 is above 0.7V, Pin22 of IC301 goes o "low" (squelch circui
is ac ive). When he vol age of Pin21 is below 0.7V, Pin22 of IC301 goes o

6. Audio Power
Amplifier Circui
7. Signal Me er
Circui
2) Transmi er Sys em
1. Microphone Amplifier
Modula or Circui
"High" (squelch circui does no work). This signal "SD" is led o he CPU
Pin of IC401, and hen processed by CPU. When he squelch circui is
ac ive, Q311 and Q304 are off. When he squelch circui does no work,
Q311 and Q304 are on. In his way he audio ou pu signal is con rolled.
When he squelch circui does no work, Q323 goes on, he squelch indica or
LED (D303B) ligh urns on. When he squelch circui is ac ive, Q323 goes
off, he squelch indica or LED (D303B) ligh urns off.
When he power supply vol age of radio becomes above 6.3V in he vol age
s abilizer circui (Q302, Q303, D301 and D304). The power supply vol age of
audio power amplifier IC (IC305) is con rolled below 6.3V.
The vol age of audio power amplifier IC (IC305) is con rolled by he Q304.
The Q304 is ON when he squelch is OFF, BEEP sound is ou pu ing, and
DTMF moni or (TX) is ON, hen IC305 works.
The IC301 has S me er func ion. When he signal s reng h is low, vol age of
Pin 16 becomes lower, and when he signal s reng h is high, vol age of Pin
16 becomes higher. The S me er vol age of Pin 16 is led o he variable
resis or (VR310) and inpu o he Pin of IC401 (CPU). I is conver ed by A/D
conver er buil -in CPU, and S is appeared in he LCD.
2. Power Amplifier
Circui
3. APC Circui
Af er he voice is conver ed in o he elec ric signal hrough he in ernal or
ex ernal microphone, he signal is led o he microphone amplifier IC304.
IC304 consis s of wo opera ional amplifiers. One opera ional amplifier (Pin5,
6 and 7) uses pre-emphasis circui and IDC circui , and he o her opera ional
amplifier (Pin1, 2 and 3) uses spla er fil er. The ou pu from he microphone
amplifier is passed hrough variable resis ors VR305 for maximum devia ion
adjus men o ca hode of varicap (D206) diode of he VCO, con rolling he
VCO frequency and so producing a frequency-modula ion.
The signal from VCO is amplified by RF amplifier Q4 and drives amplifier
Q3, and inpu o he power module Pin 1 of IC1. The signal is amplified by
power module IC1, and ou pu from Pin5 of IC1, and hen led o he low-
pass fil er (L6, C15, C16), he an enna swi ch circui D1 and he low-pass
fil er (L1, L2, C3, C4 and C5). The unwan ed harmonics frequency signal is
elimina ed by he low-pass fil er and inpu o he an enna.
Par of he ransmission power is passed hrough he C17, C11 and de ec ed
by D3. The de ec ed DC vol age is amplified by Q2 and drives he Q1. This
vol age is con rolled by he bias vol age of Pin3 of IC1 and collec or vol age
of RF amplifier Q3 o s abilize he ransmission power. When he ransmis
sion power goes higher han he se led power, de ec ed vol age by D3 goes
higher, collec or vol age of Q1 goes o low. When he ransmission power
goes lower han he se led power, de ec ed vol age by D3 goes lower,
collec or vol age of Q1 goes o high. The high power se ing variable resis or

VR308 and he middle power se ing variable resis or VR307 loca ed in he
IF uni . The radio has no low power se ing variable resis or.
3) PLL Circui
1. Reference Freq.
Circui
2. Phase Compara or
Circui
3. Loop Fil er Circui
4) VCO Circui
Power High Middle Low
D306A OFF ON OFF
D306B ON OFF OFF
The PLL serial da a (clock, da a, s robe) is sen from CPU IC401. The Pin9
of IC2 is clock, Pin10 of IC2 is da a, Pin 11 of IC2 is s robe. The VCO signal
is amplified by RF amplifier Q19, and inpu o he Pin8 of IC2. The program
mable divider of IC2 is de ermined by frequency da a, and i divides (1/N)
inpu signal of IC2. Resul ing signal will be 5kHz or 6.25kHz.
There are 8 channel s eps (5, 10, 12.5, 15, 20, 25, 30 and 50kHz) of DJ-
G1T/E. The reference frequency is ob ained by divided by 2560 or 2048
reference oscilla or (12.8MHz). The reference frequency (5kHz) uses a
channel s ep of 5, 10, 15, 20, 25, 30 and 50kHz. The reference frequency
(6.25kHz) uses a channel s ep of 12.5kHz.
The reference frequency of he IC2 is 5kHz or 6.25kHz.
The VCO ou pu frequency divided by N is compared wi h 5kHz or 6.25kHz
in he phase compara or.
If he phase error should occur in PLL, he charge pump (Pin5 of IC2)
ou pu s he pulse. This signal is conver ed in o DC vol age by PLL loop fil er
(C84, C85, C86, R70, R71, R72 and R73), and inpu o he varicap diode
(D202, D203, D204 and D205) in he VCO uni for he frequency con rol.
The frequency con rol vol age from he PLL circui is inpu o he ca hode of
he varicap diode D202 (VC01), D203 (VC01), D204 (VC02) and D205
(VC02).
The ou pu frequency of VCO is amplified by RF amplifier Q203, and ou pu
from VCO uni . The circui is Colpi s oscilla or. To ge he wide band receive
range, he radio has wo VCO's. To ge he wide oscilla ion frequency range,
he fixed capaci ance in he VCO is se o he smalles value.
Oscilla or Tune Varicap Modula ion
Varicap Shif
Swi ch
VC01 Q201 D202, D203 D206 D201
VC02 Q202 D204, D205

Each of he oscilla ion frequency of VC01 and VC02 is as follows.
5) DTMF Circui
1. Encoder Circui
2. Decoder Circui
6) Tone Squelch
Circui
1. Encoder Circui
2. Decoder Circui
Oscilla ion Frequency Tune Varicap
VC01
(TTX)
(E TX)
138.85MHz~170.845MHz 108.00MHz~ 139.995MHz
170.85MHz~204.845MHz 140.00MHz~173.995MHz
134.575MHz~169.57MHz
144.00MHZ-147.995MHz
144.00MHz-145.995MHz
VC02
(E)
450.85MHz~460.845MHz 420.00MHz~429.995MHz
399.15MHz~419.145MHz 430.00MHz~449.995MHz
419.15MHZ-449.145MHz 450.00MHz~479.995MHz
384.575MHz~484.57MHz 800.00MHz~999.99M Hz
The CPU has he DTMF encoder. The column signal is ou pu from Pin98,
and he row signal is ou pu from Pin99. The DTMF signal is de ermined
corresponding o he combina ion of he column and row. DTMF signal is
passed hrough variable resis or for modula ion adjus men , and inpu o he
modula ion erminal of VCO uni via he spla er fil er.
The de ec ed signal from IC301 is inpu o he DTMF decoder Pin2 of IC402.
When he one squelch decoder decodes he inpu one signal frequency as
he programmed frequency, he decoded da a is ou pu from Pinll, 12, 13
and 14 processed in he CPU IC401.
The 4-bi digi al codes are ou pu from Pin 34, 35, 36 and 37 of CPU and
conver ed ino he mimic sign wave wi h he R437 and R440. The sign wave
is inpu o he low-pass fil er (R435, R436 and C419), AF amp Q313, and via
he ac ive low-pass fil er (Q314, R359, R360, R363 and C364), inpu o he
modula ion erminal of VCO uni . 39 selec able one frequency waves are
provided.
The one decoder uni EJ-16u is op ion. The de ec ed signal from Pin 12 of
IC301 is inpu o he Pin15of IC701 in he EJ-16uvia CN302. When he one
squelch decoder decodes he inpu one signal frequency as he pro
grammed frequency, "high" signal is ou pu from Pin9. When he one
squelch decoder does no decode he inpu one signal frequency as he
programmed frequency, "low" signal is ou pu from Pin9, and i is inpu o he
CPU. Consequen ly he audio signal is con rolled by CPU.

7) Terminal Func ion of Microprocessor
No. Pin Name Signal Name I/O Descrip ion H L Remarks
01 AVcc Vdd /AD Conver er Power Supply Terminal
02 AN0 BP1 A/D
03 AN1 MRC A/D Microphone Remo e Con rol Inpu
04 AN2 +BD A/D Power Supply Vol age De ec ion
05 AN3 SMT A/D S-Me er Inpu
06 AVss GND / AD Conver er Ground
07 TEST Vdd IConnec o Vdd
08 OSC1 Xin IMCU In ernal Clock Inpu
09 OSC2 Xou O MCI) In ernal Clock Ou pu
10 RESET RST IMCU Rese Inpu
11 X1 Vdd IConnec o Vdd
12 X2 NC O Open
13 GND GND / Ground Terminal
14 DO FUNC I Func ion Key Inpu
15 D1 MONI I Moni or Key Inpu
16 D2 PT5 PTT1 I PTT Swi ch Inpu
17 D3 PTT2 I TX Low Power Inpu
18 D4 M.MUTE 0 Microphone Mu e
19 D5 LAM PC 0Lamp ON/OFF
20 D6 SDA I/O Da a for EEPROM
21 D7 SCL 0 Clock for EEPROM
22 D8 STB1 0S robe for PLL IC
23 D9 STB2 TICD I/O CTCSS Uni De ec ion and S robe
24 DIO/STOPC TSQD I CTCSS Tone De ec ion Inpu
25 D11/INT0 Bu I Back Up Signal De ec ion Inpu
26 R00/INT1 SD I SD Signal Inpu
27 R01/INT2 R01 I Ro ary Encoder Up Inpu
28 R02/INT3 R02 I Ro ary Encoder Down Inpu
29 R03/INT4 DSlD I DTMF Signal De ec ion Inpu
30 RIO/TOB BEEP 0Beep Tone Ou pu
31 R11/TOC 1750 0Tone Burs (1750Hz) Ou pu
32 R12/TOD DPD oDTMF ON/OFF

No. Pin Name Signal Name I/O Descrip ion H L Remarks
33 R13/EVNB DTOE 0DTMF Signal Inpu
34 R20/EVND TONEO 0Sub Tone Signal Ou pu
35 R21/SCK TONE1 0Sub Tone Signal Ou pu
36 R22/SI TONE2 0Sub Tone Signal Ou pu
37 R23/SO TONE3 0Sub Tone Signal Ou pu
38 R30/SEG1 DQ1 BP2 I DTMF 4-Bi Da a Inpu
39 R31/SEG2 DQ2 BP3 IDTMF 4-Bi Da a Inpu
40 R32/SEG3 DQ3 BP4 IDTMF 4-Bi Da a Inpu
41 R33/SEG4 DQ4 BP5 IDTMF 4-Bi Da a Inpu
42 R40/SEG5 KIN0 I Key Ma rix Inpu l
43 R41/SEG6 KIN1 I Key Ma rix Inpu 2
44 R42/SEG7 KIN2 IKey Ma rix Inpu 3
45 R43/SEG8 KIN3 I Key Ma rix Inpu 4
46 R50/SEG9 KOUTO oKey Ma rix Ou pu l
47 R51/SEG10 KOÜT1 oKey Ma rix Ou pu 2
48 R52/SEG11 KOUT2 oKey Ma rix Ou pu 3
49 R53/SEG12 KOUT3 oKey Ma rix Ou pu 4
50 R60/SEG13 KOÜT4 oKey Ma rix Ou pu 5
51 R61/SEG14 CLK oClock Signal
52 R62/SEG15 DATA 0 Da a Signal
53 R63/SEG16 STB3 oS robe for 4094
54 R70/SEG17 SEGO oLCD SEGO
55 R71/SEG18 SEG1 oLCD SEG1
56 R72/SEG19 SEG2 oLCD SEG2
57 R73/SEG20 SEG3 oLCD SEG3
58 SEG21 SEG4 oLCD SEG4
59 SEG22 SEG5 0 LCD SEG5
60 SEG23 SEG6 oLCD SEG6
61 SEG24 SEG7 oLCD SEG7
62 SEG25 SEG8 oLCD SEG8
63 SEG26 SEG9 0LCD SEG9
64 SEG27 SEG10 0 LCD SEG10
65 SEG28 SEG11 oLCD SEG11
66 SEG29 SEG12 oLCD SEG12

No. Pin Name Signal Name I/O Descrip ion H LRemarks
67 SEG30 SEG13 OLCD SEG13
68 SEG31 SEG14 OLCD SEG14
69 SEG32 SEG15 0LCD SEG15
70 SEG33 SEG16 0LCD SEG16
71 SEG34 SEG17 0LCD SEG17
72 SEG35 SEG18 0LCD SEG18
73 SEG36 SEG19 0LCD SEG19
74 SEG37 SEG20 0LCD SEG20
75 SEG38 SEG21 0LCD SEG21
76 SEG39 SEG22 0LCD SEG22
77 SEG40 SEG23 oLCD SEG23
78 SEG41 SEG24 0LCD SEG24
79 SEG42 SEG25 0LCD SEG25
80 SEG43 SEG26 0LCD SEG26
81 SEG44 SEG27 0LCD SEG27
82 SEG45 SEG28 0LCD SEG28
83 SEG46 SEG29 oLCD SEG29
84 SEG47 SEG30 0LCD SEG30
85 SEG48 SEG31 0LCD SEG31
86 SEG49 SEG32 0LCD SEG32
87 SEG50 SEG33 0LCD SEG33
88 SEG51 SEG34 0LCD SEG34
89 SEG52 SEG35 0LCD SEG35
90 COM1 COMO 0LCD COMO
91 COM2 COM1 oLCD COM1
92 COM3 COM2 0LCD COM2
93 COM4 NC 0
94 V1 VL1 / LCD Power S pply
95 V2 VL2 /LCD Power S pply
96 V3 VL3 /LCD Power S pply
97 Vcc Vdd /Power S pply
98 TON EC DTONC 0Col mn O tp t for DTMF Signal
99 TONER DTONR 0Row O tp t for DTMF Signal
100 VTref Vdd IReference Power S pply for DTMF O tp t
10

8) Terminal Func ion of IC302
BU4094BF-T1
No. Pin Name Signal Name I/O Descrip ion H L Remarks
01 STROBE STB3 I
02 DATA DATA I
03 CLOCK CK I
04 Q1 AFPC OPower S pply Control for AF Power Amp. ON
05 Q2 R5C O Power S pply Control for RX 5V ON
06 Q3 AFS 0AF Switch ON
07 Q4 AM 0AM Switch ON
08 Vss GND
09 Qs
10 Os’ IC303 (2)
11 Q3 T5C 0Power S pply Control for TX 5V ON
12 Q7 SUBC 0 Power S pply Control for S b Band ON
13 Q6 360C 0Power S pply Control for 360 Band ON
14 Q5 870C 0 Power S pply Control for 870 Band ON
15 OUTPUT C5V
16 Vdd C5V
11

9) Terminal Func ion of IC303
BU4094BF-T1
No. Pin Name Signal Name I/O Descrip ion H L Remarks
01 STROBE STB3 I
02 DATA DATA I IC302 (10)
03 CLOCK CK I
04 Q1 MAINC O Power S pply Control for Main Band ON
05 Q2 VC02C O Power S pply Control (or VHF VCO ON
06 Q3 VC01C O Power S pply Control for UHF VCO ON
07 Q4 SWC O VHF VCO Shift ON/OFF ON
08 Vss GND
09 Qs
10 Os'
11 Q8 O
12 Q7 P5C OPower S pply ON/OFF of VCO and PLL ON
13 Q6 MID O TX Middle Power Control ON
14 Q5 HI 0TX High Power Control ON
15 OUTPUT C5V
16 Vdd C5V
Power Con rol Table

SEMICONDUCTOR DATA
1) BU4094 (XA0246)
8-Stage Shift Register
STROBE HZ 1w16 =l Vdd
DATA \zz 215 z□Ou pu Enable
CLOCK cz 300 14 Z J Q5
Q1 cz 4c13 ZD Q6
Q2 ÜZ 5
O
CO
-U 12 ZZ1 Q7
Q3 r z 603
n11 zz Q8
04 cz 710 Q's
Vss n z 89Qs
Func ion Table
Clock Ou pu
enable S robe Da a
Parallel ou pu s Serial ou pu s
Q 1 Qn Qs Q's
s ~ L X XZ Z Q7 No Chg.
L X XZZNo Chg. Qs
HL X No Chg. No Chg. 07 No Chg.
H H LLQn-l Q7 No Chg.
HH H HQn-1 Q7 No Chg.
!k - H X X No Chg. No Chg. No Chg. Qs
Z=High Impedance
X=Don' Care
Block Diagram
Q1 PARALLEL Q8
OUTPUT

2) CM8870CFIT (XA0231)
CTCSS Encoder/Decoder
IN+ CJ 118 ZD Vdd
IN- cz 217 =3 S /G
GS c z 3 16 ZD ES
Vref cz 4o
215 IZ) S D
INH cz=500 CO 14 ZZ 04
PD cz: 6o
O13 ZZl 03
OSC1 zz 712 ZZI Q2
OSC2 a811 ZD Q1
Vss cz 910 bn TOE
Func ion Table
Name Descrip ion
IN+ Inver ing Inpu
IN- Noninver ing Inpu
GS Gain Selec ion
Vref Reference Vol age Ou pu
INH
PD Power Down Con rol
OSC1 Clock Inpu
OSC2 Clock Ou pu
Vss Nega ive Power Supply
TOE Three S a e Ou pu Enable
Q1
Q2
Q3 Three S a e Ou pu (RX Da a Ou pu )
Q4
S D Delay S eering Ou pu
ES Firs S eering Ou pu
S /GT S eering Inpu /Guard Time Ou pu
Vdd Posi ive Power Supply
Decode Table
F low F high Key TOE Q4 Q3 02 Q1
697 1209 1H 0 0 0 1
697 1336 2H001 0
697 1477 3H0011
770 1209 4 H 0 10 0
770 1336 5 H 0 1 0 1
770 1477 6H. 0110
852 1209 7 H 0 111
852 1336 8 H 1 0 00
852 1477 9H 1 0 0 1
641 1336 0 H 1010
941 1209 H1011
941 1477 # H 1 1 0 0
697 1633 A H 110 1
770 1633 B H 1 1 10
852 1633 C H 1 1 1 1
941 1633 DH0 0 0 0
-ANY Lzzzz
L: Logic Low, H: Logic High, Z=High Impedance.

3) M5218FP (XA0068)
D al Low Noise
Operational Amplifiers
Ou pu 1 1 I
Inver ing Inpu 1 2 [
Noninver ing Inpu 1 3 [
Power Supply Minus 4 I
I e Power Supply Plus
| 7 Ou pu 2
| 6 Inver ing Inpu 2
I 5 Noninver ing Inpu 2
4) M5237ML (XA0217)
Voltage Reg lator
Tes Circui
Vi Vo
M5237ML

5) M67748L (XA0148)
135~150MHz 7W RF Power Mod le
6) MB1505 (XA0240)
PLL Freq ency Synthsizer
OSCin CZZ 1W16 zn aR
OSCou IZZ 215 ZD oP
Vp cz 314 zn (ou
Vcc czz 42
GO 13 z□BiSW
Do czz 5
_l
cn
o12 ZD FC
GND CZZ 6cn 11 LE
LD c z 710 ZZ3 Da a
fin czz 89= □ Clock
Func ion Table
No. Name I/O Func ion
1OSCin I Reference oscilla or inpu erminal
2OSCou oReference oscilla or ou pu erminal
3 Vp -Charge pump ou pu erminal
4Vcc -Power supply erminal
5Do 0 In ernal charge pump ou pu erminal
6GND -Ground erminal
7LD oPhase de ec or ou pu erminal Locked: H
8 fin IPrescaler inpu erminal
9Clock I Clock inpu erminal
10 Da a I Serial da a inpu erminal
11 LE ILoad enable signal inpu erminal
12 FC I Phase swi ch inpu erminal
13 BiSW 0 Analogue swi ch ou pu erminal
14 ou oPhase de ec or inpu moni or erminal H: (r, L: fp
15 0P oPhase de ec or ou pu erminal for ex ernal charge pump
16 oR oPhase de ec or ou pu erminal for ex ernal charge pump
16
Fin(Gro nd)

7) MX265 (XA0241 )
CTCSS Encoder/Decoder
MX265DW
6Bp
a <5
'p L iZ l
J T
XTAL/CLOCK Vdd
XTAL TONE IN
LOAD/LATCH BIAS
SERIAL ENABLE RttTX
SERIAL DATA TONE OUT
SERIAL CLOCK RX DETECT
NC DECODE COMP. IN
VSS RX DECODE
0.1MF
HI—
O.IijF
-«—II ----
O.lnF
----- II ---
0.1MF
560K
-vw—
- 4 - » -
X°.,mf
X al/Clock: Inp t to the on-chip inverter sed with a
1 MHz Xtal or external clock so rce.
X al: O tp t of the on-chip inverter (clock o tp t).
Decode Compara or Inpu : This is the inverting inp t
of the decode comparator. This pin is normally
connected to the integrated o tp t of the RX Tone
Detect line.
Load/La ch: Controls 8 on-chip latches and is sed to
latch RX/TX, PTL, and D0-D5. This pin is internally
p lled to Vdd. A logic "1" applied to this inp t p ts the 8
latches in "transparent" mode. A logic “0" applied to this
inp t p ts the 8 latches in the "latched" mode. Data is
loaded and latched by a 0-1 -0 strobe p lse on this pin.
Serial Enable: A logic "0" applied to this inp t will
enable serial programming. This pin is internally p lled
to Vdd.
Serial Data Inp t: This is the serial data inp t. Data is
loaded in the following order: D5, D4, D3, D2, D1, DO,
RX/TX and PTL. This pin is internally p lled to Vdd.
Serial Clock Inp t: Data is clocked on the positive
going edge. This pin is internally p lled to Vdd.
Rx Tone De ec : In Rx mode this pin will go to logic "1"
d ring a s ccessf l decode. It m st be externally
integrated to control response and deresponse times.
Tx Tone Ou : The CTCSS sinewave o tp t appears on
this pin nder the control of the RX/TX pin. This pin,
when not transmitting a tone, may be biased to Vdd -
0.7V or O/C.
Rx/Tx: This inp t selects Rx or Tx modes . This
f nction may be selected by this pin, or It may be serially
loaded. This pin is internally p lled to Vdd via a 1 MC2
resistor.
Bias: This pin is the o tp t of an internally generated
Vdd/2 bias level and wo ld normally be externally
deco pled to Vss via capacitor C6.
Vss: Negative s pply.
RX Tone Decode Ou : This is the gated o tp t of the
decode comparator. This o tp t is sed to gate the RX
A dio path. A logic "0" on this pin indicates a s ccessf l
decode and that the Decode Comparator Inp t pin is
more positive than the Decode Comparator Ref. inp t.
Tone Inpu : This is the inp t to the CTCSS tone
detector. It is internally biased to Vdd/2.
Vdd: Positive S pply.

8) NJM386 (XA0061)
Power Amplifiers
V+=9V RL=16fi Po=500mW
z
Gain di8
-Inpu n z 2c_
5
7
+ npu n z 3W
00
CT>
6
GND c = 45
Gain
Bypass
Vs
Vou
9) RN5VL45C (XA0232)
Voltage Detector
Equivalen Circui
10) X24C08S14-3.0T (XA0226)
EEPROM 256 x 8Bi
NC IZ Z 1w14 Z Z NC
AO d 213 ZZ1 Vcc
A1 [ZZ 3X12 IZ I TEST
NC C Z 4ro
«h
o11 Z Z I NC
A2 C Z 5o
00 10 Z Z SCL
Vss IZ Z 6 9 I Z I SDA
NC C Z 7 8 Z Z I NC
Ou Vdd Vss
Pin Names
Symbol Descrip ion
A0-A2 Adress Inpu s
SDA Serial Da a
SCL Serial Clock
TEST Hold a Vss
Vss Ground
Vcc Supply Vol age
NC No Connec

11) TK10930VTL (XA0223)
Charac erris ic Symbol Min Typical Max Typical Condi ion
Supply Curren 1 Icc1 6.8 8.9 mA No signal, AM ON
Supply Curren 2 Icc2 3.9 5.3 mA No signal, AM OFF
Mixer Conversion Gain Mg 20 dB
Mixer Inpu Impedance Mz 3.6 Kn DC Tes
FM
Limi ing Sensi ivi y Limi 2,0 8.0 pv -3.0dB
Ou pu Vol age Vo1 85 150 230 mVrms 10mVin +/-3kHz DEV
Dis or ion THD1 10 2.0 % 10mVin +/-3kHz DEV
Ou pu Impedance Zo 800 a10mVin
Fil er Gain Gf 30 38 dB Fin=30kHz, Vo=100mV
Scan Con rol Hi Vol age SH 2.3 V Squelch inpu =2.5V
Scan Con rol Low Vol age SL 0.3 V Squelch inpu =0V
Squelch Hys eresis Hys 30 mV
S me er Ou pu Vol age SO 0.05 0.5 V Vin=0mV, RS=68kil
S me er Ou pu Vol age S 1 0.05 0.5 0.9 V Vin=0.01mV, RS=68k l
S me er Ou pu Vol age S2 0.7 12 1.7 V Vin=0.1mV, RS=68ka
S me er Ou pu Vol age S3 1.2 1.8 2.5 V Vin=1mV, RS=68kil
S me er Ou pu Vol age S4 1.6 2.3 2.9 VVin=10mV, RS=60kii
S me er Ou pu Vol age S5 1.8 2.4 2.9 V Vin=100mV, RS=68kn
AM
Sensi ivi y US 20 15 ^v When ou pu is 20mVrms.
Ou pu Vol age Vo2 60 120 160 mVrms 1kHz, 30%, Vin=1mV
Dis or ion-1 THD2 1.0 2.0 % 1kHz, 30%, Vin=1mV
Dis or ion-2 THD3 2.0 4.0 %1kHz, 30%, Vin=1mV
S/N Vo1 40 48 dB 1kHz, 30%, Vin=1mV
AM OFF Vo -0.3 0.3 % OFF

12) Transis or, Diode and LED Ou line Drawings Top View
20