Altera Cyclone v User manual

HPS SoC Boot Guide - Cyclone V SoC Development Kit

2016.01.27

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Introduction

is document describes:

• An overview of the boot options available on the Cyclone®V

• Recommendations to help reduce the boot duration, including measurements of the boot process on

the Cyclone V Development Kit

• Recommendations to help with debugging the boot process

• Bare-metal boot examples that can be run on the Cyclone V SoC Development Kit

Note: Although the document targets Cyclone V, it also applies to Arria®V, since the HPS portion is

identical between the two families.

Prerequisite

In order to run the examples presented in this Boot Guide the following are required:

• Altera®Cyclone V Development Kit, Rev D

• Host PC running Windows 7 or newer(1)

• Altera SoC Embedded Design Suite (SoC EDS), v14.1 installed

• Altera Complete Design Suite (ACDS) v14.1(2)

Note: is document assumes a basic knowledge of Altera SoC EDS, ACDS, Preloader Support Package

Generator (part of SoC EDS) and ARM DS-5 AE.

Related Information

•Cyclone V Development Kit and SoC Embedded Design Suite

For more information about the Cyclone V SoC Development board.

•SoC EDS Download

For more information about and where to obtain the latest SoC EDS downloads.

•ACDS Download

For more information about and where to obtain the latest ACDS downloads.

•Altera SoC Embedded Design Suite User Guide

(1) Linux can also be used, with similar commands.

(2) Required only for the boot from FPGA example.

Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current

specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information

and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

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Boot Overview

is chapter presents an overview of the dierent boot options and capabilities available for the Cyclone V.

Boot Flow

e following gure depicts the typical boot ow:

Figure 1: Typical Boot Flow

Additional boot ows are possible, as shown in the following diagram:

Figure 2: Additional Boot Flows

As it can be seen in the above diagram, we always have the Boot ROM, but then we may have more or less

stages, depending on the system design.

Boot ROM

e HPS boot process starts when the processor is released from reset, and jumps to the reset vector

address, located in the Boot ROM address space.

Typically, the main responsibilities of the Boot ROM are:

• Detect the selected boot source

• Perform minimal HPS initialization

• Load the next boot stage (typically the Preloader) from Flash to OCRAM and jump to it

e behavior of the Boot ROM is inuenced by the BSEL and CSEL options, and also by the registers in

System Manger (for RAM boot) as shown later in the document.

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For the scenarios where the next boot stage is located in Flash, the Boot ROM can use up to four dierent

images:

• On Cold reset, the Boot ROM always starts with the rst image, and checks the CRC. If the CRC is OK,

then it passes control to it. If the CRC is not OK, then it tries the next image and so on. Before an image

is passed control, the Boot ROM updates the register sysmgr.romcodegrp.initswlastld with the

image index.

• On a Warm reset, the Boot ROM looks at the register sysmgr.romcodegrp.initswstate for the magic

value 0x49535756. If it is there, it means last Preloader executed OK, so it loads it again and executes it.

If the magic value is not found, it means the previous Preloader was not OK, and the Boot ROM will

advance to the next image and increment sysmgr.romcodegrp.initswlastld.

• If all images are exhausted, the Boot ROM will try to fallback on the FPGA image. It will continue to be

reset by the Watchdog, but will never try to boot from Flash until the next Cold reset.

Note: e BootROM requires a special header to be placed at the beginning of the images that need to be

loaded from ash. e header also contains a checksum that is used for validating the image. e

header can be attached to the image by using the mkpimage tool that is included with the SoC

EDS.

Preloader

Typically, the main responsibilities of the Preloader are:

• Perform additional HPS initialization

• Bring up SDRAM

• Load the next boot stage from Flash to SDRAM and jump to it

Currently, two dierent Preloader options are available:

• SPL – part of U-Boot. Provided with SoC EDS under GPL (Open Source) License

• MPL – provided with SoC EDS as an example using the HWLibs (Altera bare-metal libraries). Uses

BSD license.

Note: e Preloader requires a special header to be placed at the beginning of the next stage boot image.

Also, the header contains a CRC value used to validate the image. e header can be attached to an

image by using the mkimage utility that is included with the SoC EDS.

Bootloader

e Bootloader has typical responsibilities that are similar with the Preloader, except it does not need to

bring up SDRAM.

Because the Bootloader is already residing in SDRAM, it is not limited by the size of the OCRAM.

erefore, it can provide a lot of features, such as network stack support.

Boot Sources

e HPS can boot from one of the following sources, as selected by the BSEL pins:

• SD/MMC

• QSPI

• NAND

• FPGA

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e following table presents the possible BSEL options, together with the actual jumper settings on the

Cyclone V Development kit, rev D:

BSEL Description Cyclone V Dev Kit Switches

J28:BSEL0 J28:BSEL0 J28:BSEL0

0 Reserved Right Right Right

1 FPGA Le Right Right

2 1.8 V NAND - - -

3 3.3 V NAND - - -

4 1.8 V SD/MMC - - -

5 3.3 V SD/MMC Le Right Le

6 1.8 V SPI or quad SPI - - -

7 3.3 V SPI or quad SPI Le Le Le

ere are four boot options:

• Indirect execution - When booting from ash (SD/MMC/QSPI/NAND):

1. e code is loaded by the Boot ROM from the ash to the OCRAM.

2. Run the code from this location

• Direct execution - When booting from FPGA, the Boot ROM simply jumps to an address in the FPGA

address space.

• FPGA fallback boot - If the selected boot mode fails, the Boot ROM will try to jump to a fallback image

in the FPGA, if it exists.

• RAM boot - If an Warm Boot, the System Manager can be congured so that the Boot ROM directly

jumps to a location in OCRAM.

Boot from SD/MMC

When booting from SD/MMC, two dierent options are available:

• Raw mode - Preloader images are located at address0 on the card.

• Partition mode - Preloader images are located at oset 0 on a custom partition with ID=A2 on the

card.

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Figure 3: Raw Mode and Partition Mode Options

e MBR is a 512 byte data structure, located at address 0, describing the partitions existing on the

SD/MMC card.

e Raw mode does not allow the card to be partitioned, since the Preloaders are located at address 0,

where the MBR data structure needs to be placed.

When using the Partition mode, the Preloader is located on a custom partition that does not interfere with

the other partitions on the SD/MMC card. e other partitions could, for example, contain Windows FAT,

or Linux EXT2 or EXT3 le systems, providing more exibility for the overall system design.

Related Information

Booting and Conguration

For more information about the SD/MMC clocking options selected by Boot ROM based on CSEL pins,

refer to the Booting and Conguration chapter of the Cyclone V Technical Reference Manual.

Boot from QSPI

When booting from QSPI, the four Preloader images are always located at the beginning of the QSPI

address space, occupying a total of 256 KB.

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Figure 4: QSPI Address Space

Related Information

Booting and Conguration

For more information about the QSPI commands and clocking options selected by Boot ROM based on

CSEL pins, refer to the Booting and Conguration chapter of the Cyclone V Technical Reference Manual.

Boot from NAND

When booting from NAND, the Preloader images are located at the beginning of the ash. Each image has

to start at NAND ash block boundary.

Figure 5: NAND Flash Block

Note: Booting from NAND is not available on the Cyclone V Development kit.

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Related Information

Booting and Conguration

For more information about the NAND clocking options selected by Boot ROM based on CSEL pins, refer

to the Booting and Conguration chapter of the Cyclone V Technical Reference Manual.

Boot from FPGA

When booting from FPGA, the Boot ROM performs the following operations:

• Waits for FPGA to be congured and in user mode

•Veries that the Boot from FPGA was enabled in the FPGA fabric

• Jumps to address 0xC0000000, corresponding to oset 0 on the HPS-2-FPGA bridge

Note: e conguration on the FPGA side needs to enable the signal notifying the HPS that a boot image

is available (f2h_boot_from_fpga_ready).

Note: No other checking, such as CRC of the image, is performed. No clocking conguration is

performed either, and the CSEL value is ignored.

FPGA Fallback Boot

When the Boot ROM did not successfully load any image, it tries to boot from an FPGA fallback image:

• Checks if the FPGA is congured and in user mode

•Veries that the fallback image was enabled in the FPGA fabric

• Jumps to address 0xC0000000, corresponding to oset 0 on the HPS-2-FPGA bridge

Note: e conguration on the FPGA side needs to enable the signal notifying the HPS that an FPGA

fallback image is available (f2h_boot_from_fpga_on_failure).

Boot from RAM on Warm Reset

is scenario applies only for Warm resets. e Boot ROM can be instructed to directly jump to an image

already loaded in OCRAM with an optional CRC check for that image.

e following registers located in sysmgr (romcodegrp and warmramgrp) are used to set up the Boot from

RAM on Warm Reset:

•enable - Set bit 0 to enable Boot from RAM on Warm reset.

•datastart - Byte oset in OCRAM for the region to be CRC-validated. Needs to be 4 byte aligned.

•length - Size of OCRAM area to be CRC-validated, in 4 byte words. Set to 0 to disable the CRC

validation.

•execution - Byte oset in OCRAM where to jump to.

•crc - CRC value for the OCRAM area that is CRC-validated.

Note: When booting from RAM, the Boot ROM does not do any initialization, including clocking and it

therefore ignores the CSEL pins.

Boot Clocks

e board on which the Cyclone V resides can have dierent clocking needs:

• OSC1 input clock can have dierent values

• Flash memories can have dierent clocking requirements

• Board layout may also impact the maximum ash speeds

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In order to accommodate the above, the Boot ROM can be instructed to use dierent clocking options,

through the CSEL pins. e following table presents the CSEL options available on Cyclone V, together

with the actual jumper settings on the Cyclone V Development Kit, rev D:

Table 1: CSEL Options Available

CSEL Cyclone V Dev Kit Switches

J26:CSEL0 J26:CSEL1

0 Right Right

1Le Right

2 Right Le

3Le Le

Note: In the following cases the Boot ROM does not touch the clocking at all:

• CSEL = 0

• Boot from FPGA

• Fallback boot from FPGA

• RAM boot on Warm reset

Related Information

Booting and Conguration

For more information about what each of the CSEL values mean for each of the BSEL options, refer to the

Booting and Conguration chapter of the Cyclone V Technical Reference Manual.

Boot Duration

In some applications, the duration of the boot process is very critical, and it needs to meet a certain

constraint.

is section presents some considerations on optimizing the boot time, together with some measurements

taken with various options on the Cyclone V Development Kit.

e elements that compose the boot time for a typical Linux system are depicted in the gure below:

Figure 6: Boot Time Stages for Linux Systems

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A typical bare-metal application boot time is depicted in the following gure:

Figure 7: Boot Time Stages for a Bare-Metal Application

Note: e above gures are not drawn to scale - each stage is depicted with the same size.

Optimizing Boot Duration

e recommended approach for optimizing boot time consists of:

• Measure the duration of the total boot time. For example, monitor the reset signal and a custom signal

toggled at the beginning of the application by using a scope or a logical analyzer.

• Measure the duration of as many individual steps as possible, to understand where most of the time is

spent.

• If possible, optimize the steps that take most of the time. Usually the upper levels take longer than the

lower ones.

e following sections describe some of the factors that inuence the duration of the Boot ROM.

Hardware Powerup Sequence

is is the smallest contributor to boot time and it does not need to be optimized. It is actually inuenced

by the OSC1 input clock frequency, but it is so small that its duration does not warrant changing the OSC1

value.

Boot ROM

e duration of the Boot ROM is inuenced by the following factors:

•OSC1 Clock Frequency (for the portion before setting the PLLs or when using CSEL=00)

• Clocking option (selected by CSEL pins)

• Boot Source (SD/MMC, QSPI, NAND or FPGA – selected by BSEL pins)

• Performance of external ash device

• Size of Preloader image

e above parameters can be tweaked in order to optimize the Boot ROM duration. For example, the OSC1

and CSEL should be selected such that the maximum possible clock values are used for both the MPU and

the external ash.

Another example - Tweaking the Preloader so that it is made smaller. e smaller the Preloader, the less

time the Boot ROM spends loading it from ash.

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For the boot from FPGA option, the Preloader loading time is reduced to zero. But the FPGA has to be

already congured for this to be possible, and this takes time, as well.

Related Information

Booting and Conguration

Preloader

e Preloader duration is inuenced by the following elements:

• Location of next boot stage

• Size of next boot stage image

• Speed of SDRAM (since Preloader loads the image from Flash to SDRAM)

• Speed of Flash

• Various Preloader options:

• SDRAM scrubbing

• Hardware diagnostic

• Checking the CRC of the next boot stage image

• Serial logging

• Program FPGA

In order to reduce the Preloader duration, the above parameters may be tweaked. For example:

• Reduce the size of the next boot stage (for example remove networking support from U-Boot if not

needed)

• Use a faster ash (it will require changing Preloader source code – option is not available in Preloader

Generator)

• Disable hardware diagnostic if enabled (uncheck HARDWARE_DIAGNOSTIC in Preloader Generator)

• Disable serial console output - (uncheck SERIAL_SUPPORT in Preloader Generator)

• Disable CRC of the next boot stage image (uncheck CHECKSUM_NEXT_IMAGE in Preloader Generator)

If the FPGA programming is selected in the Preloader, then the following also impacts the duration:

• Location of FPGA Image (QSPI or SD Card FAT partition)

• Size of the FPGA Image (compression may reduce it signicantly)

Bootloader

e duration of the Bootloader is inuenced by the following:

• Size of the next stage to be loaded (Linux kernel for example)

• Location of the next stage (ash, network, etc)

• Whether networking is enabled, and is statically or dynamically (DHCP) congured

• Whether FPGA programming is also performed

• Speed of SDRAM

• Countdown counter(3) (default 5s in U-Boot – can be disabled for production systems)

Linux Kernel

e Linux kernel can be made to start faster, and there is a lot of material in the Linux community on how

to achieve this. For example, removing debugging capabilities and various unneeded drivers and features.

(3) Can be tweaked to achieve faster boot time.

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