ARM CoreLink GFC-200 Product manual

Arm® CoreLink™ GFC-200 Generic Flash Controller
Revision: r0p0
Technical Reference Manual
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101484_0000_01_en

Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved.
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Document history
Issue Date Confidentiality Change
0000-00 19 February 2019 Non-Confidential First early access release for r0p0.
0000-01 28 February 2022 Non-Confidential First release for r0p0 REL.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
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Inclusive language commitment
Arm values inclusive communities. Arm recognizes that we and our industry have used language
that can be offensive. Arm strives to lead the industry and create change.
Previous issues of this document included language that can be offensive. We have replaced this
language. See B Revisions on page 90.
To report offensive language in this document, email [email protected].
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Contents
Contents
1 Introduction....................................................................................................................................................... 8
1.1 Product revision status.................................................................................................................................. 8
1.2 Intended audience.......................................................................................................................................... 8
1.3 Conventions......................................................................................................................................................8
1.4 Additional reading.........................................................................................................................................10
2 Overview..........................................................................................................................................................11
2.1 About the GFC-200.................................................................................................................................... 11
2.2 Compliance.....................................................................................................................................................12
2.3 Features...........................................................................................................................................................13
2.4 Configurable options....................................................................................................................................14
2.5 Test features.................................................................................................................................................. 14
2.6 Product documentation...............................................................................................................................14
2.7 Product revisions.......................................................................................................................................... 15
3 Functional Description................................................................................................................................. 16
3.1 Internal structure.......................................................................................................................................... 16
3.2 Interfaces........................................................................................................................................................ 17
3.2.1 AHB-Lite subordinate interface.............................................................................................................18
3.2.2 Primary APB completer interface..........................................................................................................20
3.2.3 Secondary APB completer interface.................................................................................................... 21
3.2.4 APB requester interface..........................................................................................................................22
3.2.5 GFB interface.............................................................................................................................................22
3.2.6 Q-Channel interface for clock............................................................................................................... 24
3.2.7 Q-Channel interface for power.............................................................................................................24
3.2.8 P-Channel controller interface...............................................................................................................25
3.2.9 Partition configuration interface............................................................................................................25
3.2.10 System interface..................................................................................................................................... 27
3.3 Clocking...........................................................................................................................................................28
3.4 Resets.............................................................................................................................................................. 28
3.5 Interrupt sources...........................................................................................................................................28
3.6 Generic Flash Bus arbiter...........................................................................................................................30
3.7 Flash power control..................................................................................................................................... 31
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
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Issue: 01
Contents
4 Programmers Model..................................................................................................................................... 32
4.1 About this programmers model................................................................................................................ 32
4.2 Memory maps............................................................................................................................................... 32
4.2.1 AHB subordinate interface memory map........................................................................................... 33
4.2.2 APB memory maps...................................................................................................................................38
4.3 Register summary......................................................................................................................................... 39
4.4 Register descriptions....................................................................................................................................40
4.4.1 Interrupt enable set register, IRQ_ENABLE_SET...............................................................................40
4.4.2 Interrupt enable clear register, IRQ_ENABLE_CLR........................................................................... 42
4.4.3 Interrupt status set register, IRQ_STATUS_SET.................................................................................43
4.4.4 Interrupt status clear register, IRQ_STATUS_CLR.............................................................................45
4.4.5 Interrupt masked status register, IRQ_MASKED_STATUS.............................................................. 46
4.4.6 Control register, CTRL............................................................................................................................. 47
4.4.7 Status register, STATUS...........................................................................................................................49
4.4.8 Address register, ADDR...........................................................................................................................50
4.4.9 Data 0 register, DATA0...........................................................................................................................51
4.4.10 Data 1 register, DATA1.........................................................................................................................52
4.4.11 Data 2 register, DATA2.........................................................................................................................53
4.4.12 Data 3 register, DATA3.........................................................................................................................54
4.4.13 Partition ownership status register, PART_CTRL_RW_STATUS...................................................55
4.4.14 Partition control read-only status register, PART_CTRL_RO_STATUS........................................56
4.4.15 Partition control read status register, PART_CTRL_RD_STATUS.................................................57
4.4.16 Partition configuration mode request register, PART_CONFIG_MODE_REQ.......................... 58
4.4.17 Partition configuration mode status register, PART_CONFIG_MODE_STATUS.......................59
4.4.18 Access violation response register, ACCESS_ERR_RESP_CTRL...................................................60
4.4.19 Access violation response register, ACCESS_ERR_INFO.............................................................. 61
4.4.20 Power state status register, POWER_STATE................................................................................... 62
4.4.21 Power state request register, POWER_STATE_REQ...................................................................... 63
4.4.22 Hardware parameters register, HWPARAMS...................................................................................64
4.4.23 Peripheral ID register 4, PIDR4.......................................................................................................... 66
4.4.24 Peripheral ID register 0, PIDR0.......................................................................................................... 67
4.4.25 Peripheral ID register 1, PIDR1.......................................................................................................... 68
4.4.26 Peripheral ID register 2, PIDR2.......................................................................................................... 69
4.4.27 Peripheral ID register 3, PIDR3.......................................................................................................... 70
4.4.28 Component ID register 0, CIDR0.......................................................................................................71
4.4.29 Component ID register 1, CIDR1.......................................................................................................71
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
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Contents
4.4.30 Component ID register 2, CIDR2.......................................................................................................72
4.4.31 Component ID register 3, CIDR3.......................................................................................................73
4.5 Accessing Flash from the APB completer interfaces........................................................................... 74
4.6 Preloading transfers..................................................................................................................................... 76
4.7 Reconfiguring the partition access rights................................................................................................80
4.8 Flash macro power control........................................................................................................................ 81
A Signal Descriptions....................................................................................................................................... 82
A.1 System interface signals............................................................................................................................. 82
A.2 AHB-Lite subordinate interface signals.................................................................................................. 82
A.3 APB completer interface signals...............................................................................................................84
A.4 APB requester interface signals................................................................................................................85
A.5 GFB manager interface signals................................................................................................................. 86
A.6 Partition control interface signals.............................................................................................................87
A.7 Q-Channel interface signals...................................................................................................................... 88
A.8 P-Channel controller interface signals.....................................................................................................89
A.9 DFT signals.................................................................................................................................................... 89
B Revisions..........................................................................................................................................................90
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Introduction
1 Introduction
1.1 Product revision status
The rxpy identifier indicates the revision status of the product described in this manual, for
example, r1p2, where:
rxIdentifies the major revision of the product, for example, r1.
pyIdentifies the minor revision or modification status of the product, for example, p2.
1.2 Intended audience
This book is for system designers, system integrators, and programmers who are designing or
programming a System-on-Chip (SoC) that uses the GFC-200 Generic Flash Controller.
1.3 Conventions
The following subsections describe conventions used in Arm documents.
Glossary
The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for
those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm
meaning differs from the generally accepted meaning.
See the Arm Glossary for more information: developer.arm.com/glossary.
Typographic conventions
Convention Use
italic Citations.
bold Interface elements, such as menu names.
Signal names.
Terms in descriptive lists, where appropriate.
monospace Text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace bold Language keywords when used outside example code.
monospace underline A permitted abbreviation for a command or option. You can enter the underlined text instead of the full
command or option name.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
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Issue: 01
Introduction
Convention Use
<and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS Terms that have specific technical meanings as defined in the Arm® Glossary. For example,
IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Recommendations. Not following these recommendations might lead to system failure or damage.
Requirements for the system. Not following these requirements might result in system failure or damage.
Requirements for the system. Not following these requirements will result in system failure or damage.
An important piece of information that needs your attention.
A useful tip that might make it easier, better or faster to perform a task.
A reminder of something important that relates to the information you are reading.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does not affect normal operation.
Figure 1-1: Key to timing diagram conventions
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Introduction
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
•HIGH for active-HIGH signals.
•LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name, n denotes an active-LOW signal.
1.4 Additional reading
This document contains information that is specific to this product. See the following documents
for other relevant information:
Table 1-2: Arm publications
Document name Document ID Licensee only
AMBA® APB Protocol Specification Version 2.0 IHI 0024 No
AMBA® 3 AHB‑Lite Protocol Specification v1.0 IHI 0033A No
AMBA® Low Power Interface Specification, Arm® Q‑Channel and P‑Channel Interfaces IHI 0068 No
Arm® CoreLink™ GFC‑200 Generic Flash Controller Configuration and Integration Manual 101485 Yes
AMBA® Generic Flash Bus Protocol Specification IHI 0083 Yes
Table 1-3: Other publications
Document ID Organization Document name
JEP106 JEDEC Standard Manufacturer’s Identification Code
Arm tests its PDFs only in Adobe Acrobat and Acrobat Reader. Arm cannot
guarantee the quality of its documents when used with any other PDF reader.
Adobe PDF reader products can be downloaded at http://www.adobe.com
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Overview
2 Overview
Read this for an introduction to the GFC-200 Generic Flash Controller and its features.
2.1 About the GFC-200
The GFC-200 Generic Flash Controller comprises the generic part of a Flash controller in a System-
on-Chip (SoC). The GFC-200 enables an embedded Flash macro to be integrated easily into any
system.
An eFlash macro enables a Flash controller to access eFlash memory. The eFlash macros produced
by different foundries and processes can have different interfaces, timings, signal names, protocols,
and features that are determined by the foundry processes that produced the eFlash memory.
The GFC-200 provides functions that relate only to services for the system side of the Flash
controller. The GFC-200 cannot communicate directly with the eFlash macro. Therefore, the
GFC-200 must be integrated with a process-specific part that connects to, and communicates with,
the eFlash macro.
The process-specific part of the Flash controller is part of the Flash subsystem in your SoC. It
communicates directly with the eFlash macro through a Flash interface.
The GFC-200 supports accesses from two managers that can operate in separate domains such
as a Non-secure domain and a Secure domain. Communication between the system and eFlash
memory is through a Generic Flash Bus (GFB) supplied with GFC-200.
The following figure shows how the GFC-200 is used in a Flash controller implementation.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Overview
Figure 2-1: GFC-200 in a Flash controller implementation
Flash subsystem
Flash controller
Non-secure system
(secondary domain)
Secure system
(primary domain)
GFC-200 Generic Flash Controller
Process-specific part
eFlash macro
Generic Flash Bus
Flash interface
2.2 Compliance
The GFC-200 interfaces are compliant with Arm specifications and protocols.
The GFC-200 is compliant with the:
•AMBA® GFB protocol. See the AMBA® Generic Flash Bus Protocol Specification.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
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Overview
•AMBA® 3 AHB-Lite protocol. See the AMBA® 3 AHB‑Lite Protocol Specification v1.0.
•AMBA® 4 APB protocol. See the AMBA® APB Protocol Specification Version 2.0.
•AMBA® Low Power Interface specification. See the AMBA® Low Power Interface Specification,
Arm® Q‑Channel and P‑Channel Interfaces.
2.3 Features
The GFC-200 provides several interfaces and features.
Flash memory partitioning:
•Ability to divide the available Flash memory space into several partitions and perform access
control on a per partition basis
•Dynamically configurable access rights to partitions
•A configuration parameter controls the size of the partitions
AMBA® AHB-Lite interface:
•Read-only access to the embedded Flash
•Configurable data width
•Burst support
•Low latency
Primary APB completer interface:
•Write and erase access to the embedded Flash
•Debug read access to the embedded Flash
•Control port for GFC-200 and the eFlash macro
•Interrupt capability for long running commands
•Access to internal registers and the control registers in the process-specific part
Secondary APB completer interface:
•Write and erase access to the embedded Flash
•Debug read access to the embedded Flash
•Control port for GFC-200
•Interrupt capability for long running commands
•Access to internal registers
APB register requester interface:
•Enables access to the registers in the process-specific part
Q-Channel interface:
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
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Issue: 01
Overview
•Control port for system power
•Control port for the system clock
P-Channel controller interface:
•Control port for power to the process-specific part
Generic Flash Bus (GFB):
•Enables GFC-200 accesses to embedded Flash
•Simple command-based protocol
•Synchronous with the AHB clock
•Simplifies communication between GFC-200 and the attached process-specific part
2.4 Configurable options
The GFC-200 provides design-time configuration options.
At design-time, you can configure:
•The width of the AHB read data bus, by using the HRDATA_WIDTH parameter.
•The width of the GFB read data bus, by using the FRDATA_WIDTH parameter.
•The width of the GFB write data bus, by using the FWDATA_WIDTH parameter.
•The size of the partitions in Flash memory, by using the PARTITION_SIZE parameter.
2.5 Test features
GFC-200 provides components that comprise a Flash model, that simulates the behavior of the
process‑specific part and the attached embedded Flash.
The GFC-200 deliverables include an Out‑of‑Box (OoB) execution testbench. You can use
the execution testbench to check that the delivered RTL is complete and that it can perform
transactions towards the Flash model as expected.
2.6 Product documentation
Documentation that is provided with this product includes a Technical Reference Manual (TRM) and
a Configuration and Integration Manual (CIM), together with architecture and protocol information.
For relevant protocol and architectural information that relates to this product, see 1.4 Additional
reading on page 10".
The GFC-200 documentation is as follows:
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
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Overview
Technical Reference Manual
The TRM describes the functionality and the effects of functional options on the behavior
of GFC-200. It is required at all stages of the design flow. The choices that are made in the
design flow can mean that some behaviors that the TRM describes are not relevant. If you
are programming GFC-200, contact:
•The implementer to determine:
◦ The build configuration of the implementation.
◦ What integration, if any, was performed before implementing GFC-200.
•The integrator to determine the signal configuration of the device that you use.
The TRM complements architecture and protocol specifications and relevant external
standards. It does not duplicate information from these sources.
Configuration and Integration Manual
The CIM describes:
•The available build configuration options.
•How to configure the RTL with the build configuration options.
•How to integrate GFC-200 into an SoC.
•How to implement GFC-200 into your design.
•The processes to validate the configured design.
The Arm product deliverables include reference scripts and information about using them to
implement your design.
The CIM is a confidential book that is only available to licensees.
2.7 Product revisions
This section describes the differences in functionality between product revisions:
r0p0 First release.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
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Functional Description
3 Functional Description
Read this for a description of the GFC-200 Generic Flash Controller functions.
3.1 Internal structure
GFC-200 comprises several submodules.
The following figure shows the internal high-level structure of an example system that integrates
GFC-200 with a process-specific part and embedded Flash.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
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Functional Description
Figure 3-1: GFC-200 internal structure
eFlash subsystem
APB 1
completer
AHB
subordinate
Line
buffer
Line
buffer
APB 0
completer
LPI-Q LPI-Q
APB 1
registers
APB 0
registers
Q-Channel
controller
Flash power control
P-Channel
controller
APB
requester
Arbiter
GFB
Process-specific part
GFB receiver FSM
APB completer
LPI-P PCSM
LPI-PAPB
GFB
Register block
Timer block
Flash memory interface
Flash power control
eFlash macro
Flash data path
Flash power management
Main system
(secondary domain)
AHB
interconnect
APB
AHB-Lite
Secure enclave
(primary domain)
partition_ctrl_ro[15:0]
Power Policy
Unit
Q-Channel power
ACG
Address
decoding
AHB2APB
bridge
APB
Arm TrustZone
technology filters,
AHB and APB
interconnects
partition_ctrl_rd[15:0]
partition_ctrl_rw[15:0]
Clock
controller
ACG
clk
Reset
synchronizer
Reset
controller
resetn
hpart logic
hpart
Q-Channel
clock
GFC-200
3.2 Interfaces
GFC-200 has several interfaces that enable it to communicate with the system and the process-
specific part.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
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Functional Description
3.2.1 AHB-Lite subordinate interface
The AHB-Lite subordinate interface is a read-only port through which the system can make read-
only accesses to the embedded Flash. System accesses through the AHB-Lite subordinate interface
are then transferred over the Generic Flash Bus (GFB).
Data width
The HRDATA_WIDTH configuration parameter sets the width of the data bus. Read accesses that are
greater than HRDATA_WIDTH are ignored and generate an error response. Write accesses of any size
are ignored and generate an error response.
If the GFB read data bus width is smaller than the AHB data bus width, then hsize
must not exceed the GFB read data bus width otherwise the GFC-200 generates
an error response. The FRDATA_WIDTH configuration parameter sets the width of the
GFB read data bus.
The address of the access does not have to be aligned to the data width, because it is forwarded to
the GFB directly without any restriction. The AMBA® Generic Flash Bus Protocol Specification defines
that, for wider data widths, the lower address bits are ignored. Although the AHB specification
defines that the address must be aligned for all bursts, and single bursts, GFC-200 does not
generate an error if an access is not aligned.
Line buffers
If the configured GFB data width is greater than the AHB data width, then each domain has a
dedicated line buffer in the AHB interface logic.
Each line buffer can store an entire Flash read data word. If a new AHB read request targets an
address for which the data is available in the line buffer, then the GFC-200 fulfills the request
without initiating any GFB transactions. The line buffers reduce the number of Flash accesses to
the minimum.
AHB sideband signal for access rights checking
The hpart input is a sideband signal on the AHB interface to identify the manager that initiates an
AHB transaction. External logic must drive this signal for each AHB transfer during the address
phase, depending on which domain initiates the transfer. For AHB transfers, the GFC-200 uses
hpart to perform access permission checking and line buffer selection. Therefore, the system must
drive hpart to the correct logic value and it must remain stable during the entire address phase, and
during waited transfers.
Address width
The address width is fixed to allow for access to a 4MB memory area.
If the process-specific Flash controller allows less than 4MB or the Flash macro is smaller than
4MB, then aliasing might occur in the process-specific part. Therefore, the process-specific
controller must provide protection against aliasing, so that it can give an error response for any out-
of-range addresses.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
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Functional Description
See 4.2.1 AHB subordinate interface memory map on page 32 for a description of the AHB-
Lite subordinate interface memory map.
Burst transfers
Burst transfers are supported to allow large blocks of data to be read from memory. GFC-200
supports all burst types that are specified in the AMBA® 3 AHB‑Lite Protocol Specification v1.0. Burst
transfers ensure that read accesses from the memory have priority above any other commands,
and are executed at the same speed as commands are executed in the process-specific part.
Locked transfers
A system AHB manager can use locked transfers to control the GFC-200 arbitration scheme.
Access is granted to the AHB-Lite subordinate port only, and all APB accesses are blocked until
the entire locked transfer finishes. This behavior ensures that accesses through the AHB-Lite
subordinate port have deterministic response times.
Delayed response
The response time through the AHB-Lite subordinate interface is delayed by asserting the
hreadyout signal LOW. The following conditions assert hreadyout:
•A delayed GFB transfer response, because the embedded Flash is slow to respond.
•The GFB arbiter block selects a different requestor to access the memory.
•An AHB manager initiates a transfer while a Q-Channel interface is in the Q_STOPPED state.
•The GFB has a transfer in progress.
A Flash write or erase operation can require millions of clock cycles that can
significantly block the AHB interconnect.
Error response
The following conditions can generate an error response:
•An AHB manager sends a write access to the GFC-200.
•The hsize data width exceeds HRDATA_WIDTH, when HRDATA_WIDTH ≤ FRDATA_WIDTH.
•The hsize data width exceeds FRDATA_WIDTH, when FRDATA_WIDTH ≤ HRDATA_WIDTH.
•A GFB transfer generates an error response.
•The primary AHB manager (hpart == 0) initiates an access to partition that belongs to the
secondary AHB manager (hpart == 1), when the partition_ctrl_rd signal does not grant read
access to the non-owner of that partition.
•The secondary AHB manager (hpart == 1) initiates an access to partition that belongs to the
primary AHB manager (hpart == 0), when the partition_ctrl_rd signal does not grant read
access to the non-owner of that partition.
•If the secondary AHB manager (hpart == 1) initiates an access, while the GFC-200 is in
partition configuration mode.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Functional Description
Related information
AHB-Lite subordinate interface signals on page 82
Partition configuration interface on page 25
3.2.2 Primary APB completer interface
The primary APB completer interface enables read, write, and erase access to the embedded Flash,
if that partition has the appropriate R/W permissions set. It also acts as a control port for GFC-200
and the Flash macro.
The primary APB interface also provides direct access to a register interface that is external to
GFC-200. If the process-specific part contains programmable registers, then software can use the
primary APB interface to initialize its parameters such as the Flash interface access times.
The secondary APB interface does not have access to the external registers.
Address width
The address width is fixed at 13 bits, to allow for 2 × 4KB address spaces. One 4KB region is
for internal registers, and the other 4KB region is for external registers that might reside in the
process-specific part. The MSB, paddr_s[12], selects either internal or external accesses.
See 4.2.2 APB memory maps on page 38 for a description of the APB completer interface
memory map.
Strobe signals
The strobe signals are checked for writes to ensure that all bits are set to 1 to indicate 32-bit word
accesses. Otherwise the write is ignored and has no effect on the registers. The strobe signals are
forwarded to the downstream APB requester, because the process-specific part might support byte
accesses.
Delayed response
Accesses to the internal register bank are serviced without delay. The design of the process-
specific register bank determines how much delay can be expected for accesses that target its
interface.
Error response
APB accesses to the internal register bank always give an OKAY response. For reads of reserved
addresses, the GFC-200 sets prdata_s0 LOW. The GFC-200 ignores writes to a reserved address.
The response behavior to external register accesses depends on the implementation of the
attached process-specific register bank. Therefore, any errors that the APB requester interface
receives, are forwarded through the APB completer interface to the access initiator.
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