ARM CoreLink GFC-200 Product manual

Arm® CoreLink™ GFC-200 Generic Flash Controller
Revision: r0p0
Technical Reference Manual
Non-Confidential
Copyright © 2019, 2022 Arm Limited (or its affiliates).
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Issue 01
101484_0000_01_en

Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Copyright © 2019, 2022 Arm Limited (or its affiliates). All rights reserved.
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Document history
Issue Date Confidentiality Change
0000-00 19 February 2019 Non-Confidential First early access release for r0p0.
0000-01 28 February 2022 Non-Confidential First release for r0p0 REL.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Inclusive language commitment
Arm values inclusive communities. Arm recognizes that we and our industry have used language
that can be offensive. Arm strives to lead the industry and create change.
Previous issues of this document included language that can be offensive. We have replaced this
language. See B Revisions on page 90.
To report offensive language in this document, email [email protected].
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Contents
Contents
1 Introduction....................................................................................................................................................... 8
1.1 Product revision status.................................................................................................................................. 8
1.2 Intended audience.......................................................................................................................................... 8
1.3 Conventions......................................................................................................................................................8
1.4 Additional reading.........................................................................................................................................10
2 Overview..........................................................................................................................................................11
2.1 About the GFC-200.................................................................................................................................... 11
2.2 Compliance.....................................................................................................................................................12
2.3 Features...........................................................................................................................................................13
2.4 Configurable options....................................................................................................................................14
2.5 Test features.................................................................................................................................................. 14
2.6 Product documentation...............................................................................................................................14
2.7 Product revisions.......................................................................................................................................... 15
3 Functional Description................................................................................................................................. 16
3.1 Internal structure.......................................................................................................................................... 16
3.2 Interfaces........................................................................................................................................................ 17
3.2.1 AHB-Lite subordinate interface.............................................................................................................18
3.2.2 Primary APB completer interface..........................................................................................................20
3.2.3 Secondary APB completer interface.................................................................................................... 21
3.2.4 APB requester interface..........................................................................................................................22
3.2.5 GFB interface.............................................................................................................................................22
3.2.6 Q-Channel interface for clock............................................................................................................... 24
3.2.7 Q-Channel interface for power.............................................................................................................24
3.2.8 P-Channel controller interface...............................................................................................................25
3.2.9 Partition configuration interface............................................................................................................25
3.2.10 System interface..................................................................................................................................... 27
3.3 Clocking...........................................................................................................................................................28
3.4 Resets.............................................................................................................................................................. 28
3.5 Interrupt sources...........................................................................................................................................28
3.6 Generic Flash Bus arbiter...........................................................................................................................30
3.7 Flash power control..................................................................................................................................... 31
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Contents
4 Programmers Model..................................................................................................................................... 32
4.1 About this programmers model................................................................................................................ 32
4.2 Memory maps............................................................................................................................................... 32
4.2.1 AHB subordinate interface memory map........................................................................................... 33
4.2.2 APB memory maps...................................................................................................................................38
4.3 Register summary......................................................................................................................................... 39
4.4 Register descriptions....................................................................................................................................40
4.4.1 Interrupt enable set register, IRQ_ENABLE_SET...............................................................................40
4.4.2 Interrupt enable clear register, IRQ_ENABLE_CLR........................................................................... 42
4.4.3 Interrupt status set register, IRQ_STATUS_SET.................................................................................43
4.4.4 Interrupt status clear register, IRQ_STATUS_CLR.............................................................................45
4.4.5 Interrupt masked status register, IRQ_MASKED_STATUS.............................................................. 46
4.4.6 Control register, CTRL............................................................................................................................. 47
4.4.7 Status register, STATUS...........................................................................................................................49
4.4.8 Address register, ADDR...........................................................................................................................50
4.4.9 Data 0 register, DATA0...........................................................................................................................51
4.4.10 Data 1 register, DATA1.........................................................................................................................52
4.4.11 Data 2 register, DATA2.........................................................................................................................53
4.4.12 Data 3 register, DATA3.........................................................................................................................54
4.4.13 Partition ownership status register, PART_CTRL_RW_STATUS...................................................55
4.4.14 Partition control read-only status register, PART_CTRL_RO_STATUS........................................56
4.4.15 Partition control read status register, PART_CTRL_RD_STATUS.................................................57
4.4.16 Partition configuration mode request register, PART_CONFIG_MODE_REQ.......................... 58
4.4.17 Partition configuration mode status register, PART_CONFIG_MODE_STATUS.......................59
4.4.18 Access violation response register, ACCESS_ERR_RESP_CTRL...................................................60
4.4.19 Access violation response register, ACCESS_ERR_INFO.............................................................. 61
4.4.20 Power state status register, POWER_STATE................................................................................... 62
4.4.21 Power state request register, POWER_STATE_REQ...................................................................... 63
4.4.22 Hardware parameters register, HWPARAMS...................................................................................64
4.4.23 Peripheral ID register 4, PIDR4.......................................................................................................... 66
4.4.24 Peripheral ID register 0, PIDR0.......................................................................................................... 67
4.4.25 Peripheral ID register 1, PIDR1.......................................................................................................... 68
4.4.26 Peripheral ID register 2, PIDR2.......................................................................................................... 69
4.4.27 Peripheral ID register 3, PIDR3.......................................................................................................... 70
4.4.28 Component ID register 0, CIDR0.......................................................................................................71
4.4.29 Component ID register 1, CIDR1.......................................................................................................71
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Contents
4.4.30 Component ID register 2, CIDR2.......................................................................................................72
4.4.31 Component ID register 3, CIDR3.......................................................................................................73
4.5 Accessing Flash from the APB completer interfaces........................................................................... 74
4.6 Preloading transfers..................................................................................................................................... 76
4.7 Reconfiguring the partition access rights................................................................................................80
4.8 Flash macro power control........................................................................................................................ 81
A Signal Descriptions....................................................................................................................................... 82
A.1 System interface signals............................................................................................................................. 82
A.2 AHB-Lite subordinate interface signals.................................................................................................. 82
A.3 APB completer interface signals...............................................................................................................84
A.4 APB requester interface signals................................................................................................................85
A.5 GFB manager interface signals................................................................................................................. 86
A.6 Partition control interface signals.............................................................................................................87
A.7 Q-Channel interface signals...................................................................................................................... 88
A.8 P-Channel controller interface signals.....................................................................................................89
A.9 DFT signals.................................................................................................................................................... 89
B Revisions..........................................................................................................................................................90
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Introduction
1 Introduction
1.1 Product revision status
The rxpy identifier indicates the revision status of the product described in this manual, for
example, r1p2, where:
rxIdentifies the major revision of the product, for example, r1.
pyIdentifies the minor revision or modification status of the product, for example, p2.
1.2 Intended audience
This book is for system designers, system integrators, and programmers who are designing or
programming a System-on-Chip (SoC) that uses the GFC-200 Generic Flash Controller.
1.3 Conventions
The following subsections describe conventions used in Arm documents.
Glossary
The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for
those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm
meaning differs from the generally accepted meaning.
See the Arm Glossary for more information: developer.arm.com/glossary.
Typographic conventions
Convention Use
italic Citations.
bold Interface elements, such as menu names.
Signal names.
Terms in descriptive lists, where appropriate.
monospace Text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace bold Language keywords when used outside example code.
monospace underline A permitted abbreviation for a command or option. You can enter the underlined text instead of the full
command or option name.
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Introduction
Convention Use
<and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS Terms that have specific technical meanings as defined in the Arm® Glossary. For example,
IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Recommendations. Not following these recommendations might lead to system failure or damage.
Requirements for the system. Not following these requirements might result in system failure or damage.
Requirements for the system. Not following these requirements will result in system failure or damage.
An important piece of information that needs your attention.
A useful tip that might make it easier, better or faster to perform a task.
A reminder of something important that relates to the information you are reading.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does not affect normal operation.
Figure 1-1: Key to timing diagram conventions
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Arm® CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Introduction
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
•HIGH for active-HIGH signals.
•LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name, n denotes an active-LOW signal.
1.4 Additional reading
This document contains information that is specific to this product. See the following documents
for other relevant information:
Table 1-2: Arm publications
Document name Document ID Licensee only
AMBA® APB Protocol Specification Version 2.0 IHI 0024 No
AMBA® 3 AHB‑Lite Protocol Specification v1.0 IHI 0033A No
AMBA® Low Power Interface Specification, Arm® Q‑Channel and P‑Channel Interfaces IHI 0068 No
Arm® CoreLink™ GFC‑200 Generic Flash Controller Configuration and Integration Manual 101485 Yes
AMBA® Generic Flash Bus Protocol Specification IHI 0083 Yes
Table 1-3: Other publications
Document ID Organization Document name
JEP106 JEDEC Standard Manufacturer’s Identification Code
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