ARM PrimeCell PL241 Product manual

Copyright © 2006 ARM Limited. All rights reserved.
ARM DDI 0389B
PrimeCell®AHB SRAM/NOR
Memory Controller (PL241)
Revision: r0p1
Technical Reference Manual

ii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
PrimeCell AHB SRAM/NOR Memory Controller (PL241)
Technical Reference Manual
Copyright © 2006 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM Limited in good faith.
However, all warranties implied or expressed, including but not limited to implied warranties of
merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change History
Date Issue Confidentiality Change
17 March 2006 A Non-Confidential First release for r0p0.
20 December 2006 B Non-Confidential Updated for r0p1.

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. iii
Contents
PrimeCell AHB SRAM/NOR Memory Controller
(PL241) Technical Reference Manual
Preface
About this manual .......................................................................................... x
Feedback ..................................................................................................... xiv
Chapter 1 Introduction
1.1 About the AHB MC ...................................................................................... 1-2
1.2 Supported devices ...................................................................................... 1-5
Chapter 2 Functional Overview
2.1 Functional description ................................................................................. 2-2
2.2 SMC ............................................................................................................ 2-4
2.3 Functional operation ................................................................................... 2-7
2.4 SMC functional operation .......................................................................... 2-15
Chapter 3 Programmer’s Model
3.1 About the programmer’s model ................................................................... 3-2
3.2 Register summary ....................................................................................... 3-3
3.3 Register descriptions .................................................................................. 3-6

Contents
iv Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Chapter 4 Programmer’s Model for Test
4.1 SMC integration test registers .................................................................... 4-2
Chapter 5 Device Driver Requirements
5.1 Memory initialization ................................................................................... 5-2
Appendix A Signal Descriptions
A.1 About the signals list ................................................................................... A-2
A.2 Clocks and resets ....................................................................................... A-3
A.3 AHB signals ................................................................................................ A-4
A.4 SMC memory interface signals ................................................................... A-5
A.5 SMC miscellaneous signals ........................................................................ A-6
A.6 Low-power interface ................................................................................... A-7
A.7 Configuration signal .................................................................................... A-8
A.8 Scan chains ................................................................................................ A-9
Glossary

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. v
List of Tables
PrimeCell AHB SRAM/NOR Memory Controller
(PL241) Technical Reference Manual
Change History ............................................................................................................. ii
Table 2-1 Static memory clocking options ............................................................................... 2-12
Table 2-2 Asynchronous read opmode chip register settings ................................................. 2-28
Table 2-3 Asynchronous read SRAM cycles register settings ................................................. 2-28
Table 2-4 Asynchronous read in multiplexed-mode opmode chip register settings ................ 2-29
Table 2-5 Asynchronous read in multiplexed-mode SRAM cycles register settings ............... 2-29
Table 2-6 Asynchronous write opmode chip register settings ................................................. 2-30
Table 2-7 Asynchronous write SRAM cycles register settings ................................................ 2-30
Table 2-8 Asynchronous write in multiplexed-mode opmode chip register settings ................ 2-31
Table 2-9 Asynchronous write in multiplexed-mode SRAM cycles register settings ............... 2-31
Table 2-10 Page read opmode chip register settings ................................................................ 2-31
Table 2-11 Page read SRAM cycles register settings ............................................................... 2-31
Table 2-12 Synchronous burst read opmode chip register settings .......................................... 2-32
Table 2-13 Synchronous burst read SRAM cycles register settings ......................................... 2-32
Table 2-14 Synchronous burst read in multiplexed-mode opmode chip register settings ......... 2-34
Table 2-15 Synchronous burst read in multiplexed-mode read SRAM cycles register settings 2-34
Table 2-16 Synchronous burst write opmode chip register settings .......................................... 2-35
Table 2-17 Synchronous burst write SRAM cycles register settings ......................................... 2-35
Table 2-18 Synchronous burst write in multiplexed-mode opmode chip register settings ......... 2-36
Table 2-19 Synchronous burst write in multiplexed-mode SRAM cycles register settings ........ 2-36
Table 2-20 Synchronous read and asynchronous write opmode chip register settings ............ 2-37

List of Tables
vi Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Table 2-21 Synchronous read and asynchronous write opmode chip register settings ............ 2-37
Table 3-1 Register summary ..................................................................................................... 3-4
Table 3-2 smc_memc_status Register bit assignments ........................................................... 3-6
Table 3-3 smc_memif_cfg Register bit assignments ................................................................ 3-7
Table 3-4 smc_memc_cfg_set Register bit assignments ......................................................... 3-9
Table 3-5 smc_memc_cfg_clr Register bit assignments .......................................................... 3-9
Table 3-6 smc_direct_cmd Register bit assignments ............................................................. 3-10
Table 3-7 smc_set_cycles Register bit assignments .............................................................. 3-11
Table 3-8 smc_set_opmode Register bit assignments ........................................................... 3-13
Table 3-9 smc_refresh_period_0 Register bit assignments .................................................... 3-15
Table 3-10 smc_sram_cycles Register bit assignments ........................................................... 3-16
Table 3-11 smc_opmode Register bit assignments .................................................................. 3-17
Table 3-12 smc_user_status Register bit assignments ............................................................ 3-18
Table 3-13 smc_user_config Register bit assignments ............................................................ 3-19
Table 3-14 smc_periph_id Register bit assignments ................................................................ 3-19
Table 3-15 smc_periph_id_0 Register bit assignments ............................................................ 3-20
Table 3-16 smc_periph_id_1 Register bit assignments ............................................................ 3-21
Table 3-17 smc_periph_id_2 Register bit assignments ............................................................ 3-21
Table 3-18 smc_periph_id_3 Register bit assignments ............................................................ 3-21
Table 3-19 smc_pcell_id Register bit assignments ................................................................... 3-22
Table 3-20 smc_pcell_id_0 Register bit assignments ............................................................... 3-23
Table 3-21 smc_pcell_id_1 Register bit assignments ............................................................... 3-23
Table 3-22 smc_pcell_id_2 Register bit assignments ............................................................... 3-24
Table 3-23 smc_pcell_id_3 Register bit assignments ............................................................... 3-24
Table 4-1 SMC test register summary ...................................................................................... 4-2
Table 4-2 smc_int_cfg Register bit assignments ...................................................................... 4-3
Table 4-3 smc_int_inputs Register bit assignments ................................................................. 4-3
Table 4-4 smc_int_outputs Register bit assignments ............................................................... 4-4
Table A-1 Clocks and resets ..................................................................................................... A-3
Table A-2 AHB signals .............................................................................................................. A-4
Table A-3 SMC memory interface signals ................................................................................. A-5
Table A-4 SMC miscellaneous signals ...................................................................................... A-6
Table A-5 Low-power interface signals ..................................................................................... A-7
Table A-6 Configuration signal .................................................................................................. A-8
Table A-7 Scan chain signals .................................................................................................... A-9

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. vii
List of Figures
PrimeCell AHB SRAM/NOR Memory Controller
(PL241) Technical Reference Manual
Key to timing diagram conventions ............................................................................. xii
Figure 1-1 AHB MC (PL241) configuration ................................................................................. 1-2
Figure 2-1 AHB MC (PL241) configuration ................................................................................. 2-2
Figure 2-2 AHB MC (PL241) clock domains ............................................................................... 2-3
Figure 2-3 SMC block diagram ................................................................................................... 2-4
Figure 2-4 SMC SRAM pad interface external connections ....................................................... 2-6
Figure 2-5 Big-endian implementation ...................................................................................... 2-10
Figure 2-6 AHBC memory map ................................................................................................ 2-11
Figure 2-7 Request to enter low-power mode .......................................................................... 2-13
Figure 2-8 AHB domain denying a low-power request ............................................................. 2-13
Figure 2-9 Accepting requests .................................................................................................. 2-14
Figure 2-10 SMC aclk domain FSM ........................................................................................... 2-15
Figure 2-11 Chip configuration registers .................................................................................... 2-23
Figure 2-12 Device pin mechanism ............................................................................................ 2-25
Figure 2-13 Software mechanism ............................................................................................... 2-26
Figure 2-14 Asynchronous read ................................................................................................. 2-29
Figure 2-15 Asynchronous read in multiplexed-mode ................................................................ 2-29
Figure 2-16 Asynchronous write ................................................................................................. 2-30
Figure 2-17 Asynchronous write in multiplexed-mode ................................................................ 2-31
Figure 2-18 Page read ................................................................................................................ 2-32
Figure 2-19 Synchronous burst read .......................................................................................... 2-33

List of Figures
viii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Figure 2-20 Synchronous burst read in multiplexed-mode ........................................................ 2-34
Figure 2-21 Synchronous burst write ......................................................................................... 2-35
Figure 2-22 Synchronous burst write in multiplexed-mode ........................................................ 2-36
Figure 2-23 Synchronous read and asynchronous write ............................................................ 2-38
Figure 3-1 SMC register map ..................................................................................................... 3-2
Figure 3-2 SMC configuration register map ............................................................................... 3-3
Figure 3-3 SMC chip configuration register map ........................................................................ 3-3
Figure 3-4 SMC user configuration register map ....................................................................... 3-4
Figure 3-5 SMC peripheral and PrimeCell identification configuration register map .................. 3-4
Figure 3-6 smc_memc_status Register bit assignments ........................................................... 3-6
Figure 3-7 smc_memif_cfg Register bit assignments ................................................................ 3-7
Figure 3-8 smc_memc_cfg_set Register bit assignments ......................................................... 3-8
Figure 3-9 smc_memc_cfg_clr Register bit assignments .......................................................... 3-9
Figure 3-10 smc_direct_cmd Register bit assignments ............................................................. 3-10
Figure 3-11 smc_set_cycles Register bit assignments .............................................................. 3-11
Figure 3-12 smc_set_opmode Register bit assignments ........................................................... 3-12
Figure 3-13 smc_refresh_period_0 Register bit assignments .................................................... 3-15
Figure 3-14 smc_sram_cycles Register bit assignments ........................................................... 3-15
Figure 3-15 smc_opmode Register bit assignments .................................................................. 3-16
Figure 3-16 smc_user_status Register bit assignments ............................................................ 3-18
Figure 3-17 smc_user_config Register bit assignments ............................................................ 3-19
Figure 3-18 smc_periph_id Register bit assignments ................................................................ 3-20
Figure 3-19 smc_pcell_id Register bit assignments ................................................................... 3-22
Figure 4-1 SMC integration test register map ............................................................................ 4-2
Figure 4-2 smc_int_cfg Register bit assignments ...................................................................... 4-2
Figure 4-3 smc_int_inputs Register bit assignments ................................................................. 4-3
Figure 4-4 smc_int_outputs Register bit assignments ............................................................... 4-4
Figure 5-1 SMC and memory initialization sheet 1 of 3 ............................................................. 5-3
Figure 5-2 SMC and memory initialization sheet 2 of 3 ............................................................. 5-4
Figure 5-3 SMC and memory initialization sheet 3 of 3 ............................................................. 5-5
Figure A-1 AHB MC PL241 grouping of signals ......................................................................... A-2

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. ix
Preface
This preface introduces the PrimeCell AHB SRAM/NOR Memory Controller (MC)
(PL241) Technical Reference Manual. It contains the following sections:
•About this manual on page x
•Feedback on page xiv.

Preface
xCopyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
About this manual
This is the Technical Reference Manual (TRM) for the PrimeCell AHB SRAM/NOR
Memory Controller.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This manual is written for system designers, system integrators, and verification
engineers who are designing a System-on-Chip (SoC) device that uses the AHB MC.
The manual describes the external functionality of the AHB MC.
Using this manual
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for a high-level view of the AHB MC and a description
of its features.
Chapter 2 Functional Overview
Read this chapter for a description of the major components of the AHB
MC and how they operate.
Chapter 3 Programmer’s Model
Read this chapter for a description of the AHB MC registers.
Chapter 4 Programmer’s Model for Test
Read this chapter for a description of the additional logic for integration
testing.
Chapter 5 Device Driver Requirements
Read this chapter for a description of device driver requirements for the
Static Memory Controller (SMC).

Preface
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xi
Appendix A Signal Descriptions
Read this appendix for a description of the AHB MC input and output
signals.
Glossary Read the Glossary for definitions of terms used in this manual.
Conventions
Conventions that this manual can use are described in:
•Typographical
•Timing diagrams on page xii
•Signals on page xii
•Numbering on page xiii.
Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
signal names. Also used for terms in descriptive lists, where
appropriate.
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
• The Opcode_2 value selects the register that is accessed.

Preface
xii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Note
Angle brackets can also enclose a permitted range of values. The
example, <0-3>, shows that in name extensions, only one of the
values 0, 1, 2, or 3 is valid.
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means HIGH for
active-HIGH signals and LOW for active-LOW signals.
Lower-case n Denotes an active-LOW signal.
Prefix A Denotes global Advanced eXtensible Interface (AXI) signals.
Prefix AR Denotes AXI read address channel signals.
Prefix AW Denotes AXI write address channel signals.
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Preface
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xiii
Prefix B Denotes AXI write response channel signals.
Prefix C Denotes AXI low-power interface signals.
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Prefix P Denotes Advanced Peripheral Bus (APB) signals.
Prefix R Denotes AXI read data channel signals.
Prefix W Denotes AXI write data channel signals.
Numbering
The Verilog numbering convention is:
<size in bits>'<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
• 'h7B4 is an unsized hexadecimal value.
• 'o7654 is an unsized octal value.
• 8'd9 is an eight-bit wide decimal value of 9.
• 8'h3F is an eight-bit wide hexadecimal value of
0x3F . This is
equivalent to b00111111.
• 8'b1111 is an eight-bit wide binary value of b00001111.
Further reading
This section lists publications by ARM Limited, and by third parties.
ARM Limited periodically provides updates and corrections to its documentation. See
http://www.arm.com for current errata sheets, addenda, and the Frequently Asked
Questions list.
ARM publications
This manual contains information that is specific to the AHB MC. See the following
documents for other relevant information:
•PrimeCell AHB SRAM/NOR Memory Controller (PL241) Integration Manual
(ARM DII 0151)
•PrimeCell AHB SRAM/NOR Memory Controller (PL241) Implementation Guide
(ARM DDI 0144)
•AMBA™Specification (Rev 2.0) (ARM IHI 0011)
•AMBA 3 APB Protocol v1.0 Specification (ARM IHI 0024).

Preface
xiv Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
Feedback
ARM Limited welcomes feedback on the AHB MC and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier
giving:
• the product name
• a concise explanation of your comments.
Feedback on this manual
If you have any comments on this manual, send email to
[email protected] giving:
• the title
• the number
• the relevant page number(s) to which your comments apply
• a concise explanation of your comments.
ARM Limited also welcomes general suggestions for additions and improvements.

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-1
Chapter 1
Introduction
This chapter introduces the AHB MC. It contains the following sections:
•About the AHB MC on page 1-2
•Supported devices on page 1-5.

Introduction
1-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
1.1 About the AHB MC
The AHB MC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
System-on-Chip (SoC) peripheral. It is developed, tested, and licensed by ARM
Limited.
The AHB MC takes advantage of the newly developed Static Memory Controller
(SMC). The AHB MC has an AHB port with access to the external memory. The AHB
port has a bridge interface to the memory controller. There is a separate AHB port to
configure the memory controller. Specific configurations of the SMC are instantiated to
target specific memory devices. Figure 1-1 shows the AHB MC (PL241) configuration.
Figure 1-1 AHB MC (PL241) configuration
This section describes:
•AHB interface on page 1-3
•AHB to APB bridge on page 1-3
•SMC on page 1-4
•Clock domains on page 1-4
•Low-power interfaces on page 1-4.
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Introduction
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-3
1.1.1 AHB interface
The interface converts the incoming AHB transfers to the protocol used internally by
the AHB MC.
The interface has the following features:
• all AHB fixed length burst types are directly translated to fixed length bursts
• all undefined length INCR bursts are converted to INCR4 bursts
• broken bursts are supported
• the bufferable bit of the HPROT signal determines if the interface must wait for
a write transfer to complete internally
•aRead After Write (RAW) hazard detection buffer avoids RAW hazards
• AHB response signals are registered to improve timing
• locked transfers are supported within a 512MB region
•HWDATA is registered to improve internal timing paths
• a big-endian 32-bit mode option is implemented
• AHB error response logic is removed as no internal components generate errors.
This interface is a fully validated component. This ensures that it obeys both the AHB
protocol and the internal protocol that the interconnect uses.
See Chapter 2 Functional Overview for more information.
1.1.2 AHB to APB bridge
This bridge converts AHB transfers from the configuration port to the APB transfers
that the internal memory controllers require.
See Chapter 2 Functional Overview for more information.

Introduction
1-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
1.1.3 SMC
The SMC is a high-performance, area-optimized SRAM memory controller.
The SMC is pre-configured and validated for:
• the SRAM memory type
• the number of SRAM memory devices
• the maximum SRAM memory width.
The SRAM memory interface type is defined as supporting:
• synchronous or asynchronous SRAM
•Pseudo Static Random Access Memory (PSRAM)
• NOR flash
• NAND flash devices with an SRAM interface.
The SMC block offers the following features:
• it is configured to support the maximum SRAM memory data width of 32-bit
• programmable cycle timings, and memory width per chip select
• atomic switching of memory device and controller operating modes
• support for the PL220 External Bus Interface (EBI) PrimeCell, enabling sharing
of external address and data bus pins between memory controller interfaces
• support for a low-power interface
• support for a remap signal
• support for clock domains to be synchronous or asynchronous
See Chapter 2 Functional Overview for more information.
1.1.4 Clock domains
The memory controller has two clock domains:
• AHB clock domain
• static memory clock domain.
See Chapter 2 Functional Overview for more information.
1.1.5 Low-power interfaces
The memory controller has two low-power interfaces, one for each clock domain.
See Chapter 2 Functional Overview for more information.

Introduction
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-5
1.2 Supported devices
The SMC supports SRAM/NOR, see SMC on page 1-4. The Release Note provides a
specific list of memory devices tested with each configuration.
Some memory devices or series of memory devices have specific requirements:
Intel W18 series NOR FLASH, for example 28f128W18td
These devices, when in synchronous operation, use a WA I T pin.
However non-array operations when in synchronous mode do not use the
WA I T pin and it is always asserted. The controller cannot differentiate
between array and non-array accesses and therefore cannot support these
non-array accesses.
Therefore, W18 devices can only carry out non-array operations such as
Read Status in asynchronous modes of operation.
Cellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb_701_1us
You can program these devices using a CRE pin or by software access.
Whenever you program these devices through software access, using a
sequence of two reads followed by two writes, ensure that the third
access, that is, the first write is a
CE# controlled write.
SMC only does
WE# controlled writes. This is to simplify the design of the
SMC by having fewer timing registers and simpler timing controls.
Therefore, you can only program these devices by using the CRE pin
method of access.
Note
Because the memory controller maps INCR transfers into INCR4 transfers, it does not
support memory mapped FIFO components.

Introduction
1-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B