ARM PL310 Product manual

Copyright © 2007, 2008 ARM Limited. All rights reserved.
ARM DDI 0402B
PrimeCell Level 2 MBIST Controller
(PL310)
Revision: r1p0
Technical Reference Manual

ii Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Copyright © 2007, 2008 ARM Limited. All rights reserved.
Release Information
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Confidentiality Change
30 November 2007 A Non-Confidential First release for r0p0
04 April 2008 B Non-Confidential First release for r1p0

ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. iii
Contents
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Preface
About this manual .......................................................................................... x
Feedback ..................................................................................................... xiv
Chapter 1 Introduction
1.1 About the MBIST controller ......................................................................... 1-2
1.2 MBIST controller interface ........................................................................... 1-3
1.3 Product revisions ........................................................................................ 1-7
Chapter 2 Functional Description
2.1 Functional overview .................................................................................... 2-2
2.2 Functional operation ................................................................................. 2-13
Chapter 3 MBIST Instruction Register
3.1 About the MBIST Instruction Register ......................................................... 3-2
3.2 Field descriptions ........................................................................................ 3-4
Appendix A Signal Descriptions
A.1 MBIST controller interface signals .............................................................. A-2
A.2 Miscellaneous signals ................................................................................. A-4

Contents
iv Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B

ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. v
List of Tables
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Cache controller MBIST interface signals ................................................................. 1-5
Table 2-1 Cache controller compiled RAM latency ................................................................... 2-4
Table 2-2 MBISTADDR and MBISTDIN mapping for data RAM, 8-way ................................... 2-5
Table 2-3 MBISTADDR and MBISTDIN mapping for data RAM, 16-way ................................. 2-6
Table 2-4 Writes for data RAM testing ...................................................................................... 2-7
Table 2-5 MBISTADDR and MBISTDIN mapping for tag RAM, 8-way ..................................... 2-8
Table 2-6 MBISTADDR and MBISTDIN mapping for tag RAM, 16-way ................................... 2-8
Table 2-7 MBISTTX signals .................................................................................................... 2-10
Table 2-8 MBISTRX signals .................................................................................................... 2-11
Table 2-9 MBIST controller top level I/O ................................................................................. 2-11
Table 2-10 Data log format ........................................................................................................ 2-15
Table 3-1 Pattern field encoding ............................................................................................... 3-4
Table 3-2 Go/No-Go test pattern ............................................................................................... 3-6
Table 3-3 Control field encoding ............................................................................................... 3-7
Table 3-4 Read latency field encoding ...................................................................................... 3-8
Table 3-5 Write latency field encoding ...................................................................................... 3-8
Table 3-6 Y-address field encoding ......................................................................................... 3-12
Table 3-7 X-address field encoding ......................................................................................... 3-12
Table 3-8 Required sums of X-address and Y-address fields for data RAM ........................... 3-13
Table 3-9 Required sums of X-address and Y-address fields for tag RAM ............................. 3-14

List of Tables
vi Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
Table 3-10 Enables field encoding ............................................................................................ 3-15
Table 3-11 Column width field encoding ................................................................................... 3-16
Table 3-12 Cache size field encoding ....................................................................................... 3-16
Table 3-13 Way size field encoding .......................................................................................... 3-17
Table A-1 MBIST controller interface signals ............................................................................ A-2
Table A-2 Miscellaneous signals ............................................................................................... A-4

ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. vii
List of Figures
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Key to timing diagram conventions ............................................................................. xii
Figure 1-1 Cache controller MBIST configuration ...................................................................... 1-2
Figure 1-2 MBIST controller wiring diagram ............................................................................... 1-3
Figure 1-3 Traditional method of interfacing MBIST ................................................................... 1-4
Figure 1-4 Cache controller MBIST interface ............................................................................. 1-5
Figure 2-1 Cache controller MBIST and RAM interfaces ........................................................... 2-3
Figure 2-2 Cache controller compiled RAM latency ................................................................... 2-5
Figure 2-3 Cache controller MBIST paths for data RAM testing ................................................ 2-7
Figure 2-4 Cache controller MBIST paths for tag RAM testing .................................................. 2-9
Figure 2-5 MBIST controller block ............................................................................................ 2-10
Figure 2-6 Loading the MBIST controller instruction ................................................................ 2-13
Figure 2-7 Starting the MBIST test ........................................................................................... 2-14
Figure 2-8 Detecting an MBIST failure ..................................................................................... 2-14
Figure 2-9 Start of data log retrieval ......................................................................................... 2-15
Figure 2-10 End of data log retrieval .......................................................................................... 2-15
Figure 2-11 Start of bitmap data log retrieval ............................................................................. 2-16
Figure 2-12 End of bitmap data log retrieval .............................................................................. 2-16
Figure 3-1 MBIST Instruction Register ....................................................................................... 3-2
Figure 3-2 Example data RAM topology ................................................................................... 3-10
Figure 3-3 MBIST address scrambling ..................................................................................... 3-11

List of Figures
viii Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B

ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. ix
Preface
This preface introduces the PrimeCell Level 2 MBIST Controller (PL310) Revision r1p0
Technical Reference Manual. It contains the following sections:
•About this manual on page x
•Feedback on page xiv.

Preface
xCopyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
About this manual
This is the Technical Reference Manual (TRM) for the PrimeCell Level 2 MBIST
Controller (PL310). In this manual the generic term MBIST controller means the
PrimeCell Level 2 MBIST Controller, and cache controller means the PrimeCell Level
2 Cache Controller.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This manual is written for hardware engineers who are familiar with ARM technology
and want to use the MBIST controller to test the RAM blocks used by the cache
controller. The AXI protocol is not specified but some familiarity with AXI is assumed.
Using this manual
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to MBIST technology.
Chapter 2 Functional Description
Read this chapter for a description of the cache controller interface to the
MBIST controller and MBIST testing of the data RAM and tag RAMs.
Also read this chapter for a description of the timing sequences for
loading MBIST instructions, starting the MBIST test, detecting failures,
and retrieving the data log.
Chapter 3 MBIST Instruction Register
Read this chapter for a description on how to use the MBIST Instruction
Register to configure the mode of operation of the MBIST engine.
Appendix A Signal Descriptions
Read this appendix for a description of the MBIST controller input and
output signals.