ARM PL310 Product manual
Copyright © 2007, 2008 ARM Limited. All rights reserved.
ARM DDI 0402B
PrimeCell Level 2 MBIST Controller
(PL310)
Revision: r1p0
Technical Reference Manual
ii Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Copyright © 2007, 2008 ARM Limited. All rights reserved.
Release Information
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Confidentiality Change
30 November 2007 A Non-Confidential First release for r0p0
04 April 2008 B Non-Confidential First release for r1p0
ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. iii
Contents
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Preface
About this manual .......................................................................................... x
Feedback ..................................................................................................... xiv
Chapter 1 Introduction
1.1 About the MBIST controller ......................................................................... 1-2
1.2 MBIST controller interface ........................................................................... 1-3
1.3 Product revisions ........................................................................................ 1-7
Chapter 2 Functional Description
2.1 Functional overview .................................................................................... 2-2
2.2 Functional operation ................................................................................. 2-13
Chapter 3 MBIST Instruction Register
3.1 About the MBIST Instruction Register ......................................................... 3-2
3.2 Field descriptions ........................................................................................ 3-4
Appendix A Signal Descriptions
A.1 MBIST controller interface signals .............................................................. A-2
A.2 Miscellaneous signals ................................................................................. A-4
Contents
iv Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. v
List of Tables
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Cache controller MBIST interface signals ................................................................. 1-5
Table 2-1 Cache controller compiled RAM latency ................................................................... 2-4
Table 2-2 MBISTADDR and MBISTDIN mapping for data RAM, 8-way ................................... 2-5
Table 2-3 MBISTADDR and MBISTDIN mapping for data RAM, 16-way ................................. 2-6
Table 2-4 Writes for data RAM testing ...................................................................................... 2-7
Table 2-5 MBISTADDR and MBISTDIN mapping for tag RAM, 8-way ..................................... 2-8
Table 2-6 MBISTADDR and MBISTDIN mapping for tag RAM, 16-way ................................... 2-8
Table 2-7 MBISTTX signals .................................................................................................... 2-10
Table 2-8 MBISTRX signals .................................................................................................... 2-11
Table 2-9 MBIST controller top level I/O ................................................................................. 2-11
Table 2-10 Data log format ........................................................................................................ 2-15
Table 3-1 Pattern field encoding ............................................................................................... 3-4
Table 3-2 Go/No-Go test pattern ............................................................................................... 3-6
Table 3-3 Control field encoding ............................................................................................... 3-7
Table 3-4 Read latency field encoding ...................................................................................... 3-8
Table 3-5 Write latency field encoding ...................................................................................... 3-8
Table 3-6 Y-address field encoding ......................................................................................... 3-12
Table 3-7 X-address field encoding ......................................................................................... 3-12
Table 3-8 Required sums of X-address and Y-address fields for data RAM ........................... 3-13
Table 3-9 Required sums of X-address and Y-address fields for tag RAM ............................. 3-14
List of Tables
vi Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
Table 3-10 Enables field encoding ............................................................................................ 3-15
Table 3-11 Column width field encoding ................................................................................... 3-16
Table 3-12 Cache size field encoding ....................................................................................... 3-16
Table 3-13 Way size field encoding .......................................................................................... 3-17
Table A-1 MBIST controller interface signals ............................................................................ A-2
Table A-2 Miscellaneous signals ............................................................................................... A-4
ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. vii
List of Figures
PrimeCell Level 2 MBIST Controller (PL310)
Technical Reference Manual
Key to timing diagram conventions ............................................................................. xii
Figure 1-1 Cache controller MBIST configuration ...................................................................... 1-2
Figure 1-2 MBIST controller wiring diagram ............................................................................... 1-3
Figure 1-3 Traditional method of interfacing MBIST ................................................................... 1-4
Figure 1-4 Cache controller MBIST interface ............................................................................. 1-5
Figure 2-1 Cache controller MBIST and RAM interfaces ........................................................... 2-3
Figure 2-2 Cache controller compiled RAM latency ................................................................... 2-5
Figure 2-3 Cache controller MBIST paths for data RAM testing ................................................ 2-7
Figure 2-4 Cache controller MBIST paths for tag RAM testing .................................................. 2-9
Figure 2-5 MBIST controller block ............................................................................................ 2-10
Figure 2-6 Loading the MBIST controller instruction ................................................................ 2-13
Figure 2-7 Starting the MBIST test ........................................................................................... 2-14
Figure 2-8 Detecting an MBIST failure ..................................................................................... 2-14
Figure 2-9 Start of data log retrieval ......................................................................................... 2-15
Figure 2-10 End of data log retrieval .......................................................................................... 2-15
Figure 2-11 Start of bitmap data log retrieval ............................................................................. 2-16
Figure 2-12 End of bitmap data log retrieval .............................................................................. 2-16
Figure 3-1 MBIST Instruction Register ....................................................................................... 3-2
Figure 3-2 Example data RAM topology ................................................................................... 3-10
Figure 3-3 MBIST address scrambling ..................................................................................... 3-11
List of Figures
viii Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
Preface
xCopyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
About this manual
This is the Technical Reference Manual (TRM) for the PrimeCell Level 2 MBIST
Controller (PL310). In this manual the generic term MBIST controller means the
PrimeCell Level 2 MBIST Controller, and cache controller means the PrimeCell Level
2 Cache Controller.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This manual is written for hardware engineers who are familiar with ARM technology
and want to use the MBIST controller to test the RAM blocks used by the cache
controller. The AXI protocol is not specified but some familiarity with AXI is assumed.
Using this manual
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to MBIST technology.
Chapter 2 Functional Description
Read this chapter for a description of the cache controller interface to the
MBIST controller and MBIST testing of the data RAM and tag RAMs.
Also read this chapter for a description of the timing sequences for
loading MBIST instructions, starting the MBIST test, detecting failures,
and retrieving the data log.
Chapter 3 MBIST Instruction Register
Read this chapter for a description on how to use the MBIST Instruction
Register to configure the mode of operation of the MBIST engine.
Appendix A Signal Descriptions
Read this appendix for a description of the MBIST controller input and
output signals.
Preface
ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. xi
Conventions
Conventions that this manual can use are described in:
•Typographical
•Timing diagrams
•Signals on page xii
•Numbering on page xiii.
Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
ARM processor signal names. Also used for terms in descriptive
lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace
Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace
italic
Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace
bold
Denotes language keywords when used outside example code.
< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
• The Opcode_2 value selects which register is accessed.
Timing diagrams
The figure named Key to timing diagram conventions on page xii explains the
components used in timing diagrams. Variations, when they occur, have clear labels.
You must not assume any timing information that is not explicit in the diagrams.
Preface
xii Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals
• LOW for active-LOW signals.
Lower-case n At the start or end of a signal name denotes an active-LOW signal.
Prefix A Denotes global Advanced eXtensible Interface (AXI) signals.
Prefix AR Denotes AXI read address channel signals.
Prefix AW Denotes AXI write address channel signals.
Prefix B Denotes AXI write response channel signals.
Prefix C Denotes AXI low-power interface signals.
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Prefix P Denotes Advanced Peripheral Bus (APB) signals.
Prefix R Denotes AXI read data channel signals.
Prefix W Denotes AXI write data channel signals.
&ORFN
+,*+WR/2:
7UDQVLHQW
+,*+/2:WR+,*+
%XVVWDEOH
%XVWRKLJKLPSHGDQFH
%XVFKDQJH
+LJKLPSHGDQFHWRVWDEOHEXV
Preface
ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. xiii
Numbering
The numbering convention is:
<size in bits>'<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
• 'h7B4 is an unsized hexadecimal value.
• 'o7654 is an unsized octal value.
• 8'd9 is an eight-bit wide decimal value of 9.
• 8'h3F is an eight-bit wide hexadecimal value of
0x3F
. This is
equivalent to b00111111.
• 8'b1111 is an eight-bit wide binary value of b00001111.
Additional reading
This section lists publications by ARM and by third parties.
See
http://infocenter.arm.com/help/index.jsp
for access to ARM documentation.
ARM publications
This manual contains information that is specific to the MBIST controller. See the
following documents for other relevant information:
•AMBA AXI Protocol Specification (ARM IHI 0022)
•ARM Architecture Reference Manual (ARM DDI 0406)
•ARM PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual
(ARM DDI 0246)
•ARM PrimeCell Level 2 Cache Controller (PL310) Implementation Guide
(ARM DII 0045).
Preface
xiv Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
Feedback
ARM welcomes feedback on the MBIST controller and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier
giving:
• the product name
• a concise explanation of your comments.
Feedback on this manual
If you have any comments on this manual, send email to
giving:
• the title
• the number
• the relevant page number(s) to which your comments apply
• a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
Introduction
1-2 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
1.1 About the MBIST controller
MBIST is the industry-standard method of testing embedded memories. MBIST works
by performing sequences of reads and writes to the memory according to a test
algorithm. Many industry-standard test algorithms exist.
An MBIST controller generates the correct sequence of reads and writes to all locations
of the RAM to ensure that the cells are operating correctly. In doing this, some
additional test coverage is achieved in the address and data paths that the MBIST uses.
You must only use the MBIST controller with the cache controller to perform memory
testing of the Level 2 (L2) cache RAM.
Note
The example integration files provided with the MBIST controller only support a
16-way cache design.
MBIST mode takes priority over all other modes, for example SCAN, in that the L2
RAMs are only accessible to the MBIST controller when MBIST mode is activated with
the MTESTON pin. You must keep the MTESTON signal LOW during functional
mode, and the AXI interfaces LOW during MBIST mode.
The MBIST controller controls the MBIST testing of the L2 RAMs through the MBIST
port of the cache controller. Figure 1-1 shows the cache controller MBIST
configuration.
When MTESTON is HIGH, the MBIST block, the cache controller, and the RAMs
must be clocked at the same frequency.
Figure 1-1 Cache controller MBIST configuration
7DJ5$0V
&DFKH
FRQWUROOHU
0%,67EORFN
'LVSDWFK
XQLW
0%,67
FRQWUROOHU
'DWDSDULW\5$0
'DWD5$0
Introduction
ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 1-3
1.2 MBIST controller interface
Figure 1-2 shows the MBIST controller interface to the Automated Test Equipment
(ATE) and to the MBIST interface of the cache controller.
Figure 1-2 MBIST controller wiring diagram
Figure 1-3 on page 1-4 shows the traditional method of accessing a cache RAM for
MBIST.
0%,67'$7$,1
0%,675(6(71
07(6721
0%,67'6+,)7
0%,67581
0%,676+,)7
0%,675(68/7>@
Q5(6(7
&/. &/.
0%,67'287>@
0%,67'&7/>@
0%,675(6(71
07(6721
0%,67'6+,)7
0%,67581
0%,676+,)7
0%,67'$7$,1
0%,675(68/7>@
0%,67&(>@
0%,67:(>@
0%,67$''5>@
0%,67',1>@
0%,67&(>@
0%,67:(>@
0%,67$''5>@
0%,67',1>@
07(6721
0%,67'&7/>@
0%,67'287>@
&/.
Q5(6(7
$XWRPDWHGWHVW
HTXLSPHQW
0%,67FRQWUROOHU &DFKHFRQWUROOHU
Introduction
1-4 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
Figure 1-3 Traditional method of interfacing MBIST
Because this method significantly reduces the maximum operating frequency, it is not
suitable for high-performance designs. Instead, the MBIST controller uses an additional
input to the existing functional multiplexors without reducing maximum operating
frequency.
Figure 1-4 on page 1-5 shows the five pipeline stages used to access the cache RAM
arrays.
'DWD,Q
%LVW'DWD,Q
$GGUHVV
%LVW$GGUHVV
&(
%LVW&(
:(
%LVW:(
%LVW0RGH
5$0 'DWD2XW
%LVW'DWD2XW
Introduction
ARM DDI 0402B Copyright © 2007, 2008 ARM Limited. All rights reserved. 1-5
Figure 1-4 Cache controller MBIST interface
The MBIST controller accesses memory through the MBIST interface of the cache
controller. Table 1-1 lists the cache controller MBIST interface signals.
0%,67$''5>@
0%,67',1>@
0%,67&(>[@
0%,67:(>@
07(6721
0%,67'&7/>@
)URP
GDWD
SDWKV
)URP
DGGUHVV
SDWKV
)URP
FKLS
HQDEOHV
)URP
ZULWH
HQDEOHV '4
'4
'4
'4
'4
'4
'4
'4
'4
'4
'4
)URPRWKHU
5$0EORFNV
0%,67'287>@
)XQFWLRQDO
RXWSXW
'4
5$0
EORFN
Table 1-1 Cache controller MBIST interface signals
Name Type Description
nRESET Input Global active LOW reset signal.
CLK Input Active HIGH clock signal. This clock drives the cache controller logic.
MBISTDOUT[63:0] Output Data out bus from all cache RAM blocks.
Introduction
1-6 Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B
Note
The interface of the MBIST controller communicates with both the ATE and the MBIST
interface of the cache controller. See Appendix A Signal Descriptions for descriptions
of the MBIST controller interface signals. See the ARM PrimeCell Level 2 Cache
Controller (PL310) Technical Reference Manual for more information about the
MBIST interface.
MBISTDCTL[19:0] Input Delayed versions of the MBISTCE[17:0] signal and the doubleword select signal,
MBISTADDR[1:0]. Selects the correct read data after it passes through the MBIST
pipeline stages.
MBISTDCTL[19:0] = delayed {MBISTCE[17:0],MBISTADDR[1:0]}.
MTESTON Input Select signal for cache RAM array. This signal is the select input to the multiplexors
that access the cache RAM arrays for test. When asserted, MTESTON takes priority
over all other select inputs to the multiplexors.
MBISTCE[17:0] Input One-hot chip enables to select cache RAM arrays for test.
MBISTWE[31:0] Input Global write enable signal for all RAM arrays.
MBISTADDR[19:0] Input Address signal for cache RAM array. MBISTADDR[1:0] is the doubleword select
value. See Y-address and X-address fields, MBIR[36:33] and MBIR[40:37] on
page 3-9 for a description of the doubleword select. Not all RAM arrays use the full
address width.
MBISTDIN[63:0] Input Data bus to the cache RAM arrays. Not all RAM arrays use the full data width.
Table 1-1 Cache controller MBIST interface signals (continued)
Name Type Description
Table of contents
Other ARM Controllers manuals
Popular Controllers manuals by other brands
Delta Electronics
Delta Electronics AH500 manual
Hubbell
Hubbell Euclid Lifting Magnet Controller 4296 Specifications
Watts
Watts Tekmar WiFi Snow Melting Control 670 installation manual
Adaptec
Adaptec RAID 5805Z Installation and user guide
ATWELL
ATWELL VG OSG Operation and installation manual
Samson
Samson 46-7 Mounting and operating instructions
