ARM L2C-310 Product manual

Copyright © 2007-2010 ARM. All rights reserved.
ARM DDI 0402F (ID011711)
CoreLink™Level 2 MBIST Controller
L2C-310
Revision: r3p2
Technical Reference Manual

ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ii
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CoreLink Level 2 MBIST Controller L2C-310
Technical Reference Manual
Copyright © 2007-2010 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
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Words and logos marked with ®or ™are registered trademarks or trademarks of ARM®in the EU and other countries,
except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Confidentiality Change
30 November 2007 A Non-Confidential First release for r0p0
04 April 2008 B Non-Confidential First release for r1p0
19 December 2008 C Non-Confidential Unrestricted Access First release for r2p0
01 October 2009 D Non-Confidential Unrestricted Access First release for r3p0
03 February 2010 E Non-Confidential Unrestricted Access First release for r3p1
10 December 2010 F Non-Confidential Unrestricted Access First release for r3p2

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Contents
CoreLink Level 2 MBIST Controller L2C-310
Technical Reference Manual
Preface
About this book ............................................................................................................ v
Feedback .................................................................................................................. viii
Chapter 1 Introduction
1.1 About the MBIST controller ...................................................................................... 1-2
1.2 MBIST controller interface ....................................................................................... 1-3
1.3 RTL configuration .................................................................................................... 1-6
1.4 Product revisions ..................................................................................................... 1-7
Chapter 2 Functional Description
2.1 Functional overview ................................................................................................. 2-2
2.2 Functional operation .............................................................................................. 2-11
Chapter 3 MBIST Instruction Register
3.1 About the MBIST Instruction Register ..................................................................... 3-2
3.2 Field descriptions ..................................................................................................... 3-3
Appendix A Signal Descriptions
A.1 MBIST controller interface signals ........................................................................... A-2
A.2 Miscellaneous signals .............................................................................................. A-4
Appendix B Revisions
Glossary

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Preface
This preface introduces the CoreLink Level 2 MBIST Controller L2C-310 Technical Reference
Manual. It contains the following sections:
•About this book on page v
•Feedback on page viii.

Preface
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About this book
This book is for Technical Reference Manual (TRM) for the CoreLink Level 2 MBIST
Controller L2C-310. In this manual the generic term MBIST controller means the CoreLink
Level 2 MBIST Controller, and cache controller means the CoreLink Level 2 Cache Controller.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this book, where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This book is written for hardware engineers who are familiar with ARM technology and want
to use the MBIST controller to test the RAM blocks used by the cache controller. The AXI
protocol is not specified but some familiarity with AXI is assumed.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to MBIST technology.
Chapter 2 Functional Description
Read this for a description of the cache controller interface to the MBIST
controller and MBIST testing of the data RAM and tag RAMs. Also read this
chapter for a description of the timing sequences for loading MBIST instructions,
starting the MBIST test, detecting failures, and retrieving the data log.
Chapter 3 MBIST Instruction Register
Read this for a description on how to use the MBIST Instruction Register to
configure the mode of operation of the MBIST engine.
Appendix A Signal Descriptions
Read this for a description of the MBIST controller input and output signals.
Appendix B Revisions
Read this for a description of the technical changes between released issues of this
book.
Glossary Read this for definitions of terms used in this book.
Conventions
Conventions that this book can use are described in:
•Typographical on page vi
•Timing diagrams on page vi
•Signals on page vii.

Preface
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Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology, denotes
internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as commands, file
and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You can enter
the underlined text instead of the full command or option name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
< and > Enclose replaceable terms for assembler syntax where they appear in code
or code fragments. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in timing
diagrams. Variations, when they occur, have clear labels. You must not assume any timing
information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does not affect normal operation.
Key to timing diagram conventions
Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and
they look similar to the bus change shown in Key to timing diagram conventions. If a timing
diagram shows a single-bit signal in this way then its value does not affect the accompanying
description.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

Preface
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Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals
• LOW for active-LOW signals.
Lower-case n At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This section lists publications by ARM and by third parties.
See Infocenter,
http://infocenter.arm.com , for access to ARM documentation.
ARM publications
This book contains information that is specific to this product. See the following documents for
other relevant information:
•AMBA AXI Protocol Specification (ARM IHI 0022)
•ARM Architecture Reference Manual (ARM DDI 0406)
•CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual (ARM DDI
0246)
•CoreLink Level 2 Cache Controller L2C-310 Implementation Guide (ARM DII 0045).

Preface
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Feedback
ARM welcomes feedback on this product and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and
diagnostic procedures if appropriate.
Feedback on content
If you have comments on content then send an e-mail to
[email protected] . Give:
• the title
• the number, ARM DDI 0402F
• the page numbers to which your comments apply
• a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.

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Chapter 1
Introduction
This chapter introduces the MBIST controller. It contains the following sections:
•About the MBIST controller on page 1-2
•MBIST controller interface on page 1-3
•Product revisions on page 1-7.

Introduction
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1.1 About the MBIST controller
MBIST is the industry-standard method of testing embedded memories. MBIST works by
performing sequences of reads and writes to the memory according to a test algorithm. Many
industry-standard test algorithms exist.
An MBIST controller generates the correct sequence of reads and writes to all locations of the
RAM to ensure that the cells are operating correctly. In doing this, some additional test coverage
is achieved in the address and data paths that the MBIST uses. You must only use the MBIST
controller with the cache controller to perform memory testing of the Level 2 (L2) cache RAM.
Note
The example integration files provided with the MBIST controller only support a 16-way cache
design.
MBIST mode takes priority over all other modes, for example scan testing, in that the L2 RAMs
are only accessible to the MBIST controller when MBIST mode is activated with the
MTESTON pin. You must keep the MTESTON signal LOW during functional mode, and the
AXI interfaces LOW during MBIST mode.
The MBIST controller controls the MBIST testing of the L2 RAMs through the MBIST port of
the cache controller. Figure 1-1 shows the cache controller MBIST configuration.
When MTESTON is HIGH, the MBIST block, the cache controller, and the RAMs must be
clocked at the same frequency.
Figure 1-1 Cache controller MBIST configuration without data banking
Tag RAMs (16)
Cache
controller
MBIST block
Dispatch
unit
MBIST
controller
Data parity RAM (1)
Data RAM (1)

Introduction
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1.2 MBIST controller interface
Figure 1-2 shows the MBIST controller interface to the Automated Test Equipment (ATE) and
to the MBIST interface of the cache controller.
Figure 1-2 MBIST controller wiring diagram
Figure 1-3 shows the traditional method of accessing a cache RAM for MBIST.
Figure 1-3 Traditional method of interfacing MBIST
Because this method significantly reduces the maximum operating frequency, it is not suitable
for high-performance designs. Instead, the MBIST controller uses an additional input to the
existing functional multiplexors without reducing maximum operating frequency.
Figure 1-4 on page 1-4 shows the five pipeline stages used to access the cache RAM arrays.
MBISTDATAIN
MBISTRESETN
MTESTON
MBISTDSHIFT
MBISTRUN
MBISTSHIFT
MBISTRESULT[2:0]
nRESET
CLK CLK
MBISTDOUT[63:0]
MBISTDCTL[19:0]
MBISTRESETN
MTESTON
MBISTDSHIFT
MBISTRUN
MBISTSHIFT
MBISTDATAIN
MBISTRESULT[2:0]
MBISTCE[17:0]
MBISTWE[31:0]
MBISTADDR[19:0]
MBISTDIN[63:0]
MBISTCE[17:0]
MBISTWE[31:0]
MBISTADDR[19:0]
MBISTDIN[63:0]
MTESTON
MBISTDCTL[19:0]
MBISTDOUT[63:0]
CLK
nRESET
Automated test
equipment
MBIST controller Cache controller
DataIn
BistDataIn
0
1
0
1
Address
BistAddress
0
1
CE
BistCE
0
1
WE
BistWE
BistMode
RAM DataOut
BistDataOut

Introduction
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Figure 1-4 Cache controller MBIST interface
The MBIST controller accesses memory through the MBIST interface of the cache controller.
Table 1-1 lists the cache controller MBIST interface signals.
MBISTADDR[19:0]
MBISTDIN[63:0]
MBISTCE[x]
MBISTWE[31:0]
MTESTON
MBISTDCTL[19:0]
From
data
paths
From
address
paths
From
chip
enables
From
write
enables DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
From other
RAM blocks
MBISTDOUT[63:0]
Functional
output
DQ
RAM
block
Table 1-1 Cache controller MBIST interface signals
Name Type Description
nRESET Input Global active LOW reset signal.
CLK Input Active HIGH clock signal. This clock drives the cache controller logic.
MBISTDOUT[63:0] Output Data out bus from all cache RAM blocks.
MBISTDCTL[19:0] Input Delayed versions of the MBISTCE[17:0] signal and the doubleword select signal,
MBISTADDR[1:0]. Selects the correct read data after it passes through the MBIST pipeline stages.
MBISTDCTL[19:0] = delayed {MBISTCE[17:0],MBISTADDR[1:0]}.
MTESTON Input Select signal for cache RAM array. This signal is the select input to the multiplexors that access the
cache RAM arrays for test. When asserted, MTESTON takes priority over all other select inputs to
the multiplexors.
MBISTCE[17:0] Input One-hot chip enables to select cache RAM arrays for test.

Introduction
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Note
The interface of the MBIST controller communicates with both the ATE and the MBIST
interface of the cache controller. See Appendix A Signal Descriptions for descriptions of the
MBIST controller interface signals. See the CoreLink Level 2 Cache Controller L2C-310
Technical Reference Manual for more information about the MBIST interface.
MBISTWE[31:0] Input Global write enable signal for all RAM arrays.
MBISTADDR[19:0] Input Address signal for cache RAM array. MBISTADDR[1:0] is the doubleword select value. See
Y-address and X-address fields, MBIR[36:33] and MBIR[40:37] on page 3-7 for a description of
the doubleword select. Not all RAM arrays use the full address width.
MBISTDIN[63:0] Input Data bus to the cache RAM arrays. Not all RAM arrays use the full data width.
Table 1-1 Cache controller MBIST interface signals (continued)
Name Type Description

Introduction
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1.3 RTL configuration
L2C-310 MBIST supports, normal RAM organization, and banked RAM organization. The
default is set to normal RAM organization mode so that
•
bist_pl310_DATA_BANKING is commented in file
l
ogical/pl310/verilog_mbist/pl310MBDefs.v
•
pl310_DATA_BANKING is commented in file
logical/pl310/verilog/pl310_defs.v
If you want to use the banked RAM organization both of these 'defines have to be uncommented.
The banked RAM structure splits both the Data RAM and Data parity RAM into four arrays.
Two dedicated L2C-310 MBIST Yaddr bits select one of the four arrays.See Y-address and
X-address fields, MBIR[36:33] and MBIR[40:37] on page 3-7 for a description of the Yaddr
field.

Introduction
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1.4 Product revisions
This section summarizes the differences in functionality between releases of the MBIST
controller:
r0p0-r1p0 The difference between these revisions is additional latency cycles in MBIR. See
Read latency and write latency fields, MBIR[44:41] and MBIR[48:45] on
page 3-5
r1p0-r2p0 There is no functional difference between these two revisions.
r2p0-r3p0 Added support for data banking.
r3p0-r3p1 There is no functional difference between these two revisions.
r3p1-r3p2 There is no functional difference between these two revisions.

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Chapter 2
Functional Description
This chapter contains a functional overview and MBIST controller implementation. The functional
operation provides timing sequences for loading instructions, starting the MBIST engine, detecting
failures, and retrieving the data log. It contains the following sections:
•Functional overview on page 2-2
•Functional operation on page 2-11.

Functional Description
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2.1 Functional overview
This section describes:
•MBIST controller interface
•MBIST controller implementation on page 2-8.
Note
You must always reset the MBIST engine before you start any array test.
2.1.1 MBIST controller interface
The MBIST controller has one MBIST port, see Appendix A Signal Descriptions. Only one
RAM is accessed by the MBIST controller at any time.
The MBIST controller must be able to account for the different latencies of the RAMs. You can
configure RAM latencies for the cache controller RAMs. You can configure the Tag and Data
RAMs for the following latencies:
•setup
• read access
• write access.
See also Compiled RAM latencies on page 2-3.
You can use the MBIST controller for testing the cache controller compiled RAMs. You can also
choose to design your own MBIST controller. You can only access one RAM by the MBIST
port at a time.
Note
For the MBIST to run correctly on the cache controller:
• set the signals on the cache controller interface as follows:
—setASSOCIATIVITY to the relevant value for your design
—setDATAWAIT, DATAERR, TAGWAIT, and TAGERR to 0
— set the AXI ports to 0.
• set the signals on the CPU as follows:
— set all AXI valid bits to 0
—setCLK active
— disable all external request signals, for example Debug request
— set the following AXI clock enables to 0, INCLKENS0, OUTCLKENS0,
INCLKENS1, OUTCLKENS1, INCLKENM0, OUTCLKENM0,
INCLKENM1, and OUTCLKENM1.
Figure 2-1 on page 2-3 shows the interfaces between the MBIST controller and the RAMs that
MBIST tests.

Functional Description
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Figure 2-1 Cache controller MBIST and RAM interfaces
This section describes RAM latencies and the two MBIST RAM tests:
•Compiled RAM latencies
•MBIST testing of cache controller data RAM on page 2-4
•MBIST testing of cache controller tag RAMs on page 2-6.
Compiled RAM latencies
The cache controller resets assuming the slowest compiled RAMs are being used. This means
sixteen cache controller clock cycles are used for each access. In terms of reads, this means that
the read data is sampled eight clock edges after the edge on which the read request is sampled
by the RAM. Using this nomenclature, the shortest latency is one. During functional mode, the
latencies for each RAM are programmed in the cache controller Auxiliary Control Register.
For MBIST, you must know the latencies of the RAMs being tested. The MBIST controller
defaults to one cycle of latency, but must reprogram this during the instruction load before
MBIST testing can begin. The latency of the current RAM being tested is passed to the MBIST
controller in the MBIST instruction.
MBIST
controller
Cache
controller
Data parity
RAM (1)
(option)
Data RAM
(1)
Tag RAMs
(16)
MBISTADDR[19:0]
MBISTCE[17:0]
MBISTDCTL[19:0]
MBISTDIN[63:0]
MBISTDOUT[63:0]
DATAPRD[31:0]
DATAPWD[31:0]
DATAADDR[17:0]
DATAEN[31:0]
DATAnRW
DATACS
DATARD[255:0]
DATAWD[255:0]
DATAADDR[17:0]
DATAEN[31:0]
DATAnRW
DATACS
TAGRDx[20:0]
TAGPRD[15:0]
TAGADDR[13:0]
TAGWD[20:0]
TAGCS[15:0]
TAGnRW
TAGEN[20:0]
TAGPWD
MTESTON
TAGPEN
MBISTWE[31:0]
TAGLWD
TAGLEN
TAGLRD[15:0]

Functional Description
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Table 2-1 shows the cache controller compiled RAM latency.
Figure 2-2 shows the cache controller compiled RAM latency.
Figure 2-2 Cache controller compiled RAM latency
MBIST testing of cache controller data RAM
The cache controller data RAM is 256 bits wide, and the size of the MBISTDIN and
MBISTDOUT buses on the cache controller MBIST interface is 64 bits, so four reads and four
writes are required for each index of the data RAM. The cache controller handles this by using
the MBISTADDR[1:0] signal as a doubleword select for each index of the data RAM for
writes. For reads from a previous MBIST transaction you use the MBISTDCTL[1:0] signal.
You require separate pins because the MBIST transactions are pipelined. The MBIST controller
Table 2-1 Cache controller compiled RAM latency
Latency bits [3:0] Cycles of latency
4’b0000 1 cycle of latency. No additional latency. This is the default.
4’b0001 2 cycles of latency.
4’b0010 3 cycles of latency.
4’b0011 4 cycles of latency.
4’b0100 5 cycles of latency.
4’b0101 6 cycles of latency.
4’b0110 7 cycles of latency.
4’b0111 8 cycles of latency.
4’b1000 9 cycles of latency.
4’b1001 10 cycles of latency.
4’b1010 11 cycles of latency.
4’b1011 12 cycles of latency.
4’b1100 13 cycles of latency.
4’b1101 14 cycles of latency.
4’b1110 15 cycles of latency.
4’b1111 16 cycles of latency.
data
data
data
CLK
Chip select
Cache controller compiled RAM latency = 0000
Cache controller compiled RAM latency = 0001
Cache controller compiled RAM latency = 0010

Functional Description
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takes into account the data RAM latency and issues the correct control signals. Table 2-2 shows
the address range of the MBISTADDR bus used to test the data RAM, based on the L2 cache
size and configured to be 8-way.
For a 16-way cache, you can remove one bit from the lower address range and add it to the upper
address range as compared to an 8-way cache of the same size. Table 2-3 shows the address
range of the MBISTADDR bus used to test the data RAM, based on the L2 cache size and
configured to be 16-way.
The cache controller has a 256-bit wide Line Read Buffer (LRB) in each slave. One of these
holds data for MBIST testing. The cache controller always adds two register delays to the
MBIST data read path for the data RAM.
When using the MBIST controller you must account for the data RAM latency in the pipeline.
The latency can be from one to eight clock cycles. See Compiled RAM latencies on page 2-3.
The signal MBISTCE[0] is for the chip enable to the data RAM. The signal
MBISTDCTL[2:0] is for reads from previous MBIST transactions.
Figure 2-3 on page 2-6 shows the cache controller MBIST paths for data RAM testing.
Table 2-2 MBISTADDR and MBISTDIN mapping for data RAM, 8-way
L2
cache
size
Number of
data RAM
indexes
MBISTADDR to data RAM mapping MBISTDIN to data RAM mapping
128KB 4,096 DATAADDR[11:0]=MBISTADDR[18:16,10:2] DATAWD[63:0]=MBISTDIN[63:0]
256KB 8,192 DATAADDR[12:0]=MBISTADDR[18:16,11:2] DATAWD[63:0]=MBISTDIN[63:0]
512KB 16,384 DATAADDR[13:0]=MBISTADDR[18:16,12:2] DATAWD[63:0]=MBISTDIN[63:0]
1MB 32,768 DATAADDR[14:0]=MBISTADDR[18:16,13:2] DATAWD[63:0]=MBISTDIN[63:0]
2MB 65,536 DATAADDR[15:0]=MBISTADDR[18:16,14:2] DATAWD[63:0]=MBISTDIN[63:0]
4MB 131,072 DATAADDR[16:0]=MBISTADDR[18:2] DATAWD[63:0]=MBISTDIN[63:0]
Table 2-3 MBISTADDR and MBISTDIN mapping for data RAM, 16-way
L2
cache
size
Number of
data RAM
indexes
MBISTADDR to data RAM mapping MBISTDIN to data RAM mapping
256KB 8,192 DATAADDR[12:0]=MBISTADDR[19:16,10:2] DATAWD[63:0]=MBISTDIN[63:0]
512KB 16,384 DATAADDR[13:0]=MBISTADDR[19:16,11:2] DATAWD[63:0]=MBISTDIN[63:0]
1MB 32,768 DATAADDR[14:0]=MBISTADDR[19:16,12:2] DATAWD[63:0]=MBISTDIN[63:0]
2MB 65,536 DATAADDR[15:0]=MBISTADDR[19:16,13:2] DATAWD[63:0]=MBISTDIN[63:0]
4MB 131,072 DATAADDR[16:0]=MBISTADDR[19:16,14:2] DATAWD[63:0]=MBISTDIN[63:0]
8MB 262,144 DATAADDR[17:0]=MBISTADDR[19:2] DATAWD[63:0]=MBISTDIN[63:0]