ARM ARM11 Product manual
Copyright © 2003 ARM Limited. All rights reserved.
ARM DDI 0289B
ARM11 Memory Built-In Self Test
Controller
Technical Reference Manual
ii Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
ARM11 Memory Built-In Self Test Controller
Technical Reference Manual
Copyright © 2003 ARM Limited. All rights reserved.
Release Information
The table below shows the release state and change history of this document.
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks owned by ARM Limited, except
as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Confidentiality Status
This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
14 April 2003 A First release
28 April 2003 B Addition of ARM11 to product name
ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. iii
Contents
ARM11 Memory Built-In Self Test Controller
Technical Reference Manual
Preface
About this book .............................................................................................. x
Feedback ..................................................................................................... xiii
Chapter 1 Introduction
1.1 Overview ..................................................................................................... 1-2
1.2 MBIST ports ................................................................................................ 1-3
Chapter 2 Functional Description
2.1 Timing ......................................................................................................... 2-2
2.2 Bitmap mode ............................................................................................... 2-6
Chapter 3 ARM11 MBIST Controller Instruction Register
3.1 Instruction Register ..................................................................................... 3-2
3.2 Field descriptions ........................................................................................ 3-3
Appendix A Signal Descriptions
A.1 Signal descriptions ...................................................................................... A-2
Contents
iv Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
Appendix B Integration with the ARM1136 Processor
2.1 Instruction Register enables field ............................................................... B-2
B.2 Choosing the RAM size .............................................................................. B-3
B.3 Connection ............................................................................................... B-12
Appendix C Integration with the ETB11
3.1 Instruction Register enables field ............................................................... C-2
C.2 Trace RAM ................................................................................................. C-3
C.3 Connection ................................................................................................. C-5
ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. v
List of Tables
ARM11 Memory Built-In Self Test Controller
Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 ARM11 MBIST Controller interface signals ............................................................... 1-4
Table 2-1 Format of the data log ............................................................................................... 2-5
Table 3-1 Register settings and resulting address sizes ........................................................... 3-5
Table 3-2 Register settings and resulting address sizes ........................................................... 3-5
Table 3-3 Behavior of the engine control field ........................................................................... 3-6
Table 3-4 Supported patterns .................................................................................................... 3-7
Table 3-5 Go/No-Go algorithm .................................................................................................. 3-9
Table A-1 Signal descriptions .................................................................................................... A-2
Table B-1 Enable bit RAM selection .......................................................................................... B-2
Table B-2 Example values for x- and y-Locations, TLB RAM .................................................... B-3
Table B-3 Choosing values for x- and y-Locations, BTAC RAM ................................................ B-4
Table B-4 ITCM size and location .............................................................................................. B-4
Table B-5 Cache valid size and locations .................................................................................. B-5
Table B-6 TCM size and locations ............................................................................................. B-6
Table B-7 Instruction cache size and tag RAM locations .......................................................... B-7
Table B-8 Instruction cache size and data RAM locations ........................................................ B-7
Table B-9 Greater of data cache or data TCM size and dirty RAM locations ............................ B-8
Table B-10 DTCM size and DTCM RAM locations ...................................................................... B-9
Table B-11 Data cache size and data cache tag RAM locations ............................................... B-10
Table B-12 Data cache size and data cache tag RAM locations ............................................... B-10
List of Tables
vi Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
Table C-1 Enable bit RAM selection .......................................................................................... C-2
Table C-2 ETB_ADDR_WIDTH and ETB11 Trace RAM locations ........................................... C-3
ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. vii
List of Figures
ARM11 Memory Built-In Self Test Controller
Technical Reference Manual
Key to timing diagram conventions .............................................................................. xi
Figure 1-1 Traditional method of interfacing MBIST ................................................................... 1-3
Figure 1-2 ARM11 processor MBIST interface ........................................................................... 1-4
Figure 2-1 Loading the ARM memory BIST instruction .............................................................. 2-2
Figure 2-2 Starting the memory BIST test .................................................................................. 2-3
Figure 2-3 Detecting a failure during memory BIST ................................................................... 2-3
Figure 2-4 Start of data log retrieval ........................................................................................... 2-4
Figure 2-5 End of data log retrieval ............................................................................................ 2-4
Figure 3-1 Memory BIST Instruction Register bit assignments .................................................. 3-2
Figure 3-2 Example RAM topology ............................................................................................. 3-4
Figure 3-3 MBIST location addressing ....................................................................................... 3-4
List of Figures
viii Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
Preface
xCopyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
About this book
This book provides a description of the ARM11 Memory Built-In Self Test (MBIST)
Controller.
Intended audience
This book is written for hardware engineers who are familiar with ARM technology and
want to use the ARM11 MBIST Controller to test embedded memory on ARM11-based
devices.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an overview of the ARM11 MBIST Controller.
Chapter 2 Functional Description
Read this chapter for timing and data log retrieval information for the
ARM11 MBIST Controller.
Chapter 3 ARM11 MBIST Controller Instruction Register
Read this chapter for a description of the ARM11 MBIST Controller
Instruction Register and associated bit assignments.
Appendix A Signal Descriptions
Read this chapter for descriptions of the ARM11 MBIST Controller
signals.
Appendix B Integration with the ARM1136 Processor
Read this chapter for a description of using the ARM11 MBIST
Controller with an ARM1136 processor.
Appendix C Integration with the ETB11
Read this chapter for a description using the ARM11 MBIST Controller
with the ARM11 Embedded Trace Buffer (ETB11).
Typographical conventions
The following typographical conventions are used in this book:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
Preface
ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. xi
bold Highlights interface elements, such as menu names. Denotes
ARM processor signal names. Also used for terms in descriptive
lists, where appropriate.
monospace
Denotes text that can be entered at the keyboard, such as
commands, file and program names, and source code.
monospace
Denotes a permitted abbreviation for a command or option. The
underlined text can be entered instead of the full command or
option name.
monospace
italic
Denotes arguments to commands and functions where the
argument is to be replaced by a specific value.
monospace
bold
Denotes language keywords when used outside example code.
Timing diagram conventions
This manual contains timing diagrams. The figure below explains the components used
in these diagrams. Any variations are clearly labeled when they occur. Therefore, no
additional meaning must be attached unless specifically stated.
Key to timing diagram conventions
Shaded bus and signal areas are undefined, so the bus or signal can assume any value in
the shaded area at that time. The actual level is unimportant and does not affect normal
operation.
Other conventions
This document uses other conventions. They are described in the following sections:
•Signals on page xii
•Bits and bytes on page xii
•Numbers on page xii.
Clock
HIGH to LOW
LOW to HIGH
Bus stable
Bus change
Preface
xii Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
Signals
When a signal is described as being asserted, the level depends on whether the signal is
active HIGH or active LOW. Asserted means HIGH for active high signals and LOW
for active low signals:
Prefix n Active LOW signals are prefixed by a lowercase n except in the case of
AHB or APB reset signals. These are named HRESETn and PRESETn
respectively.
Bits and bytes
Suffix b Indicates bits.
Suffix B Indicates bytes.
Byte Eight bits.
Numbers
Suffix K Indicates an amount of memory. It means 1024.
Suffix M When used to indicate an amount of memory means 10242= 1048576.
When used to indicate a frequency means 1000000.
Prefix 0x Indicates hexadecimal.
Prefix b Indicates binary.
Further reading
This section lists publications from both ARM Limited and third parties that provide
additional information on developing code for the ARM family of processors.
ARM periodically provides updates and corrections to its documentation. See
http://www.arm.com
for current errata sheets, addenda, and the ARM Frequently Asked
Questions list.
Preface
ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. xiii
Feedback
ARM Limited welcomes feedback on both the ARM11 MBIST Controller, and its
documentation.
Feedback on the ARM11 MBIST Controller
If you have any comments or suggestions about this product, contact your supplier
giving:
• the product name
• a concise explanation of your comments.
Feedback on this book
If you have any comments on this book, send email to
giving:
• the document title
• the document number
• the page number(s) to which your comments apply
• a concise explanation of your comments.
General suggestions for additions and improvements are also welcome.
Preface
xiv Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
Introduction
1-2 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
1.1 Overview
In recent years, MBIST has become the industry-standard method of testing embedded
memories. MBIST works by performing sequences of reads and writes to the memory
according to an algorithm. Many industry-standard algorithms exist.
An MBIST Controller is used to generate the correct sequence of reads and writes. The
ARM11 MBIST Controller can be used with some ARM products to perform embedded
memory testing. ARM11 MBIST Controllers are currently available for the following
products:
• ARM1136JF-S processor
• ARM1136J-S processor
• ARM1136J-S PrimeXsys Platform (PXP) uses the ARM11 MBIST Controller
• ETB11.
This Technical Reference Manual (TRM) provides a high-level description of the
common features of these ARM11 MBIST Controllers. Information that is specific to
individual ARM11 MBIST Controllers for each of the supported products is provided
in Appendix B Integration with the ARM1136 Processor and Appendix C Integration
with the ETB11.
Introduction
ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. 1-3
1.2 MBIST ports
The traditional method of gaining access to a RAM for MBIST is shown in Figure 1-1.
Figure 1-1 Traditional method of interfacing MBIST
This is not suitable for use in high-performance designs because the maximum
operating frequency is reduced significantly. Instead, an additional input to existing
multiplexors is added without reducing maximum operating frequency. Figure 1-2 on
page 1-4 shows four of the pipeline stages used to access the RAM blocks. This number
can vary depending on the product used.
Note
The method shown in Figure 1-1 has the advantage of having the two cycle
register-to-register path that accesses the RAM blocks using the same path in memory
BIST mode as in functional mode.
0
1
0
1
0
1
0
1
BistMode
BistWE
BistCE
BistAddress
BistDataIn
WE
CE
Address
DataIn
DataOut
BistDataOut
RAM
Introduction
1-4 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
Figure 1-2 ARM11 processor MBIST interface
The ARM11 MBIST Controller accesses the memory in this way through the MBIST
interface. This contains the ports listed in Table 1-1.
RAM
block
CLK
Functional
output
MBISTDIN
MBISTADDR
MBISTCE
From other RAM blocks
From
data
paths
MBISTDOUT
From
address
paths
DQ
DQ
DQ
DQ
MBISTCE
From
chip
enables
DQ
DQ
MBISTWE
From
write
enables
DQ
DQ
MTESTON DQ
DQ
EN
DQ
DQ
Table 1-1 ARM11 MBIST Controller interface signals
Name Type Description
MTESTON Input Switches multiplexors to give access to the RAM blocks. Must be HIGH during MBIST
mode.
MBISTDIN Input Data bus to the RAM blocks. Not all RAM blocks are the full width.
MBISTADDR Input RAM block address signals. Not all RAM blocks use the full address width.
Introduction
ARM DDI 0289B Copyright © 2003 ARM Limited. All rights reserved. 1-5
MBISTCE Input Selects RAM blocks. One hot-chip enable for each of the RAM blocks. This signal can be a
bus if required.
MBISTWE Input Global write enabling signal to all of the RAM blocks.
MBISTDOUT Output Data out bus for all of the RAM blocks. Multiple RAM blocks can be selected if output bits
do not overlap.
Table 1-1 ARM11 MBIST Controller interface signals (continued)
Name Type Description
Introduction
1-6 Copyright © 2003 ARM Limited. All rights reserved. ARM DDI 0289B
Table of contents
Other ARM Controllers manuals
