ARM Cortex-A9 MBIST Product manual

Copyright © 2008 ARM Limited. All rights reserved.
ARM DDI 0414C
Cortex™-A9 MBIST Controller
Revision: r1p0
Technical Reference Manual

ii Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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Cortex-A9 MBIST Controller
Technical Reference Manual
Copyright © 2008 ARM Limited. All rights reserved.
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Contents
Cortex-A9 MBIST Controller Technical
Reference Manual
Preface
About this book ............................................................................................. xii
Feedback ..................................................................................................... xvi
Chapter 1 Introduction
1.1 About the MBIST controller ......................................................................... 1-2
1.2 MBIST controller interface ........................................................................... 1-3
1.3 Product revisions ........................................................................................ 1-7
Chapter 2 Functional Description
2.1 Functional overview .................................................................................... 2-2
2.2 Functional operation ................................................................................. 2-15
Chapter 3 MBIST Instruction Register
3.1 About the MBIST instruction register .......................................................... 3-2
3.2 Field descriptions ........................................................................................ 3-4
Chapter 4 MBIST Datalog Register
4.1 About the MBIST Datalog Register ............................................................. 4-2
4.2 Field descriptions ........................................................................................ 4-3

Contents
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Appendix A Signal Descriptions
A.1 MBIST controller interface signals .............................................................. A-2
A.2 Miscellaneous signals ................................................................................. A-4
Appendix B Revisions
Glossary

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List of Tables
Cortex-A9 MBIST Controller Technical
Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Cortex-A9 processor MBIST interface signals .......................................................... 1-6
Table 2-1 Cortex-A9 signal settings for MBIST ......................................................................... 2-2
Table 2-2 RAM arrays and MBIST controller interfaces ............................................................ 2-2
Table 2-3 Data data RAM byte write enable control .................................................................. 2-5
Table 2-4 MBISTARRAY bit usage for tag RAMs ..................................................................... 2-6
Table 2-5 Tag RAM control ....................................................................................................... 2-8
Table 2-6 MBISTTX signals .................................................................................................... 2-11
Table 2-7 MBISTRX signals .................................................................................................... 2-12
Table 2-8 MBIST controller top level I/O ................................................................................. 2-13
Table 2-9 Data log format ........................................................................................................ 2-18
Table 3-1 Pattern field encoding ............................................................................................... 3-4
Table 3-2 Go/No-Go test pattern ............................................................................................... 3-6
Table 3-3 Control field encoding (five LSB bits) ........................................................................ 3-7
Table 3-4 Read latency field encoding ...................................................................................... 3-8
Table 3-5 Write latency field encoding ...................................................................................... 3-8
Table 3-6 MBIR[39:36] CPU mapping ....................................................................................... 3-9
Table 3-7 MaxXAddr field encoding ........................................................................................ 3-10
Table 3-8 MaxYAddr field encoding ........................................................................................ 3-10
Table 3-9 ArrayEnables field encoding ................................................................................... 3-11
Table 3-10 ColumnWidth field encoding ................................................................................... 3-13

List of Tables
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Table 3-11 CacheSize field encoding ....................................................................................... 3-13
Table A-1 MBIST controller interface signals ............................................................................ A-2
Table A-2 MBISTARRAY one-hot chip enables ........................................................................ A-2
Table A-3 Miscellaneous signals ............................................................................................... A-4
Table B-1 Differences between issue A and issue B ................................................................ B-1
Table B-2 Differences between issue B and issue C ................................................................ B-1

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List of Figures
Cortex-A9 MBIST Controller Technical
Reference Manual
Key to timing diagram conventions ............................................................................ xiv
Figure 1-1 Cortex-A9 MBIST configuration ................................................................................ 1-2
Figure 1-2 MBIST controller wiring diagram ............................................................................... 1-3
Figure 1-3 Traditional method of interfacing MBIST ................................................................... 1-4
Figure 1-4 Cortex-A9 processor MBIST interface ...................................................................... 1-5
Figure 2-1 Data In for Instruction data RAM and Data data RAM .............................................. 2-5
Figure 2-2 Data Out for Instruction data RAM and Data data RAM ........................................... 2-5
Figure 2-3 Data in for Instruction tag RAM ................................................................................. 2-6
Figure 2-4 Data out for Instruction tag RAM ............................................................................... 2-7
Figure 2-5 Data in for Data tag RAM and SCU tag RAM ........................................................... 2-7
Figure 2-6 Data out for Data tag RAM and SCU tag RAM ......................................................... 2-7
Figure 2-7 Data in for Outer RAM ............................................................................................... 2-8
Figure 2-8 Data out for Outer RAM ............................................................................................ 2-8
Figure 2-9 Data in for BTAC RAM .............................................................................................. 2-9
Figure 2-10 Data out for BTAC RAM ............................................................................................ 2-9
Figure 2-11 Data in for TLB RAM ................................................................................................. 2-9
Figure 2-12 Data out for TLB RAM ............................................................................................. 2-10
Figure 2-13 Data in for GHB RAM .............................................................................................. 2-10
Figure 2-14 MBIST controller block ............................................................................................ 2-11
Figure 2-15 Loading the MBIST controller instruction ................................................................ 2-15
Figure 2-16 Starting the MBIST test ........................................................................................... 2-16

List of Figures
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Figure 2-17 Detecting an MBIST failure ..................................................................................... 2-16
Figure 2-18 Start of data log retrieval ......................................................................................... 2-17
Figure 2-19 End of data log retrieval .......................................................................................... 2-17
Figure 2-20 Start of bitmap data log retrieval ............................................................................. 2-18
Figure 2-21 End of bitmap data log retrieval .............................................................................. 2-19
Figure 3-1 MBIST instruction register control unit ...................................................................... 3-2
Figure 3-2 MBIST instruction register dispatch unit ................................................................... 3-2
Figure 4-1 MBIST Datalog Register format ................................................................................ 4-2

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Preface
This preface introduces the Cortex-A9 MBIST Controller Technical Reference Manual.
It contains the following sections:
•About this book on page xii
•Feedback on page xvi.

Preface
xii Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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About this book
This book is for the Cortex-A9 MBIST controller.
In this book, the generic term MBIST controller means the Cortex-A9 MBIST
controller, and Cortex-A9 processor means the Cortex-A9 processor family.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This book is written for hardware engineers who are familiar with ARM technology and
want to use the MBIST controller to test the RAM blocks used by the Cortex-A9
processor. The AXI protocol is not specified, but some familiarity with AXI is assumed.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to MBIST technology.
Chapter 2 Functional Description
Read this for a description of the Cortex-A9 processor interface to the
MBIST controller and MBIST testing of the data RAM and tag RAMs.
Also read this chapter for a description of the timing sequences for
loading MBIST instructions, starting the MBIST test, detecting failures,
and retrieving the data log.
Chapter 3 MBIST Instruction Register
Read this for a description on how to use the MBIST Instruction Register
to configure the mode of operation of the MBIST engine.
Chapter 4 MBIST Datalog Register
Read this for a description of the MBIST Datalog Register.

Preface
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Appendix A Signal Descriptions
Read this for a description of the MBIST controller input and output
signals.
Appendix B Revisions
Read this for a description of the technical changes between released
issues of this book.
Glossary Read this for definitions of terms used in this book.
Conventions
Conventions that this book can use, are described in:
•Typographical
•Timing diagrams on page xiv
•Signals on page xiv.
Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
signal names. Also used for terms in descriptive lists, where
appropriate.
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
< and > Enclose replaceable terms for assembler syntax where they appear
in code or code fragments. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>

Preface
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Timing diagrams
The figure named Key to timing diagram conventions explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals
• LOW for active-LOW signals.
Lower-case n At the start or end of a signal name denotes an active-LOW signal.
Prefix A Denotes global Advanced eXtensible Interface (AXI) global and
address channel signals.
Prefix AF Denotes Advanced Trace Bus (ATB) flush control signals.
Prefix AR Denotes AXI read address channel signals.
Prefix AT Denotes ATB data flow signals.
Prefix AW Denotes AXI write address channel signals.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

Preface
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Prefix B Denotes AXI write response channel signals.
Prefix C Denotes AXI low-power interface signals.
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Prefix P Denotes Advanced Peripheral Bus (APB) signals.
Prefix R Denotes AXI read data channel signals.
Prefix W Denotes AXI write data channel signals.
Further reading
This section lists publications by ARM and by third parties.
See
http://infocenter.arm.com for access to ARM documentation.
ARM publications
This book contains information that is specific to this product. See the following
documents for other relevant information:
•Cortex-A9 Technical Reference Manual (ARM DDI 0388)
•Cortex-A9 Configuration and Sign-Off Guide (ARM DII 0146)
•AMBA AXI Protocol Specification (ARM IHI 0022)
•ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
(ARM DDI 0406).

Preface
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Feedback
ARM welcomes feedback on the MBIST controller and on its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier
giving:
• the product name
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms
if appropriate.
Feedback on this book
If you have any comments on this book, send e-mail to
[email protected] giving:
• the title
• the number
• the relevant page number(s) to which your comments apply
• a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.

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Chapter 1
Introduction
This chapter describes the purpose of the MBIST controller. It contains the following
sections:
•About the MBIST controller on page 1-2
•MBIST controller interface on page 1-3
•Product revisions on page 1-7.

Introduction
1-2 Copyright © 2008 ARM Limited. All rights reserved. ARM DDI 0414C
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1.1 About the MBIST controller
MBIST is the industry-standard method of testing embedded memories. MBIST works
by performing sequences of reads and writes to the memory according to a test
algorithm. Many industry-standard test algorithms exist.
An MBIST controller generates the correct sequence of reads and writes to all locations
of the RAM to ensure that the cells are operating correctly. In doing this, some
additional test coverage is achieved in the address and data paths that the MBIST uses.
You must only use the MBIST controller with the Cortex-A9 processor to perform
memory testing of the Cortex-A9 RAMs.
MBIST mode takes priority over all other modes, for example SCAN, in that the
Cortex-A9 RAMs are only accessible to the MBIST controller when MBIST mode is
activated with the MBISTENABLE pin. You must keep the MBISTENABLE signal
LOW during functional mode, and the AXI interfaces LOW during MBIST mode.
The MBIST controller controls the MBIST testing of the Cortex-A9 RAMs through the
MBIST port of the Cortex-A9 processor. Figure 1-1 shows the Cortex-A9 processor
MBIST configuration.
Figure 1-1 Cortex-A9 MBIST configuration
Cortex-A9 /
A9MP NORAM
MBIST block
Dispatch
unit
MBIST
controller
CPU0 RAMs
CPU1 RAMs
(for MP version)
CPU2 RAMs
(for MP version)
CPU3 RAMs
(for MP version)
SCU RAMs
(for MP version)

Introduction
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1.2 MBIST controller interface
Figure 1-2 shows the nonprotein configuration of the MBIST controller interface to the
Automated Test Equipment (ATE) and to the MBIST interface of the Cortex-A9
processor.
Figure 1-2 MBIST controller wiring diagram
Figure 1-3 on page 1-4 shows the traditional method of accessing RAMs for MBIST.
MBISTDATAIN
nRESET
MBISTENABLE
MBISTDSHIFT
MBISTRUN
MBISTSHIFT
MBISTRESULT[5:0]
nRESET
CLK CLK
MBISTDOUTDATA[255:0]
nRESET
MBISTENABLE
MBISTDSHIFT
MBISTRUN
MBISTSHIFT
MBISTDATAIN
MBISTRESULT[5:0]
MBISTARRAY[19:0]
MBISTBE[25:0]
MBISTADDR[10:0]
MBISTINDATA[63:0]
MBISTARRAY[19:0]
MBISTBE[25:0]
MBISTADDR[10:0]
MBISTINDATA[63:0]
MBISTENABLE
MBISTDOUTDATA[255:0]
CLK
nRESET
Automated Test
Equipment (ATE)
MBIST controller Cortex-A9/A9MP
MBISTWRITEEN MBISTWRITEEN

Introduction
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Figure 1-3 Traditional method of interfacing MBIST
Because this method significantly reduces the maximum operating frequency, it is not
suitable for high-performance designs. Instead, the MBIST controller uses an additional
input to the existing functional multiplexors without reducing maximum operating
frequency.
Figure 1-4 on page 1-5 shows the six pipeline stages used to access the RAM arrays.
DataIn
BistDataIn
0
1
0
1
Address
BistAddress
0
1
CE
BistCE
0
1
WE
BistWE
BistMode
RAM DataOut
BistDataOut