ARM CoreLink GIC-600AE Product manual

Arm® CoreLink™ GIC-600AE Generic Interrupt
Controller
Revision: r0p3
Technical Reference Manual
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101206_0003_04_en

Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Copyright © 2018–2020, 2022 Arm Limited (or its affiliates). All rights reserved.
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Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
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Contents
Contents
1. Introduction....................................................................................................................................................12
1.1 Product revision status................................................................................................................................12
1.2 Intended audience........................................................................................................................................12
1.3 Conventions................................................................................................................................................... 12
1.4 Useful resources........................................................................................................................................... 14
2. About the GIC-600AE.................................................................................................................................16
2.1 Components...................................................................................................................................................16
2.2 Compliance.....................................................................................................................................................20
2.3 Features...........................................................................................................................................................21
2.4 Test features.................................................................................................................................................. 22
2.5 Product documentation...............................................................................................................................22
2.6 Product revisions.......................................................................................................................................... 23
3. Components and configuration................................................................................................................ 25
3.1 Distributor...................................................................................................................................................... 25
3.1.1 Distributor AXI4-Stream interfaces...................................................................................................... 26
3.1.2 Distributor ACE-Lite subordinate interface........................................................................................ 27
3.1.3 Distributor ACE-Lite manager interface.............................................................................................. 28
3.1.4 Distributor Q-Channels........................................................................................................................... 29
3.1.5 Distributor P-Channel.............................................................................................................................. 30
3.1.6 Distributor configuration......................................................................................................................... 30
3.2 Redistributor...................................................................................................................................................31
3.2.1 Redistributor AXI4-Stream interface.................................................................................................... 32
3.2.2 Redistributor GIC Stream Protocol interface......................................................................................32
3.2.3 Redistributor Q-Channel......................................................................................................................... 32
3.2.4 Redistributor PPI signals..........................................................................................................................33
3.2.5 Redistributor configuration..................................................................................................................... 33
3.3 Interrupt Translation Service......................................................................................................................34
3.3.1 ITS ACE-Lite subordinate interface...................................................................................................... 36
3.3.2 ITS ACE-Lite manager interface............................................................................................................37
3.3.3 ITS AXI4-Stream interface...................................................................................................................... 38
3.3.4 ITS Q-Channel........................................................................................................................................... 39
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Contents
3.3.5 ITS configuration....................................................................................................................................... 39
3.4 MSI-64 Encapsulator................................................................................................................................... 40
3.4.1 MSI-64 ACE-Lite interfaces................................................................................................................... 40
3.4.2 MSI-64 Encapsulator configuration...................................................................................................... 41
3.5 SPI Collator.................................................................................................................................................... 42
3.5.1 SPI Collator AXI4-Stream interface...................................................................................................... 42
3.5.2 SPI Collator wires......................................................................................................................................42
3.5.3 SPI Collator power Q-Channel.............................................................................................................. 43
3.5.4 SPI Collator clock Q-Channel................................................................................................................ 43
3.5.5 SPI Collator configuration....................................................................................................................... 44
3.6 Wake Request............................................................................................................................................... 44
3.6.1 Wake Request AXI4-Stream interface..................................................................................................45
3.6.2 Wake Request configuration.................................................................................................................. 45
3.7 Interconnect................................................................................................................................................... 45
3.7.1 Interconnect configuration......................................................................................................................46
3.8 Hierarchy.........................................................................................................................................................46
4. Operation........................................................................................................................................................48
4.1 Interrupt types.............................................................................................................................................. 48
4.1.1 SGIs...............................................................................................................................................................48
4.1.2 PPIs............................................................................................................................................................... 48
4.1.3 SPIs............................................................................................................................................................... 49
4.1.4 LPIs............................................................................................................................................................... 49
4.1.5 Choosing between LPIs and SPIs..........................................................................................................50
4.2 Interrupt groups and security....................................................................................................................51
4.3 Physical interrupt signals (PPIs and SPIs)................................................................................................52
4.4 Affinity routing and assignment................................................................................................................53
4.5 SPI routing and 1 of N selection..............................................................................................................54
4.6 Power management..................................................................................................................................... 56
4.6.1 Redistributor power management.........................................................................................................56
4.6.2 Processor core power management..................................................................................................... 57
4.6.3 Other power management..................................................................................................................... 58
4.7 Getting started.............................................................................................................................................. 60
4.8 Backwards compatibility..............................................................................................................................60
4.9 ITS.................................................................................................................................................................... 60
4.9.1 ITS cache control, locking, and test......................................................................................................61
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Contents
4.9.2 ITS commands and errors.......................................................................................................................62
4.10 LPI caching...................................................................................................................................................63
4.11 Memory access and attributes............................................................................................................... 64
4.12 MSI-64.......................................................................................................................................................... 65
4.13 RAMs and ECC...........................................................................................................................................66
4.14 Performance Monitoring Unit................................................................................................................. 67
4.15 Reliability, Accessibility, and Serviceability........................................................................................... 68
4.15.1 Non-secure access................................................................................................................................. 69
4.15.2 Scrub..........................................................................................................................................................69
4.15.3 Error record classification..................................................................................................................... 69
4.15.4 ECC error reporting and recovery......................................................................................................69
4.15.5 Error recovery and fault handling interrupts....................................................................................70
4.15.6 Error handling records...........................................................................................................................71
4.15.7 Bus errors................................................................................................................................................. 87
4.16 Multichip operation................................................................................................................................... 88
4.16.1 Connecting the chips.............................................................................................................................89
4.16.2 Changing the Routing table owner.................................................................................................... 90
4.16.3 SPI ownership for multichip operation..............................................................................................91
4.16.4 Power control and P-Channel............................................................................................................. 91
4.16.5 Isolating a chip from the system........................................................................................................ 92
4.16.6 SPI operation for multichip operation............................................................................................... 93
4.16.7 LPI multichip operation......................................................................................................................... 94
5. Programmers model.....................................................................................................................................95
5.1 Register map pages......................................................................................................................................95
5.1.1 Discovery.....................................................................................................................................................97
5.1.2 GIC-600AE register access and banking.............................................................................................98
5.2 Distributor registers (GICD/GICDA) summary...................................................................................... 98
5.2.1 GICD_CTLR, Distributor Control Register........................................................................................ 101
5.2.2 GICD_TYPER, Interrupt Controller Type Register...........................................................................102
5.2.3 GICD_IIDR, Distributor Implementer Identification Register........................................................103
5.2.4 GICD_FCTLR, Function Control Register..........................................................................................104
5.2.5 GICD_SAC, Secure Access Control register.....................................................................................106
5.2.6 GICD_CHIPSR, Chip Status Register................................................................................................. 107
5.2.7 GICD_DCHIPR, Default Chip Register.............................................................................................. 109
5.2.8 GICD_CHIPR<n>, Chip Registers....................................................................................................... 109
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Contents
5.2.9 GICD_ICLARn, Interrupt Class Registers.......................................................................................... 111
5.2.10 GICD_ICERRRn, Interrupt Clear Error Registers...........................................................................112
5.2.11 GICD_CFGID, Configuration ID Register....................................................................................... 112
5.2.12 GICD_PIDR4, Peripheral ID4 register............................................................................................. 114
5.2.13 GICD_PIDR3, Peripheral ID3 register............................................................................................. 114
5.2.14 GICD_PIDR2, Peripheral ID2 register............................................................................................. 115
5.2.15 GICD_PIDR1, Peripheral ID1 register............................................................................................. 116
5.2.16 GICD_PIDR0, Peripheral ID0 register............................................................................................. 117
5.3 Distributor registers (GICM) for message-based SPIs summary..................................................... 118
5.3.1 GICM_TYPER, Message-based Type Register................................................................................. 119
5.3.2 GICM_IIDR, Message-based Distributor Implementer Identification Register..........................120
5.4 Redistributor registers for control and physical LPIs summary....................................................... 121
5.4.1 GICR_IIDR, Redistributor Implementation Identification Register............................................... 123
5.4.2 GICR_TYPER, Redistributor Type Register....................................................................................... 124
5.4.3 GICR_WAKER, Power Management Control Register................................................................... 125
5.4.4 GICR_FCTLR, Function Control Register.......................................................................................... 126
5.4.5 GICR_PWRR, Power Register.............................................................................................................. 127
5.4.6 GICR_CLASSR, Class Register............................................................................................................. 129
5.4.7 GICR_PIDR2, Peripheral ID2 Register............................................................................................... 129
5.5 Redistributor registers for SGIs and PPIs summary........................................................................... 130
5.5.1 GICR_MISCSTATUSR, Miscellaneous Status Register....................................................................132
5.5.2 GICR_IERRVR, Interrupt Error Valid Register...................................................................................133
5.5.3 GICR_SGIDR, SGI Default Register....................................................................................................134
5.5.4 GICR_CFGID0, Configuration ID0 Register..................................................................................... 135
5.5.5 GICR_CFGID1, Configuration ID1 Register..................................................................................... 136
5.6 ITS control register summary.................................................................................................................. 137
5.6.1 GITS_IIDR, ITS Implementer Identification Register....................................................................... 138
5.6.2 GITS_TYPER, ITS Type Register..........................................................................................................139
5.6.3 GITS_FCTLR, Function Control Register...........................................................................................140
5.6.4 GITS_OPR, Operations Register..........................................................................................................143
5.6.5 GITS_OPSR, Operation Status Register.............................................................................................144
5.6.6 GITS_CFGID, Configuration ID Register........................................................................................... 145
5.6.7 GITS_PIDR2, Peripheral ID2 Register................................................................................................146
5.7 ITS translation register summary............................................................................................................147
5.8 GICT register summary.............................................................................................................................148
5.8.1 GICT_ERR<n>FR, Error Record Feature Register........................................................................... 149
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Contents
5.8.2 GICT_ERR<n>CTLR, Error Record Control Register.......................................................................150
5.8.3 GICT_ERR<n>STATUS, Error Record Primary Status Register.....................................................151
5.8.4 GICT_ERR<n>ADDR, Error Record Address Register....................................................................152
5.8.5 GICT_ERR<n>MISC0, Error Record Miscellaneous Register 0.................................................... 153
5.8.6 GICT_ERR<n>MISC1, Error Record Miscellaneous Register 1.................................................... 158
5.8.7 GICT_ERRGSR, Error Group Status Register....................................................................................159
5.8.8 GICT_ERRIRQCR<n>, Error Interrupt Configuration Registers....................................................160
5.8.9 GICT_DEVID, Device Configuration register................................................................................... 161
5.8.10 GICT_PIDR2, Peripheral ID2 Register............................................................................................. 162
5.9 GICP register summary.............................................................................................................................163
5.9.1 GICP_EVCNTRn, Event Counter Registers.......................................................................................164
5.9.2 GICP_EVTYPERn, Event Type Configuration Registers................................................................. 164
5.9.3 GICP_SVRn, Shadow Value Registers................................................................................................ 168
5.9.4 GICP_FRn, Filter Registers................................................................................................................... 169
5.9.5 GICP_CNTENSET0, Counter Enable Set Register 0...................................................................... 170
5.9.6 GICP_CNTENCLR0, Counter Enable Clear Register 0.................................................................. 170
5.9.7 GICP_INTENSET0, Interrupt Contribution Enable Set Register 0...............................................171
5.9.8 GICP_INTENCLR0, Interrupt Contribution Enable Clear Register 0...........................................172
5.9.9 GICP_OVSCLR0, Overflow Status Clear Register 0.......................................................................173
5.9.10 GICP_OVSSET0, Overflow Status Set Register 0.........................................................................174
5.9.11 GICP_CAPR, Counter Shadow Value Capture Register.............................................................. 175
5.9.12 GICP_CFGR, Configuration Information Register.........................................................................176
5.9.13 GICP_CR, Control Register................................................................................................................ 176
5.9.14 GICP_IRQCR, Interrupt Configuration Register............................................................................ 177
5.9.15 GICP_PIDR2, Peripheral ID2 Register............................................................................................. 178
5.10 FMU register summary.......................................................................................................................... 179
5.10.1 FMU_ERR<n>FR, Error Record Feature Register......................................................................... 180
5.10.2 FMU_ERR<n>CTLR, Error Record Control Register.................................................................... 181
5.10.3 FMU_ERR<n>STATUS, Error Record Primary Status register....................................................182
5.10.4 FMU_ERRGSR, Error Group Status Register................................................................................. 184
5.10.5 FMU_KEY, FMU Key register............................................................................................................184
5.10.6 FMU_PINGCTLR, Ping Control Register.........................................................................................185
5.10.7 FMU_PINGNOW, Ping Now register.............................................................................................. 186
5.10.8 FMU_SMEN, Safety Mechanism Enable register......................................................................... 187
5.10.9 FMU_SMINJERR, Safety Mechanism Inject Error register......................................................... 189
5.10.10 FMU_PINGMASK, Ping Mask register..........................................................................................190
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Contents
5.10.11 FMU_STATUS, FMU Status register............................................................................................. 191
5.10.12 FMU_ERRIDR, Error Record ID Register......................................................................................191
6. Functional Safety........................................................................................................................................193
6.1 Safety Mechanism overview................................................................................................................... 193
6.2 Fault Management Unit............................................................................................................................196
6.2.1 FMU APB4 interface............................................................................................................................. 197
6.2.2 Error signaling..........................................................................................................................................197
6.2.3 Error record format................................................................................................................................ 198
6.2.4 FMU reset................................................................................................................................................ 199
6.2.5 Safety Mechanism IDs...........................................................................................................................199
6.2.6 Ping mechanisms.................................................................................................................................... 203
6.2.7 Lock and key mechanism......................................................................................................................206
6.2.8 Correctable Error enable...................................................................................................................... 207
6.2.9 Software interaction...............................................................................................................................207
6.3 FuSa programmer's view.......................................................................................................................... 209
6.4 FuSa I/O.......................................................................................................................................................209
6.4.1 Non-architected FuSa ports.................................................................................................................209
6.4.2 P-Channel and Q-Channel FuSa ports.............................................................................................. 210
6.4.3 AMBA interface FuSa ports................................................................................................................. 211
6.5 Clocks and resets.......................................................................................................................................211
6.5.1 Clocks........................................................................................................................................................ 212
6.5.2 Resets........................................................................................................................................................ 214
6.6 Lock-step protection..................................................................................................................................217
6.6.1 Comparators.............................................................................................................................................218
6.6.2 Non-resettable flops.............................................................................................................................. 219
6.6.3 Reset.......................................................................................................................................................... 219
6.6.4 Error injection..........................................................................................................................................219
6.7 RAM protection.......................................................................................................................................... 219
6.7.1 SECDED ECC data protection............................................................................................................ 220
6.7.2 Address protection................................................................................................................................. 220
6.7.3 RAM scrubbing........................................................................................................................................221
6.8 External interface protection...................................................................................................................221
6.8.1 ACE-Lite interface parity protection..................................................................................................222
6.8.2 AXI4-Stream interface parity protection........................................................................................... 224
6.8.3 APB interface parity protection.......................................................................................................... 225
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Contents
6.9 AXI4-Stream internal interconnect protection.................................................................................... 226
6.9.1 GIC-rendered partially duplicated interconnect.............................................................................. 226
6.9.2 Non-GIC interconnect IP...................................................................................................................... 228
6.10 P-Channel and Q-Channel protection................................................................................................232
6.10.1 CHK bit timing......................................................................................................................................235
6.10.2 Transient faults......................................................................................................................................236
6.10.3 Stuck-at faults....................................................................................................................................... 238
6.10.4 Disabling P-Channel and Q-Channel Safety Mechanisms..........................................................239
6.10.5 P-Channel...............................................................................................................................................239
6.10.6 Q-Channel..............................................................................................................................................241
6.11 PPI and SPI interrupt interface protection........................................................................................ 244
6.11.1 PPI and SPI CHK bit timing...............................................................................................................244
6.11.2 PPI and SPI transient faults...............................................................................................................245
6.11.3 PPI and SPI stuck-at faults................................................................................................................ 246
6.11.4 PPI and SPI configuration parameters.............................................................................................246
6.12 Systematic fault watchdog protection................................................................................................246
6.13 DFT protection.........................................................................................................................................247
6.13.1 MBIST..................................................................................................................................................... 247
6.13.2 ATPG/Scan............................................................................................................................................ 248
6.13.3 LBIST....................................................................................................................................................... 248
6.14 Generic fault inputs................................................................................................................................ 248
6.15 Configuration and parameters..............................................................................................................249
A. Signal descriptions.....................................................................................................................................250
A.1 Common control signals...........................................................................................................................250
A.2 Power control signals................................................................................................................................251
A.3 Interrupt signals..........................................................................................................................................253
A.4 CPU interface signals................................................................................................................................254
A.5 ACE-Lite interface signals........................................................................................................................255
A.6 Miscellaneous signals................................................................................................................................258
A.7 Interblock AXI4-Stream interface signals............................................................................................. 260
A.8 Interdomain signals....................................................................................................................................262
A.9 Interchip AXI4-Stream interface signals............................................................................................... 262
B. Implementation-defined features.......................................................................................................... 263
C. Revisions...................................................................................................................................................... 265
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Introduction
1. Introduction
1.1 Product revision status
The rxpy identifier indicates the revision status of the product described in this manual, for
example, r1p2, where:
rxIdentifies the major revision of the product, for example, r1.
pyIdentifies the minor revision or modification status of the product, for
example, p2.
1.2 Intended audience
This book is written for system designers and programmers who are designing or programming a
System on Chip (SoC) that uses the GIC-600AE.
1.3 Conventions
The following subsections describe conventions used in Arm documents.
Glossary
The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for
those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm
meaning differs from the generally accepted meaning.
See the Arm Glossary for more information: developer.arm.com/glossary.
Convention Use
italic Citations.
bold Terms in descriptive lists, where appropriate.
monospace Text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace underline A permitted abbreviation for a command or option. You can enter the underlined text instead of the full
command or option name.
<and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
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Introduction
Convention Use
SMALL CAPITALS Terms that have specific technical meanings as defined in the Arm® Glossary. For example,
IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Recommendations. Not following these recommendations might lead to system
failure or damage.
Requirements for the system. Not following these requirements might result in
system failure or damage.
Requirements for the system. Not following these requirements will result in system
failure or damage.
An important piece of information that needs your attention.
A useful tip that might make it easier, better or faster to perform a task.
A reminder of something important that relates to the information you are reading.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does not affect normal operation.
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Document ID: 101206_0003_04_en
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Introduction
Figure 1-1: Key to timing diagram conventions
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
•HIGH for active-HIGH signals.
•LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name, n denotes an active-LOW signal.
1.4 Useful resources
This document contains information that is specific to this product. See the following resources for
other useful information.
Access to Arm documents depends on their confidentiality:
•Non-Confidential documents are available at developer.arm.com/documentation. Each
document link in the following tables goes to the online version of the document.
•Confidential documents are available to licensees only through the product package.
Arm product resources Document ID Confidentiality
Arm® CoreLink™ ADB-400 AMBA® Domain Bridge User Guide DUI 0615 Confidential
Arm® CoreLink™ CMN-600 Coherent Mesh Network Technical Reference Manual 100180 Non‑Confidential
Arm® CoreLink™ GIC-600AE Generic Interrupt Controller Configuration and Integration
Manual
101207 Confidential
Arm® CoreLink™ GIC-600AE Generic Interrupt Controller Development Interface Report 101209 Confidential
Arm® CoreLink™ GIC-600AE Generic Interrupt Controller Safety Manual 101208 Confidential
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Introduction
Arm product resources Document ID Confidentiality
GIC-600AE Dependent Failure Analysis Report PJDOC-1779577084-15964 Confidential
GIC-600AE FMEDA Report PJDOC-1779577084-15988 Confidential
Arm architecture and specifications Document ID Confidentiality
AMBA® AXI and ACE Protocol Specification IHI 0022F Non‑Confidential
AMBA® 4 AXI4-Stream Protocol Specification IHI 0051A Non‑Confidential
AMBA® Low Power Interface Specification IHI 0068D Non‑Confidential
Arm® Architecture Reference Manual Armv8, for A-profile architecture DDI 0487G.b Non‑Confidential
Arm® Architecture Reference Manual Supplement Reliability, Availability, and Serviceability (RAS), for
Armv8-A
DDI 0587D.c Non‑Confidential
Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4 IHI 0069E Non‑Confidential
GICv3 and GICv4 Software Overview DAI 0492 Non‑Confidential
Non-Arm resources Document ID Organization
Standard Manufacturer’s Identification Code JEP106 JEDEC
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Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
2. About the GIC-600AE
The GIC-600AE is a Functional Safety (FuSa) variant of the GIC‑600. The GIC-600AE is a Generic
Interrupt Controller (GIC) that handles interrupts from peripherals to the cores and between cores.
The GIC-600AE supports a distributed microarchitecture containing several individual blocks that
are used to provide a flexible GIC implementation.
The GIC-600AE supports the GICv3 architecture. For more information, see the Arm® Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
The microarchitecture scales from a single core to coherent multichip environments containing up
to 16 chips of up to 64 cores each.
All the GIC-600AE blocks communicate through fully credited AXI4-Stream interface channels. This
means that the interface only exerts transient backpressure on their ic<xy>tready signals, enabling
packets to be routed over any free-flowing interconnect. Channels can be routed over dedicated
AXI4-Stream buses, or over any available free-flowing transport layer in the system. A channel is
described as free-flowing when all transactions on that channel complete without a non-transient
dependency on any other transaction.
The GIC-600AE includes build scripts that can create appropriate levels of hierarchy for any
particular configuration. In small configurations, the distribution can be hidden and internally
optimized.
GIC‑600 information is unchanged, and information about the FuSa features
available in GIC-600AE can be found in 6. Functional Safety on page 193.
2.1 Components
The GIC-600AE comprises several significant blocks that work in combination to create a single
architecturally compliant GICv3 implementation within the system. The GIC-600AE top level can
have one of several optional structures.
The GIC-600AE consists of the following blocks:
Distributor
The Distributor is the hub of all the GIC communications and contains the functionality
for all Shared Peripheral Interrupts (SPIs) and Locality-specific Peripheral Interrupts (LPIs). It
is responsible for the entire GIC programmers model, except for the GITS_TRANSLATER
register, which is hosted in the Interrupt Translation Service (ITS) block.
The Distributor also maintains the coherency of the SPI register space in multichip
configurations.
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Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
The LPI functionality for all cores on a chip is combined into a single cache in the Distributor.
Redistributor
The Redistributor maintains the Private Peripheral Interrupts (PPIs) and Software Generated
Interrupts (SGIs) for a particular set of cores. A Redistributor can scale from 1-64 cores and is
best placed next to the processors that it is servicing to reduce wiring to the cores.
A Redistributor is also referred to as a PPI block.
The GICv3 architecture specifies a Redistributor address space containing two pages per
core. The SGI page functionality is contained in the GIC-600AE Redistributor. However, the
command and control pages for all cores on a chip are contained in the Distributor.
The GIC-600AE supports powering down the Redistributors and the associated cores.
Interrupt Translation Service
The ITS translates message-based interrupts, Message-Signaled Interrupts (MSI/MSIx), from an
external PCI Express (PCIe) Root Complex (RC), or other sources. The ITS also manages LPIs
during core power management.
The GIC-600AE supports up to eight ITS blocks per chip.
For more information about the ITS, see the GICv3 and GICv4 Software Overview.
MSI-64 Encapsulator
The MSI-64 Encapsulator is a small block that combines the DeviceID (DID), required by
writes to the GITS_TRANSLATER register, into a single memory access.
SPI Collator
The GIC-600AE supports up to 960 SPIs that are spread across the system. The SPI Collator
enables SPIs to be converted into messages remotely from the Distributor. This enables
hierarchical clock gating of the Distributor and the use of other more aggressive low-power
states.
Wake Request
The Wake Request contains all the architecturally defined wake_request signals for each core
on the chip. It is a separate block that can be positioned remotely from the Distributor, such
as next to a system control processor if necessary.
GIC interconnect
The GIC interconnect is a set of components that can be used for routing the AXI4-Stream
interfaces between the different blocks.
Top level
The top level has no specific interfaces but combines the interfaces of other blocks within
the clock or power domain to reduce the number of domain bridges. The GIC-600AE build
scripts enable you to build the GIC from a single combined block or a set of individual blocks
that are interconnected using your own transport layer.
These blocks can be combined in different ways:
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Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
•In systems where there is an available free-flowing transport layer in place, existing buses can
be used to route the GIC traffic.
•The GIC-600AE includes a narrow, 16-bit, AXI4-Stream interconnect that can be used for
routing internal traffic.
The following figure shows a GIC-600AE with a free-flowing interconnect in an example system.
Figure 2-1: GIC-600AE with free-flowing interconnect in an example system
PCIe Root
Complex
System Memory Management Unit
(SMMU)
Free-flowing interconnect
Core cluster
SPIs
Programming
interface
Core cluster
Key:
Free-flowing channel
Cross-chip
interfaces
Memory
controller
GIC
components
Wake
Request
ITS
Distributor
Redistributor Redistributor
SPI
Collator
A free-flowing channel is clear to transmit a transaction that arrives at its
destination without any non-transient dependencies on other transactions.
The following figure shows a GIC-600AE with interconnect in an example system. The cross-chip
interfaces enable communication between cores in a multichip configuration.
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Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
Figure 2-2: GIC-600AE with interconnect in an example system
PCIe Root
Complex
SMMU
System interconnect
Core cluster
Core cluster
SPIs
Programming
interface
Key:
Free-flowing channel
Cross-chip
interfaces
GIC
components
Memory
controller
Wake
Request
ITS
Distributor
Redistributor
Redistributor
SPI
Collator
The following figure shows a monolithic GIC-600AE with interconnect in an example system.
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Arm® CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
About the GIC-600AE
Figure 2-3: Monolithic GIC-600AE with interconnect in an example system
PCIe Root
Complex
SMMU
System interconnect
Core cluster Core cluster
SPIs
Programming
and ITS
interfaces
Key:
Free-flowing channel
Cross-chip
interfaces
GIC
components
ITS Distributor
Redistributor
Redistributor
SPI
Collator
Memory
controller
If the GIC supports LPIs, there must be free-flowing access to main memory. This requirement
is irrespective of the interconnect that is used for routing the AXI4-Stream interfaces. For more
information, see the Arm® CoreLink™ GIC-600AE Generic Interrupt Controller Configuration and
Integration Manual.
The GIC-600AE supports cores that implement only the Armv8.0-A architecture, and later versions
such as Armv8.2-A. The cores must also support the GIC CPU interface with the standard GIC
AXI4-Stream protocol interface. The GIC-600AE implements version 3.0 of the Arm® Generic
Interrupt Controller Architecture Specification, GIC architecture version 3 and version 4.
Related information
Components and configuration on page 25
2.2 Compliance
The GIC-600AE interfaces are compliant with Arm specifications and protocols.
The GIC-600AE is compliant with:
•Version 3.0 of the Arm GIC architecture specification. See the Arm® Generic Interrupt
Controller Architecture Specification, GIC architecture version 3 and version 4.
•The AMBA® ACE-Lite protocol. See the AMBA® AXI and ACE Protocol Specification.
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