ARTERY AT32F435 Series Guide

AT32F435/437 CRM Start Guide
2022.12.23 1 Ver 2.0.4
AN0084
Application Note
AT32F435/437 CRM Start Guide
Introduction
This application note mainly introduces:
1. How to configure and modify the clock source code based on the BSP_ V2.x.x provided by Artery.
2. How to use the accessary clock configuration tools to set clock path and parameters to generate
and use the corresponding clock code.
Applicable products:
Part number
AT32F435xx
AT32F437xx

AT32F435/437 CRM Start Guide
2022.12.23 2 Ver 2.0.4
Contents
1Overview................................................................................................................. 6
2Clock tree................................................................................................................ 7
3Code configuration and parsing .......................................................................... 8
3.1 Functions.................................................................................................................. 8
3.2 Clock configuration................................................................................................... 9
3.2.1 CRM Reset...................................................................................................................9
3.2.2 Set Flash clock division................................................................................................9
3.2.3 Clock source configuration...........................................................................................9
3.2.4 PLL configuration .......................................................................................................10
3.2.5 Set bus frequency division.........................................................................................11
3.2.6 Switch system clock...................................................................................................11
3.2.7 Update core frequency...............................................................................................12
3.3 Example of clock configuration............................................................................... 12
4Clock configuration tools ................................................................................... 14
4.1 Environment requirement.......................................................................................14
4.2 Installation.............................................................................................................. 14
4.3 Function overview ..................................................................................................14
4.4 Menu bar................................................................................................................ 15
4.5 Create configuration project ...................................................................................15
4.6 Clock configuration interface .................................................................................. 16
4.7 Generate code........................................................................................................ 18
5Notes..................................................................................................................... 19
5.1 Modification of HEXT.............................................................................................. 19
5.2 Usage of tools ........................................................................................................19
6Application case 1: Switch system clock.......................................................... 20
6.1 Introduction.............................................................................................................20

AT32F435/437 CRM Start Guide
2022.12.23 3 Ver 2.0.4
6.2 Resources.............................................................................................................. 20
6.3 Software design...................................................................................................... 20
6.4 Test result...............................................................................................................22
7Application case 2: Clock fail detector.............................................................. 23
7.1 Introduction.............................................................................................................23
7.2 Resources.............................................................................................................. 23
7.3 Software design...................................................................................................... 23
7.4 Test result...............................................................................................................25
8Application case 3: Calculation of PLL parameters......................................... 26
8.1 Introduction.............................................................................................................26
8.2 Resources.............................................................................................................. 26
8.3 Software design...................................................................................................... 26
8.4 Test result...............................................................................................................27
9Revision history................................................................................................... 28

AT32F435/437 CRM Start Guide
2022.12.23 4 Ver 2.0.4
List of tables
Table 1. Document revision history....................................................................................................28

AT32F435/437 CRM Start Guide
2022.12.23 5 Ver 2.0.4
List of figures
Figure 1. Block diagram of clock .........................................................................................................7
Figure 2. Clock configuration process.................................................................................................9
Figure 3. Startup interface.................................................................................................................14
Figure 4. Configuration interface.......................................................................................................15
Figure 5. Menu bar.............................................................................................................................15
Figure 6. Select MCU.........................................................................................................................16
Figure 7. Clock configuration interface..............................................................................................16
Figure 8. Clock configuration block ...................................................................................................17

AT32F435/437 CRM Start Guide
2022.12.23 6 Ver 2.0.4
1 Overview
As the necessary condition for the correct and efficient running of chips, proper clock configuration
is of great importance. The clock configuration of each AT32 series MCU may be slight different.
This application note mainly introduces how to use BSP_V2.x.x provided by Artery to perform clock
configuration of the corresponding AT32 MCU series.
The clock is configured with the following methods:
1. Manually write code to invoke the driver function interface in BSP to perform clock
configuration;
2. Use clock configuration tools to set and generate the corresponding source code.

AT32F435/437 CRM Start Guide
2022.12.23 7 Ver 2.0.4
2 Clock tree
Before configuring the clock, it is necessary to have a comprehensive understanding of the clock
tree, with focuses on the clock source, frequency multiplication and system clock.
Figure 1. Block diagram of clock
Figure 1 contains the following key elements:
1) SCLKSEL: The system clock can be selected from HEXT, PLLCLK and HICK.
2) HEXT: It is a high-speed external oscillator that is connected externally to a 4~25 MHz crystal
or clock source.
3) HICK: It is a high-speed internal oscillator that is clocked by a high-speed RC, and the internal
frequency of the HICK clock is 48 MHz. The HICKDIV bit is used to select HICK (48 MHz) or
HICK/6 (if the HICK/6 is selected, the clock frequency is 8 MHz).
4) PLLCLK: PLL clock = PLL reference clock / PLL_MS * PLL_NS / PLL_FR.
5) PLL reference clock: It is determined by the PLLRCS bit, and it can be selected from HICK 8
MHz and HEXT.
USB
Divider
/1,1.5,
2,2.5,
3,3.5,
4,...,7
HICK_TO_USB
USB48M
To USB interface
/2,3,4,...31
LEXT RTCCLK
To RTC
LICK RC
40 kHz
RTCSEL[1:0]
LICK
To WDT
WDTCLK
CLKOUT1
Divider1
/1,2, ,5
Clock Output1 CLKOUT1
HICK
LEXT
HEXT
PLLCLK
CLKOUT1_SEL
ADC
Divider
/2,3,4,...,17
To ADC1,2,3 ADCCLK
Max.80 MHz
Peripheral
clock enable
To AHB peripheral/memory
MACTXCLK
MII_RMII_SEL
EMAC_MII_TX_CLK
EMAC_MII_RX_CLK
0
1
0
1
/2,20
MII_RMII_SEL
To EMAC
To EMAC
EMACRMIICLK
MACRXCLK
ACC
HICK RC
48 MHz
/6
HICK48M
HICKDIV
HICK
HEXT_OUT
HEXT_IN
HEXT OSC
4-25 MHz HEXT
HEXT
PLLRCS
PLLCLK
PLLCLK
LEXT OSC
32.768 kHz
LEXT_IN
LEXT_OUT
LEXT
LICK
HICK_TO_SCLK SCLKSEL
CFD
HICK8M
HEXT
HICK
SCLK
Max. 288 MHz
12S1/2/3/4 CLK
Peripheral
clock enable
AHB
Divider
/1,2...512
HCLK
Max.288MHz
CPU FCLK
/8 CPU SysTick
MII_RMII_SEL
To EMAC
CLKOUT1
Divider2
/1,2..512
CLKOUT2
Divider1
/1,2, ,5
Clock Output2 CLKOUT2
HEXT
PLLCLK
CLKOUT2_SEL1
CLKOUT2
Divider2
/1,2..512
SCLK
HICK
ADCCLK
USB48M
CLKOUT2_SEL2
LICK
LEXT
DVP_PCLK DVP_PCLK
/MS VCO
xNS
/FR
Peripheral
Clock enable
PCLK1/2
Max.144 MHz To APB1/2 peripheral
Max.288 MHz to TMRxCLK
Peripheral
clock enable
APB1/2
Divider
/1,2,4,8,16
x1,x 2

AT32F435/437 CRM Start Guide
2022.12.23 8 Ver 2.0.4
3 Code configuration and parsing
This section introduces how to use library function interface to configure the clock.
3.1 Functions
The interface functions for hardware clock configuration in BSP of the corresponding MCU series
are encapsulated and can be called. Functions commonly used for clock configuration are listed
below. Refer to at32f435_437_crm.c/.h for details about parameters and return value of each
function.
/* CRM reset function, which resets clock configuration to default */
void crm_reset(void);
/* HEXT bypass enablel function */
void crm_hext_bypass(confirm_state new_state);
/* Status flag get function, such as the stable status flag of PLL/HEXT/HICK */
flag_status crm_flag_get(uint32_t flag);
/* Wait for HEXT clock to stable */
error_status crm_hext_stable_wait(void);
/* Clock source enable function, such as enable PLL/HEXT/HICK */
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
/* PLL configuration function for PLL clock source and PLL multiplication factor */
void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, uint16_t pll_ms, crm_pll_fr_type
pll_fr);
/* System clock switch function */
void crm_sysclk_switch(crm_sclk_type value);
/* Current system clock switch status get function */
crm_sclk_type crm_sysclk_switch_status_get(void);
/* Auto step-by-step system clock switch enable function; when PLL frequency > 108 MHz, enable auto step-by-
step switch before switching the system clock to PLL */
void crm_auto_step_mode_enable(confirm_state new_state);
/* HICK/6 configuration function, which is mainly used to select HICK 48 MHz as system clock and USB clock */
void crm_hick_divider_select(crm_hick_div_6_type value);
/* Frequency select function when HICK is selected as system clock; the frequency can be set to a fixed value (8
MHz) or divided by 6 (48 MHz divided by 6, depending on the HICK 6 divider configuration function) */
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
/* System clock to AHB clock divider configuration function */
void crm_ahb_div_set(crm_ahb_div_type value);
/* AHB clock to APB1 clock divider configuration function */
void crm_apb1_div_set(crm_apb1_div_type value);
/* AHB clock to APB2 clock divider configuration function */
void crm_apb2_div_set(crm_apb2_div_type value);

AT32F435/437 CRM Start Guide
2022.12.23 9 Ver 2.0.4
3.2 Clock configuration
Figure 2 shows the clock configuration process.
Figure 2. Clock configuration process
Set Flash Clock Division
Clock Source Enable
PLL Configuration
Switch System Clock
Update Core Frequency
CRM Reset
Set Bus Frequency Division
3.2.1 CRM Reset
According to the configuration process, perform CRM reset firstly, which switches system clock to
HICK, and write the default value to other system clock configuration registers. The implementation
code of function calling is as follows:
crm_reset(); /* CRM reset */
3.2.2 Set Flash clock division
The relationship between Flash clock division factor and system clock frequency is shown below.
System Clock Frequency
Flash Clock Division
<= 240 MHz
FLASH_CLOCK_DIV_2
>240 MHz
FLASH_CLOCK_DIV_3
The implementation code is as follows.
flash_clock_divider_set(FLASH_CLOCK_DIV_3); /* Set Flash clock division factor to 3 */
3.2.3 Clock source configuration
The HEXT or HICK can be selected as the system clock source, which can also be used as for PLL
frequency multiplication. Before enabling PLL, enable the PLL reference clock source and wait until
it becomes stable.
HEXT
If HEXT is connected externally to an active clock, the HEXT bypass mode should be enabled. If
the crystal oscillator is used, the bypass mode should be disabled. The bypass mode is set before
enabling the HEXT clock source (disabled by default). The implementation code of enabling bypass
mode is as follows:
crm_hext_bypass(TRUE); /* HEXT bypass mode enable */

AT32F435/437 CRM Start Guide
2022.12.23 10 Ver 2.0.4
Enable HEXT clock source and wait until HEXT clock becomes stable. The implementation code is
as follows:
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* Enable HEXT clock source */
while(crm_hext_stable_wait() == ERROR) /* Wait until HEXT clock becomes stable */
{
}
HICK
The HICK oscillator is clocked by a high-speed RC in the microcontroller. Enable HICK clock
source and wait until HICK clock becomes stable. The implementation code is as follows:
crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* Enable HICK clock source */
while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET) /* Wait until HICK stable flag is set */
{
}
3.2.4 PLL configuration
PLL configuration includes PLL clock source, PLL multiplication factor and PLL frequency range
after multiplication. The frequency multiplication formula is PLLCLK = (PLL reference clock *
PLL_NS) / (PLL_MS * PLL_FR).
PLL clock source
PLL clock source can be selected from HICK (8 MHz) and HEXT. PLL clock source is enabled and
becomes stable before enabling PLL configuration. The corresponding parameters of these two
clock sources in crm_pll_config function are as follows:
CRM_PLL_SOURCE_HICK
CRM_PLL_SOURCE_HEXT
PLL multiplication factor
PLL_MS: PLL pre-division factor that ranges from 1 to 15. It is used for pre-division of PLL
reference clock.
PLL_NS: PLL multiplication factor that ranges from 31 to 500. It is used for multiplication of the PLL
reference clock after PLL_MS pre-division.
PLL_FR: PLL post-division factor that can be set to 1, 2, 4, 8, 16 and 32. It is used for post-division
of the PLL reference clock after PLL_NS multiplication, and the post-divided clock is the PLL clock.
For details about these parameters, please refer to Section 4.1.1 in AT32F435/437 Series
Reference Manual.
2 MHz <= PLL reference clock / PLL_MS <= 16 MHz
500 MHz <= PLL reference clock * PLL_NS / PLL_MS <= 1200 MHz
After the PLL configuration is completed, enable PLL and wait until it becomes stable. For example,
select HEXT 8 MHz as the PLL clock source, and the implementation code of multiplying PLLCLK
to 288 MHz is as follows:
crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_4); /* Configure PLL parameters */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); /* Enable PLL clock source */

AT32F435/437 CRM Start Guide
2022.12.23 11 Ver 2.0.4
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) /* Wait until PLL stable flag is set
*/
{
}
3.2.5 Set bus frequency division
The bus frequnency division configuration includes SCLK to AHBCLK, AHBCLK to APB1CLK and
AHBCLK to APB2CLK. The implementation code of AHB bus (divided by 1), APB1/APB2 bus
(divided by 2) frequency division is as follow:
crm_ahb_div_set(CRM_AHB_DIV_1); /* SCLK/1 is used as AHB bus clock */
crm_apb2_div_set(CRM_APB2_DIV_2); /* AHBCLK/2 is used as APB2 bus clock */
crm_apb1_div_set(CRM_APB1_DIV_2); /* AHBCLK/2 is used as APB1 bus clock */
3.2.6 Switch system clock
The system clock has three main sources: HICK, HEXT and PLLCLK. Before switching the system
clock to any of the three clocks, the corresponding clock source must be stable.
Auto step-by-step switch mode
The automatic frequency switch is designed to ensure a smooth and stable switch of system
frequency. When the operational target is larger than 108 MHz, it is recommended to enable the
auto step-by-step switch mode. This function is mainly used when PLLCLK is selected as system
clock, which is enabled before switching the system clock and disabled after the switching is
completed. The implementation code is as follows:
crm_auto_step_mode_enable(TRUE); /* Enable step-by-step switch mode */
crm_auto_step_mode_enable(FALSE); /* Disbale step-by-step switch mode */
HICK
The HICK is used as system clock source by default after system reset. The HICK frequency can
be set to 8 MHz and 48 MHz in the code. As shown in Figure 1, the HICK frequency is set to 8 MHz
(by default) and can be set to 48 MHz.
The implementation code of setting the HICK 8 MHz as system clock is as follows:
crm_sysclk_switch(CRM_SCLK_HICK); /* Switch system clock source to HICK */
while(crm_sysclk_switch_status_get() != CRM_SCLK_HICK) /* Wait until the system clock switch status
becomes HICK */
{
}
The implementation code of setting the HICK 48 MHz as system clock is as follows:
crm_hick_sclk_frequency_select (CRM_HICK_SCLK_48MHZ); /* HICK frequency is selected to
be 48 MHz */
crm_sysclk_switch(CRM_SCLK_HICK); /* Switch system clock source to
HICK */
while(crm_sysclk_switch_status_get() != CRM_SCLK_HICK) /* Wait until the system clock
switch status becomes HICK */

AT32F435/437 CRM Start Guide
2022.12.23 12 Ver 2.0.4
{
}
HEXT
When the HEXT is used as system clock source, the system clock frequency depends on the actual
external clock frequency (range: 4~25 MHz). The implementation code of setting HEXT as system
clock source is as follows:
crm_sysclk_switch(CRM_SCLK_HEXT); /* Switch system clock source to HEXT */
while(crm_sysclk_switch_status_get() != CRM_SCLK_HEXT) /* Wait until the system clock switch status
becomes HEXT */
{
}
PLLCLK
When the PLLCLK is used as system clock source, the system clock frequency depends on the
actual PLL frequency multiplication and the maximum frequency. The implementation code of
setting PLLCLK as system clock source is as follows:
crm_sysclk_switch(CRM_SCLK_PLL); /* Switch system clock source to PLL */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) /* Wait until the system clock switch status
becomes PLL */
{
}
3.2.7 Update core frequency
The parameter “system_core_clock”indicating the system core frequency is reserved in the BSP
code framework to save the CPU core operating frequency. It is updated each time the system
clock is configured, so that peripherals can quickly get and use the current core operating
frequency. The implementation code is as follows:
system_core_clock_update(); /* Update system core frequency system_core_clock */
3.3 Example of clock configuration
In this example, the 8 MHz HEXT is used as clock source, and the HEXT is set to 288 MHz through
PLL multiplication and then used as system clock; AHB is not divided, and APB1/APB2 are divided
by 2. The system_clock_config function implementation code is as follows:
void system_clock_config(void)
{
crm_reset(); /* CRM reset */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); /* Set LDO 1.3V */
flash_clock_divider_set(FLASH_CLOCK_DIV_3); /* Divided by 3 when system clock
frequency is greater than 240 MHz */
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* Enable HEXT clock source */
while(crm_hext_stable_wait() == ERROR) /* Wait until HEXT clock beomes stable

AT32F435/437 CRM Start Guide
2022.12.23 13 Ver 2.0.4
*/
{
}
crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_4); /* Configure PLL: The HEXT is used
as PLL clock source; set multiplication parameters as follows: PLL_MS = 1, PLL_NS = 144 and PLL_FR = 4;
PLLCLK = 8 / 1 * 144 / 4 = 288 MHz */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); /* Enable PLL */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) /* Wait until PLL becomes stable */
{
}
crm_ahb_div_set(CRM_AHB_DIV_1); /* SCLK/1 is used as AHB bus clock */
crm_apb2_div_set(CRM_APB2_DIV_2); /* AHBCLK/2 is used as APB2 bus clock */
crm_apb1_div_set(CRM_APB1_DIV_2); /* AHBCLK/2 is used as APB1 bus clock */
crm_auto_step_mode_enable(TRUE); /* PLLCLK 240 MHz >108 MHz, enable
auto step-by-step switch mode */
crm_sysclk_switch(CRM_SCLK_PLL); /* Switch system clock source to PLL */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) /* Wait until the system clock switch
status becomes PLL */
{
}
crm_auto_step_mode_enable(FALSE); /* Switch completed, disable auto step-by-
step switch mode */
system_core_clock_update(); /* Update system core frequency */
}

AT32F435/437 CRM Start Guide
2022.12.23 14 Ver 2.0.4
4 Clock configuration tools
The New Clock Configuration is a graphical configuration tool developed by Artery for configuring
the clock of AT32 series MCUs, to help users have a better understanding of the clock path,
configure the required frequency and generate source files.
4.1 Environment requirement
Software
Windows7 and above
4.2 Installation
Software installation
Run the executable program AT32_New_Clock_Configuration.exe directly.
4.3 Function overview
This section mainly introduces basic operations of this tool. The startup interface and configuration
interface are shown below.
Figure 3. Startup interface

AT32F435/437 CRM Start Guide
2022.12.23 15 Ver 2.0.4
Figure 4. Configuration interface
4.4 Menu bar
The menu bar is shown below.
Figure 5. Menu bar
Project
New
Create a new configuration project
Open
Open an existing configuration project
Save
Saved the current configuration project
Language
English
Select English as the display language
Chinese
Select the simplified Chinese as the display language
Generate code
Configure the required clock path and clock frequency of the corresponding MCU series, then click
“Generate code” to select the storage path and generate the corresponding source file.
Help
New version download
Connect to network to download the latest version
Version
View the current version
4.5 Create configuration project
Double click to run the AT32_New_Clock_Configuration.exe; go to Project-->New in the startup
interface to create a new configuration project, and select the corresponding MCU series, as shown
in Figure 6.

AT32F435/437 CRM Start Guide
2022.12.23 16 Ver 2.0.4
Figure 6. Select MCU
Click on the drop-down box to select the corresponding MCU series; then click on “OK” to enter the
configuration interface.
4.6 Clock configuration interface
Users can configure the clock path and parameter and display the current clock frequency in the
clock configuration interface. Figure 7 shows the clock configuration for AT32F435 series MCU.
The clock configuration interface mainly contains four blocks, as shown below.
Figure 7. Clock configuration interface
1. Title: Display the corresponding MCU series of the current clock configuration project.
2. Configuration: Select and configure the clock path and parameters to meet application
requirements.
3. Output: Configure the clock output (CLKOUT).
4. SCLK: When the PLL is used as system clock, the SCLK field can be used as an input box of
required system clock frequency to automatically configure the multiplication factor reversely.
5. Result: Display the clock frequency of peripherals and peripherals on the bus.
1
2
3
4
5

AT32F435/437 CRM Start Guide
2022.12.23 17 Ver 2.0.4
Figure 8 illustrates the clock configuration block. The configuration process corresponds to MCU
clock tree, which may be slightly different for different MCU series. The clock path can be
configured by clicking on each checkbox according to the configuration process, as shown below.
Figure 8. Clock configuration block
1. ertc enable: drop-down box for enabling ertc clock code configuration.
2. ertcsel: checkbox for ERTC clock source; when the ERTC is enabled, click on this checkbox for
configuration.
3. ertcdiv: drop-down box; when ERTC is clocked by HEXT, click on this drop-down box to select
the division factor.
4. lext bypass: LEXT bypass enable.
5. hext: input box, which is 8 MHz by default; it can be modified according to the actual external
clock source (note: if other frequency value is set, the HEXT_VALUE in
inc/at32f435_437_conf.h in the corresponding BSP demo should be modified, or use the
at32f435_437_conf.h file generated by using tools).
6. hext bypass: HEXT bypass enable.
7. pllrcs: checkbox, which is used to configure PLL clocked by HEXT or HICK.
8. pll_ms: input box, which is used to set the PLL pre-division factor (range: 1~15) for the PLL
reference clock.
9. pll_ns: input box, which is used to set PLL multiplication factor (range: 31~500) for frequency
multiplication after PLL_MS pre-division.
10. pll_fr: drop-down box, which is used to set PLL post-division factor (1, 2, 4, 8, 16 and 32) for
frequency division after PLL_NS multiplication, and the post-divided clock is the PLL clock.
11. sclk select: checkbox, which is used to configure HEXT, PLL or HICK as the system clock.
12. sclk frequency: in case of forward configuration, it displays the configuration result of system
clock frequency; in case of being used as an input box, it can be used to input the required
frequency and then press “Enter” on keyboard, and then proper or approximate PLL parameters
are calculated according to the input value.
13. hick to sclk: checkbox, which is used to configure HICK 8 MHz or HICK 48 MHz as the system
clock when HICK is selected in the “sclk select” checkbox (note: if 48 MHz HICK is selected,
CLKOUT HICK frequency is also 48 MHz).
2
4
5
6
7
8
9
10
1
11
12
13
14
15
16
3
17

AT32F435/437 CRM Start Guide
2022.12.23 18 Ver 2.0.4
14. usbdiv: drop-down box, which is used to configure the division factor of PLL to USB when PLL
clock is selected as the USB clock source.
15. hick to usb: checkbox, which is used to configure USB clocked by PLL clock or HICK 48 MHz.
The USB clock configuration code is controlled by the “to usb” drop-down box. The USB clock
is required to be fixed 48 MHz; therefore, with the division factor in “usbdiv”, PLL multiplication
may not meet the requirement of USB 48 MHz.
16. USB enable: drop-down box for enabling USB clock code configuration.
17. USB clock frequency display: this field calculates and displays USB clock frequency in a real-
time manner. If the configured USB clock frequency is not equal to 48 MHz, the frequency value
will be displayed in red; if USB clock is not used, select “disable” in the drop-down box and no
message will be displayed (note: it is only used for USB clock frequency configuration; USB
peripheral clocks are enabled separately as needed).
4.7 Generate code
After clock configuration is completed, click on “Generate code”, select and confirm the code
storage path, and then two folders “inc” and “src” are generated to save the header file and source
file, respectively. These files can be used together with the project in BSP_V2.x.x. The generated
clock code file (at32f4xx_clock.c/ at32f4xx_clock.h/ at32f4xx_conf.h) can be used to replace the
corresponding file in the original BSP demo, and then call the system_clock_config in the main
function.

AT32F435/437 CRM Start Guide
2022.12.23 19 Ver 2.0.4
5 Notes
5.1 Modification of HEXT
The HEXT involved in demo and configuration tools in this application note is 8 MHz HEXT. If the
HEXT is not 8 MHz in actual application, the following aspects should be noted:
Code
1. Compile the code according to the actual external clock frequency and the configuration
process and method as described in this application note to set the required clock
configuration and clock path.
2. Modify the HEXT_VALUE in at32f4xx_conf.h file of the corresponding demo project according
to the actual HEXT clock frequency. For example, if the 12.288 MHz external crystal oscillator
or clock source is used, modify the at32f4xx_conf.h file as below.
#if !defined HEXT_VALUE
#define HEXT_VALUE ((uint32_t)12288000)
#endif
Tools
1. Input the actual frequency of external clock source to the HEXT input box, and then press
“Enter” on keyboard.
2. Configure the required clock path and clock frequency, and then generate code. Use the
generated clock code file (at32f4xx_clock.c/ at32f4xx_clock.h/ at32f4xx_conf.h) to replace the
corresponding file or function content in the original BSP demo, and then call the
system_clock_config in the main function.
5.2 Usage of tools
Notes on using the New Clock Configuration tool:
1. The clock configuration source file generated by the New Clock Configuration tool should be
used together with BSP_V2.x.x provided byArtery.
2. The clock configuration source file generated for the specific MCU series should be used in the
corresponding project only.
3. After modifying parameters in each input box, press “Enter” on keyboard.

AT32F435/437 CRM Start Guide
2022.12.23 20 Ver 2.0.4
6 Application case 1: Switch system clock
6.1 Introduction
Switch the system clock when the system is running.
6.2 Resources
1) Hardware
AT-START BOARD of the corresponding MCU series
2) Software
project\at_start_f435\examples\crm\sysclk_switch
6.3 Software design
1) Configuration process
Initialize buttons;
Configure PLL/4 to be output to CLKOUT;
Compile the code of configuring HICK to be 64 MHz through PLL multiplication;
Compile the code of configuring HEXT/2 to be 96 MHz through PLL multiplication.
2) Code
Main function code
int main(void)
{
system_clock_config(); /* Configure system mclock to be 288 MHz,
by default */
at32_board_init(); /* Initialize buttons and LEDs */
clkout_config(); /* Configure PLL/4 to be output to CLKOUT
*/
while(1)
{
if(at32_button_press() == USER_BUTTON) /* Check whether the button is pressed */
{
switch_system_clock(); /* Switch system clock between 64 MHz and
96 MHz alternately */
at32_led_toggle(LED4); /* Switch once, and LED4 toggles once */
}
at32_led_toggle(LED2); /* LED2 is the operating status indicator */
delay_ms(100); /* Delay for 100 ms */
}
}
Code of configuring HICK to be 64 MHz through PLL multiplication
static void sclk_64m_hick_config(void)
{
crm_reset(); /* CRM reset */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);