ARTERY AT32F435 Series Guide

AT32F435/437 CRM Start Guide
2022.12.23 1 Ver 2.0.4
AN0084
Application Note
AT32F435/437 CRM Start Guide
Introduction
This application note mainly introduces:
1. How to configure and modify the clock source code based on the BSP_ V2.x.x provided by Artery.
2. How to use the accessary clock configuration tools to set clock path and parameters to generate
and use the corresponding clock code.
Applicable products:
Part number
AT32F435xx
AT32F437xx

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Contents
1Overview................................................................................................................. 6
2Clock tree................................................................................................................ 7
3Code configuration and parsing .......................................................................... 8
3.1 Functions.................................................................................................................. 8
3.2 Clock configuration................................................................................................... 9
3.2.1 CRM Reset...................................................................................................................9
3.2.2 Set Flash clock division................................................................................................9
3.2.3 Clock source configuration...........................................................................................9
3.2.4 PLL configuration .......................................................................................................10
3.2.5 Set bus frequency division.........................................................................................11
3.2.6 Switch system clock...................................................................................................11
3.2.7 Update core frequency...............................................................................................12
3.3 Example of clock configuration............................................................................... 12
4Clock configuration tools ................................................................................... 14
4.1 Environment requirement.......................................................................................14
4.2 Installation.............................................................................................................. 14
4.3 Function overview ..................................................................................................14
4.4 Menu bar................................................................................................................ 15
4.5 Create configuration project ...................................................................................15
4.6 Clock configuration interface .................................................................................. 16
4.7 Generate code........................................................................................................ 18
5Notes..................................................................................................................... 19
5.1 Modification of HEXT.............................................................................................. 19
5.2 Usage of tools ........................................................................................................19
6Application case 1: Switch system clock.......................................................... 20
6.1 Introduction.............................................................................................................20

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6.2 Resources.............................................................................................................. 20
6.3 Software design...................................................................................................... 20
6.4 Test result...............................................................................................................22
7Application case 2: Clock fail detector.............................................................. 23
7.1 Introduction.............................................................................................................23
7.2 Resources.............................................................................................................. 23
7.3 Software design...................................................................................................... 23
7.4 Test result...............................................................................................................25
8Application case 3: Calculation of PLL parameters......................................... 26
8.1 Introduction.............................................................................................................26
8.2 Resources.............................................................................................................. 26
8.3 Software design...................................................................................................... 26
8.4 Test result...............................................................................................................27
9Revision history................................................................................................... 28

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List of tables
Table 1. Document revision history....................................................................................................28

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List of figures
Figure 1. Block diagram of clock .........................................................................................................7
Figure 2. Clock configuration process.................................................................................................9
Figure 3. Startup interface.................................................................................................................14
Figure 4. Configuration interface.......................................................................................................15
Figure 5. Menu bar.............................................................................................................................15
Figure 6. Select MCU.........................................................................................................................16
Figure 7. Clock configuration interface..............................................................................................16
Figure 8. Clock configuration block ...................................................................................................17

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1 Overview
As the necessary condition for the correct and efficient running of chips, proper clock configuration
is of great importance. The clock configuration of each AT32 series MCU may be slight different.
This application note mainly introduces how to use BSP_V2.x.x provided by Artery to perform clock
configuration of the corresponding AT32 MCU series.
The clock is configured with the following methods:
1. Manually write code to invoke the driver function interface in BSP to perform clock
configuration;
2. Use clock configuration tools to set and generate the corresponding source code.

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2 Clock tree
Before configuring the clock, it is necessary to have a comprehensive understanding of the clock
tree, with focuses on the clock source, frequency multiplication and system clock.
Figure 1. Block diagram of clock
Figure 1 contains the following key elements:
1) SCLKSEL: The system clock can be selected from HEXT, PLLCLK and HICK.
2) HEXT: It is a high-speed external oscillator that is connected externally to a 4~25 MHz crystal
or clock source.
3) HICK: It is a high-speed internal oscillator that is clocked by a high-speed RC, and the internal
frequency of the HICK clock is 48 MHz. The HICKDIV bit is used to select HICK (48 MHz) or
HICK/6 (if the HICK/6 is selected, the clock frequency is 8 MHz).
4) PLLCLK: PLL clock = PLL reference clock / PLL_MS * PLL_NS / PLL_FR.
5) PLL reference clock: It is determined by the PLLRCS bit, and it can be selected from HICK 8
MHz and HEXT.
USB
Divider
/1,1.5,
2,2.5,
3,3.5,
4,...,7
HICK_TO_USB
USB48M
To USB interface
/2,3,4,...31
LEXT RTCCLK
To RTC
LICK RC
40 kHz
RTCSEL[1:0]
LICK
To WDT
WDTCLK
CLKOUT1
Divider1
/1,2, ,5
Clock Output1 CLKOUT1
HICK
LEXT
HEXT
PLLCLK
CLKOUT1_SEL
ADC
Divider
/2,3,4,...,17
To ADC1,2,3 ADCCLK
Max.80 MHz
Peripheral
clock enable
To AHB peripheral/memory
MACTXCLK
MII_RMII_SEL
EMAC_MII_TX_CLK
EMAC_MII_RX_CLK
0
1
0
1
/2,20
MII_RMII_SEL
To EMAC
To EMAC
EMACRMIICLK
MACRXCLK
ACC
HICK RC
48 MHz
/6
HICK48M
HICKDIV
HICK
HEXT_OUT
HEXT_IN
HEXT OSC
4-25 MHz HEXT
HEXT
PLLRCS
PLLCLK
PLLCLK
LEXT OSC
32.768 kHz
LEXT_IN
LEXT_OUT
LEXT
LICK
HICK_TO_SCLK SCLKSEL
CFD
HICK8M
HEXT
HICK
SCLK
Max. 288 MHz
12S1/2/3/4 CLK
Peripheral
clock enable
AHB
Divider
/1,2...512
HCLK
Max.288MHz
CPU FCLK
/8 CPU SysTick
MII_RMII_SEL
To EMAC
CLKOUT1
Divider2
/1,2..512
CLKOUT2
Divider1
/1,2, ,5
Clock Output2 CLKOUT2
HEXT
PLLCLK
CLKOUT2_SEL1
CLKOUT2
Divider2
/1,2..512
SCLK
HICK
ADCCLK
USB48M
CLKOUT2_SEL2
LICK
LEXT
DVP_PCLK DVP_PCLK
/MS VCO
xNS
/FR
Peripheral
Clock enable
PCLK1/2
Max.144 MHz To APB1/2 peripheral
Max.288 MHz to TMRxCLK
Peripheral
clock enable
APB1/2
Divider
/1,2,4,8,16
x1,x 2

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3 Code configuration and parsing
This section introduces how to use library function interface to configure the clock.
3.1 Functions
The interface functions for hardware clock configuration in BSP of the corresponding MCU series
are encapsulated and can be called. Functions commonly used for clock configuration are listed
below. Refer to at32f435_437_crm.c/.h for details about parameters and return value of each
function.
/* CRM reset function, which resets clock configuration to default */
void crm_reset(void);
/* HEXT bypass enablel function */
void crm_hext_bypass(confirm_state new_state);
/* Status flag get function, such as the stable status flag of PLL/HEXT/HICK */
flag_status crm_flag_get(uint32_t flag);
/* Wait for HEXT clock to stable */
error_status crm_hext_stable_wait(void);
/* Clock source enable function, such as enable PLL/HEXT/HICK */
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
/* PLL configuration function for PLL clock source and PLL multiplication factor */
void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, uint16_t pll_ms, crm_pll_fr_type
pll_fr);
/* System clock switch function */
void crm_sysclk_switch(crm_sclk_type value);
/* Current system clock switch status get function */
crm_sclk_type crm_sysclk_switch_status_get(void);
/* Auto step-by-step system clock switch enable function; when PLL frequency > 108 MHz, enable auto step-by-
step switch before switching the system clock to PLL */
void crm_auto_step_mode_enable(confirm_state new_state);
/* HICK/6 configuration function, which is mainly used to select HICK 48 MHz as system clock and USB clock */
void crm_hick_divider_select(crm_hick_div_6_type value);
/* Frequency select function when HICK is selected as system clock; the frequency can be set to a fixed value (8
MHz) or divided by 6 (48 MHz divided by 6, depending on the HICK 6 divider configuration function) */
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
/* System clock to AHB clock divider configuration function */
void crm_ahb_div_set(crm_ahb_div_type value);
/* AHB clock to APB1 clock divider configuration function */
void crm_apb1_div_set(crm_apb1_div_type value);
/* AHB clock to APB2 clock divider configuration function */
void crm_apb2_div_set(crm_apb2_div_type value);

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3.2 Clock configuration
Figure 2 shows the clock configuration process.
Figure 2. Clock configuration process
Set Flash Clock Division
Clock Source Enable
PLL Configuration
Switch System Clock
Update Core Frequency
CRM Reset
Set Bus Frequency Division
3.2.1 CRM Reset
According to the configuration process, perform CRM reset firstly, which switches system clock to
HICK, and write the default value to other system clock configuration registers. The implementation
code of function calling is as follows:
crm_reset(); /* CRM reset */
3.2.2 Set Flash clock division
The relationship between Flash clock division factor and system clock frequency is shown below.
System Clock Frequency
Flash Clock Division
<= 240 MHz
FLASH_CLOCK_DIV_2
>240 MHz
FLASH_CLOCK_DIV_3
The implementation code is as follows.
flash_clock_divider_set(FLASH_CLOCK_DIV_3); /* Set Flash clock division factor to 3 */
3.2.3 Clock source configuration
The HEXT or HICK can be selected as the system clock source, which can also be used as for PLL
frequency multiplication. Before enabling PLL, enable the PLL reference clock source and wait until
it becomes stable.
HEXT
If HEXT is connected externally to an active clock, the HEXT bypass mode should be enabled. If
the crystal oscillator is used, the bypass mode should be disabled. The bypass mode is set before
enabling the HEXT clock source (disabled by default). The implementation code of enabling bypass
mode is as follows:
crm_hext_bypass(TRUE); /* HEXT bypass mode enable */

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Enable HEXT clock source and wait until HEXT clock becomes stable. The implementation code is
as follows:
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); /* Enable HEXT clock source */
while(crm_hext_stable_wait() == ERROR) /* Wait until HEXT clock becomes stable */
{
}
HICK
The HICK oscillator is clocked by a high-speed RC in the microcontroller. Enable HICK clock
source and wait until HICK clock becomes stable. The implementation code is as follows:
crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); /* Enable HICK clock source */
while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET) /* Wait until HICK stable flag is set */
{
}
3.2.4 PLL configuration
PLL configuration includes PLL clock source, PLL multiplication factor and PLL frequency range
after multiplication. The frequency multiplication formula is PLLCLK = (PLL reference clock *
PLL_NS) / (PLL_MS * PLL_FR).
PLL clock source
PLL clock source can be selected from HICK (8 MHz) and HEXT. PLL clock source is enabled and
becomes stable before enabling PLL configuration. The corresponding parameters of these two
clock sources in crm_pll_config function are as follows:
CRM_PLL_SOURCE_HICK
CRM_PLL_SOURCE_HEXT
PLL multiplication factor
PLL_MS: PLL pre-division factor that ranges from 1 to 15. It is used for pre-division of PLL
reference clock.
PLL_NS: PLL multiplication factor that ranges from 31 to 500. It is used for multiplication of the PLL
reference clock after PLL_MS pre-division.
PLL_FR: PLL post-division factor that can be set to 1, 2, 4, 8, 16 and 32. It is used for post-division
of the PLL reference clock after PLL_NS multiplication, and the post-divided clock is the PLL clock.
For details about these parameters, please refer to Section 4.1.1 in AT32F435/437 Series
Reference Manual.
2 MHz <= PLL reference clock / PLL_MS <= 16 MHz
500 MHz <= PLL reference clock * PLL_NS / PLL_MS <= 1200 MHz
After the PLL configuration is completed, enable PLL and wait until it becomes stable. For example,
select HEXT 8 MHz as the PLL clock source, and the implementation code of multiplying PLLCLK
to 288 MHz is as follows:
crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_4); /* Configure PLL parameters */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); /* Enable PLL clock source */