ARTERY AT32F421 Series User manual

AT32F421 Application note
2020.08.17 1 Rev 1.0.0
www.arterytek.com
AN0024
Getting started guide for AT32F421 series
Introduction
This user manual provides information on how to use AT32F421 MCU for project development in a
quickly manner.
Applicable products：
Part number
AT32F421xx

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Contents
1Development environment.................................................................................... 5
1.1 Debug tools.............................................................................................................. 5
1.2 Programming tools and software.............................................................................. 5
1.3 AT32 KEIL and IAR development environment.........................................................6
1.4 How to quickly replace SXX .....................................................................................8
2Enhanced functions of AT32F421 ........................................................................ 9
2.1 PLL output up to 120 MHz........................................................................................ 9
2.2 Security library protection......................................................................................... 9
2.3 System memory usea as extended block of main Flash memory............................. 9
2.4 Encryption (Read protection).................................................................................. 10
2.5 How to distinguish AT and other ICs.......................................................................13
2.5.1 Using the UID/PID to distinguish................................................................................13
2.5.2 Take 32-bit as the simplified unique UID code...........................................................14
3FAQs during download and compiling.............................................................. 15
3.1 The program enters Hard Fault Handler at startup.................................................15
3.1.1 Abnormal circumstances triggering Hardfault............................................................15
3.2 Error occurred during download .............................................................................15
3.2.1 Error: Flash Download failed –“Cortex-M4” ..............................................................15
3.2.2 No Debug Unit Device found......................................................................................15
3.2.3 RDDI-DAP Error.........................................................................................................15
3.2.4 ISP serial interface gets stuck during download........................................................15
3.3 AT32 resume download..........................................................................................16
4Revision history................................................................................................... 17

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List of tables
Table 1 Document revision history.....................................................................................................................17

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List of figures
Figure 1.AT32F421 evaluation board physical photo..........................................................................................5
Figure 2. Keil Debug option..................................................................................................................................6
Figure 3. Keil Debug settings...............................................................................................................................6
Figure 4. Keil Utilities option.................................................................................................................................6
Figure 5. IAR Debug option..................................................................................................................................7
Figure 6. IAR CMSIS-DAP option........................................................................................................................7
Figure 7. ISP enable read protection.................................................................................................................10
Figure 8. ISP disable read protection................................................................................................................. 11
Figure 9. ISP Multi-Port Programmer enable read protection ........................................................................... 11
Figure 10. ISP Multi-Port Programmer disable read protection.........................................................................12
Figure 11. Flash Download failed –“Cortex- 4” .................................................................................................15

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1 Development environment
MCU resources download address:
VisitArtery website: http://www.arterytek.com
1.1 Debug tools
At present,AT32F421 evaluation board are equipped withAT-Link-EZ debug tool, as shown in the
red circle on the left side of the figure below. It can also be dissembled and used separately with
other circuit boards, supporting IDE online debugging, online programming,USB-to-serial interface
and other functions.
Figure 1. AT32F421 evaluation board physical photo
1.2 Programming tools and software
AT programming tools and software: AT_Link /AT_Link_EZ / AT_Link_Pro/J-Link/ ICP/ISP.
Third-party programming tools:
−Xuanwei: https://xuanweikeji.taobao.com
−Maxwiz: www.maxwiz.com.cn
−ZLG: http://tools.zlg.cn/tools
−Amo:http://www.amomcu.cn

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1.3 AT32 KEIL and IAR development environment
For Keil compiling system, Keil 4.74, 5.23 or above is recommended;
The Pack in the Keil_AT32F4xx_AddOn.exe supports Keil_v4, and the Pack in the
Keil.AT32F4xx_DFP.1.3.2.pack supports Keil_v5. Both use “double-click” to complete one-click
installation.
When usingAT-Link-EZ in Keil environment, select “CMSIS-DAP debugger “in “Debug”.
Figure 2. Keil Debug option
In “Debug”, click on “Settings”to enter “cortex –M Target Driver Setup”, as shown in the figure
below:
Step 1: select “AT-Link-EZ-CMSIS-DAP”
Step 2: select “SW” at Port and tick “SWJ”
Step 3:ARM SWD debug module is identified.
Figure 3. Keil Debug settings
In “Utilities”, first uncheck the box “Use Debug Driver”(step 1), select “CMSIS-DAP Debugger
“from the drop-down menu(step 2), and then tick the box “Use Debug Driver” (automatic selection)
Figure 4. Keil Utilities option

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For IAR compiling system, IAR7.0, IAR6.1 or above is recommended;
The Pack in the IAR_AT32F4xx_AddOn.exe supports IAR_v6 and IAR_v7, and uses “double click”
to finish one-click installation.
When usingAT-Link-EZ in IAR environment, select “CMSIS-DAP”in “Debugger”.
Figure 5. IAR Debug option
Figure 6. IAR CMSIS-DAP option

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1.4 How to quickly replace SXX
Step 1: Based on peripheral specifications, Flash capacity, SRAM size, etc., de-solder
SXX32F103 and replace it with the corresponding AT32F421 part no
Step 2: Download the latest BSP and PACK file ofAT32F421 series
Step 3: Update the tool startup file:
A. Project files: device connections and Flash memory bootloader. these files are provided
with the latest version of toolchain that supports AT32F421x devices. For more details,
please refer to the relevant tool documentation.
B. Linker configuration and vector table location files: these files are developed following
the CMSIS standard and are included in the AT32F421 library install package (Under
Libraries\CMSIS\CM4\DeviceSupport).
Step 4:Add theAT32F421 library source files to the application sources
A. Replace the sxx32f0xx_conf.h file of your application with the at32f4xx_conf.h provided
in the AT32F421 library.
B. Replace the existing sxx32f0xx_it.c/ sxx32f0xx _it.h files of your application with the
at32f4xx_it.c/ at32f4xx_it _it.h provided in theAT32F421 library.
C. Replace the existing system_sxx32f0xx.c/ system_sxx32f0xx.h files of your application
with the system_at32f4xx.c/ system_at32f4xx.h files provided in the AT32F421 library.
Step 5: Update the part of application code that uses the RCC, PWR, GPIO, FLASH,ADC
and RTC drivers.
Step 6: For other issues, refer to migration guide from SXX32F030 to AT32F421_V1.x.x
Step 7: If the program still cannot run normally after following the above steps, please refer to
other chapters in this document, or contact your agent for assistance
Note: AT32F421 library comes with a rich set of example codes (more than 100 in total) demonstrating how
to use the different peripherals (under AT32F4xx_StdPeriph_Lib_V1.x.x\Project\AT_START_F421\Examples)

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2 Enhanced functions of AT32F421
2.1 PLL output up to 120 MHz
The AT32F421 series embedded a PLL that can output up to 120 MHz clock. The AT32F421 and
SXX32 F030 series have the same clock sources and configuration procedures. However, there
are some differences related to the product voltage range, PLL configuration, maximum frequency
and Flash wait state configuration.
Thanks to the CMSIS layer, these differences are hidden from the application code; the user only
has to replace the system_sxx32f0xx.c file by system_at32f4xx.c file. This file provides an
implementation of SystemInit() function used to configure the microcontroller system at start-up
and before switching to the main() program.
For more information, refer to AT32F421 PLL setting example:
AT32F4xx_StdPeriph_Lib_V1.x.x\Project\AT_START_F421\Templates中system_at32f4xx.c的
static void SetSysClockTo120M(void) function
2.2 Security library protection
At present, more and more microcontroller applications need to use complex algorithms and
middleware solutions, therefore, how to protect the core algorithms and intellectual property codes
(IP-Code) developed by software solutions providers has become a very important subject in the
microcontroller applications.
In response to this important demand,AT32F403Aseries provide the security library area function to
prevent important IP-Code from being modified or read by end-user programs to achieve protection.
For more information, please refer to
AT32F421 Security Library Application Note
AT32F4xx_StdPeriph_Lib_Vx.x.x\Utilities\AT32F421_SLIB_Demo
2.3 System memory used as extended block of main Flash memory
By default, system memory is used as BOOT mode to store the original factory-programmed
startup code. However, theAT32F421 series has been tasked with new features in which the
system memory can also be used as an extension area of Flash memory (AP mode) to store the
user-defined codes. The system memoryAP mode can only be set once and is irreversible. After
reset, the original system memory BOOT mode cannot be restored. For more information, refer to
AN0066_configure the system memory as main Flash extension block.

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2.4 Encryption (Read protection)
Read protection, commonly referred to as “encryption”, acts on the entire Flash storage area.Once
the read protection is set in the Flash, the embedded Flash storage area can only be read through
the normal execution of the program instead of JTAG or SWD. When the read protection is
disabled using ISP/ICP tool, the chip will erase the Flash.
ISP/ICP tool can be used to enable/disable read protection as follows:
ICP tool
Read protection: “Target”---“read protection”---“enable protection”
Disable read protection: “Target”---“read protection”---“disable read protection”
Artery ISP Programmer tool
Read protection: “enable/disable protection”---“enable---read protection”---“Next”---“Yes”, and
the program is encrypted.
Figure 7. ISP enable read protection

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Disable read protection: “enable/disable protection”---“disable-read protection”---“Next”—
“Yes”, and then the Flash can be unencrypted.
Figure 8. ISP disable read protection
Artery ISP Multi-Port Programmer
Read protection: “enable/disable protection”---“enable-read protection”---click on “Begin”, and
then the program is encrypted.
Figure 9. ISP Multi-Port Programmer enable read protection

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Disable read protection: “enable/disable protection”--- “disable-read protection”—click on
“Begin”, then the Flash is unencrypted. The read protection cannot be disabled by the erase
operation.
Figure 10. ISP Multi-Port Programmer disable read protection

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2.5 How to distinguish AT and other ICs
2.5.1 Using the UID/PID to distinguish
Read the Cortex-M series CPU ID to distinguish M0, M3 and M4 core.
Read PID and UID to distinguish
cortex_id = *(uint32_t *)0xE000ED00; //read cortex part number
if((cortex_id == 0x410FC240) || (cortex_id == 0x410FC241))
{
printf("This chip is Cortex-M4.\r\n");
}
else
{
printf("This chip is Other Device.\r\n");
}
/* Read the base address of AT32 MCU PID/UID */
#define DEVICE_ID_ADDR1 0x1FFFF7F3
#define DEVICE_ID_ADDR2 0xE0042000
/* AT32F421 MCU type table */
const uint64_t AT32_MCU_ID_TABLE[] =
{
0x0000000270050242,
0x00000002700502CA,
…
};
/* Obtain PID/UID */
ID[0] = *(int*)DEVICE_ID_ADDR1;
ID[1] = *(int*)(DEVICE_ID_ADDR2+3);
ID[2] = *(int*)(DEVICE_ID_ADDR2+2);
ID[3] = *(int*)(DEVICE_ID_ADDR2+1);
ID[4] = *(int*)(DEVICE_ID_ADDR2+0);
/* Combine PID/UID */
AT_device_id = ((uint64_t)ID[0]<<32)|((uint64_t)ID[1]<<24)|((uint64_t)ID[2]<<16) |
((uint64_t)ID[3]<<8)|((uint64_t)ID[4]<<0);

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Note: there are multiple ID codes in the AT32F4xx microcontrollers, they assemble the acquired ID
information into a 64-bit data to distinguish which type of MCU is.
PROJECT ID: the access address is 0x1FFF F7F3 [7:0], which defines the project model of Artery MCU.
DEVICE ID: the access address is 0xE004 2000 [31:0], which defines the device model of MCU.
2.5.2 Take 32-bit as the simplified unique UID code
Whentheusersdonotwant toread96-bitUID (baseaddress 0x1FFFF7E8, 0x1FFFF7EC,0x1FFF
F7F0), only use 32-bit as the simplified unique UID code, they can just read [87:79] [33:28][16:0]
bits.
/* Judge AT32 MCU */
for(i=0;i<sizeof(AT32_MCU_ID_TABLE)/sizeof(AT32_MCU_ID_TABLE[0]);i++)
{
if(AT_device_id == AT32_MCU_ID_TABLE[i])
{ printf("This chip is AT32F4xx.\r\n");
}
else
{
printf("This chip is Other Device.\r\n");
}
}

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3 FAQs during download and compiling
3.1 The program enters Hard Fault Handler at startup
3.1.1 Abnormal circumstances triggering Hardfault
The SRAM used exceeds the MCU SRAM size
Access data out of boundary
System clock setting out of specification
3.2 Error occurred during download
3.2.1 Error: Flash Download failed –“Cortex-M4”
An error pops up during KEIL emulation or download:
Figure 11. Flash Download failed –“Cortex- 4”
The possible reasons are as follows:
Read protection is enabled: you need to first disable MCU read protection before download;
Select a wrong Flash file algorithm or not to load the Flash file algorithm: you need add a
correct Flash file algorithm at FlashDownload
sLib is enabled: you need to disable sLib before download
J-Link driver version is too old: the driver 6.20C or above is recommended.
3.2.2 No Debug Unit Device found
The download port is occupied, for example, ICP is connecting to the target device.
JTAG/SWD connection error or no connection.
3.2.3 RDDI-DAP Error
Disable the JTAG/SWD PIN, please refer to “3.3 AT32 resume download for solutions”.
3.2.4 ISP serial interface gets stuck during download
When the ISP serial interface is used to download, it occasionally gets stuck, causing the PC not
to release the serial port.
Solutions:
Power supply is not stable;
Use a better USB-to-serial interface tool, such as CH340 chip.

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3.3 AT32 resume download
When usingAT32F421, users may not be able to download the program after the following
operations:
After the JTAG/SWD PIN is disabled, the program cannot be downloaded and the JTAG/SWD
device cannot be found.
After entering Standby mode, the program cannot be downloaded and JTAG/SWD device cannot
be found.
Here we provide the solutions in KEIL and IAR environment:
Solution 1: switch boot mode
Switch the boot mode to Boot[1:0]=01b or Boot[1:0]=11b, and press the reset button to resume
download. In the same way, ISP can also resume download.
Solution 2: ICP tool andAT-Link-EZ
AT-Link-EZ is specially designed forAT32, so ICP and AT-Link-EZ can use resume download.

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4 Revision history
Table 1. Document revision history
Date
Revision
Changes
2020.8.17
1.0.0
Initial release

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