ARTERY AT32F403 Series Specification sheet

AT32F403 Application note
2020.8.20 1
AN0020
Introduction
This user manual provides information on how to use AT32F403 MCU for project development in a
quickly manner.
Applicable products:
Part number
AT32F403
Get started guide for AT32F403 series
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Contents
Development environment...........................................................................................................................5
1.1. Set up AT32 development environment .......................................................................................................5
1.1.1.Debug tools..........................................................................................................................................5
1.1.2.Programming tools and software.........................................................................................................5
1.1.3.AT32 KEIL and IAR development environment...................................................................................5
1.1.4.How to quickly replace SXX ..............................................................................................................10
1.2. Enhanced functions of AT32F403 ..............................................................................................................10
1.2.1 PLL setting when the clock is greater than 72 MHz ..........................................................................10
1.2.2 How to enable FPU (Hardware Floating Point Unit)..........................................................................11
1.2.3 Configuration for AT32F403 ZW/NZW Flash and embedded SRAM size.........................................13
1.2.4 Encryption (read protection and external Flash encrypted) ..............................................................19
1.2.4.1 Read protection................................................................................................................................19
1.2.4.2 Encryption of external Flash.............................................................................................................22
1.2.5 How to distinguish AT and other IC in the program...........................................................................24
1.2.5.1 UID/PID identify..................................................................................................................................24
1.2.5.2 Using 32-bit as an unique UID code to identify ..................................................................................24
2FAQs during download and compiling....................................................................................................25
2.1. The program enters Hard Fault Handler at startup....................................................................................25
2.1.1 Abnormal circumstances that cause program to enter Hardfault......................................................25
2.2. Error occurred during the download...........................................................................................................25
2.2.1 Error: Flash Download failed –“Cortex-M4”......................................................................................25
2.2.2 No Debug Unit Device found.............................................................................................................25
2.2.3 RDDI-DAP Error ................................................................................................................................26
2.2.4 ISP serial interface gets stuck during download................................................................................26
2.2.5 AT32 resume download.....................................................................................................................26
3Revision history............................................................................................................................................27
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List of tables
Table 1 .Selection of BSP and PACK................................................................................................................. 8
Table 2 . Documentation revision history......................................................................................................... 27
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List of figures
Figure 1. AT-Link physical picture ...................................................................................................................... 5
Figure 2. Install the Keil.AT32F4xx_DFP........................................................................................................... 6
Figure 3. Install the Keil_AT32F4xx_AddOn...................................................................................................... 6
Figure 4. Keil Debug option................................................................................................................................ 6
Figure 5. Keil Debug settings............................................................................................................................. 6
Figure 6. Keil Utilities option............................................................................................................................... 7
Figure 7. Install the IAR_AT32F4xx_AddOn...................................................................................................... 7
Figure 8. IAR Debug option................................................................................................................................ 7
Figure 9. IAR CMSIS-DAP option...................................................................................................................... 8
Figure 10. SXX Flash wait bits........................................................................................................................... 9
Figure 11. Enable FPU in Keil environment......................................................................................................11
Figure 12. Enable FPU in Keil environment......................................................................................................11
Figure 13.Add a code to enable FPU in Keil environment...............................................................................11
Figure 14. Enable FPU in IAR environment..................................................................................................... 12
Figure 15.Add a code to enable FPU in IAR environment.............................................................................. 12
Figure 16. ICP tool option bytes select SRAM size......................................................................................... 14
Figure 17. ICP tool option bytes select SRAM size......................................................................................... 14
Figure 18. ISP tool option bytes select SRAM size ......................................................................................... 15
Figure 19. ISP Multi-Port Programmer option bytes operation........................................................................ 15
Figure 20. ISP enable read protection ............................................................................................................. 19
Figure 21. ISP disable read protection............................................................................................................. 20
Figure 22. ISP Multi-Port Programmer enable read protection ....................................................................... 20
Figure 23. ISP Multi-Port Programmer disable read protection....................................................................... 21
Figure 24. SPIM encryption operation using ICP tool...................................................................................... 22
Figure 25. SPIM encryption operation through ISP tool .................................................................................. 22
Figure 26. SPIM encryption operation by ISP Multi-Port Programmer............................................................ 23
Figure 29.Add a code to enable FPU.............................................................................................................. 25
Figure 30. Flash Download failed –“Cortex- 4” during download ................................................................... 25
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Development environment
MCU resources download address：
VisitArtery website: http://www.arterytek.com
1.1. Set up AT32 development environment
1.1.1. Debug tools
At present, the debug tools supported by AT32F403 series are AT-Link/J-Link.
AT-Link is shown in the figure below.
Figure 1. AT-Link physical picture
1.1.2. Programming tools and software
AT programming tools and software：AT-Link/AT-Link-Pro / J-Link, ICP/ISP
Third-party programming tools:
−Xuanwei: https://xuanweikeji.taobao.com
−Maxwiz: www.maxwiz.com.cn
−ZLG: http://tools.zlg.cn/tools
−Amo: http://www.amomcu.cn
1.1.3. AT32 KEIL and IAR development environment
①For Keil compiling system, it is recommended to use Keil 4.74, 5.23 or above.
You need to install the Pack and add theAT32 MCU part numbers in the Keil. The pack is
available from Artery website.
For Keil_v5 version, Keil.AT32F4xx_DFP needs to be installed;
For Keil_v4 version, Keil_AT32F4xx_AddOn is needed;
By default, Keil installation path can be automatically recognized, if failed or incorrect, you need
to manually select Keil installation path.
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Figure 2. Install the Keil.AT32F4xx_DFP
Figure 3. Install the Keil_AT32F4xx_AddOn
WhenAT-Link is used in Keil environment, select “CMSIS-DAP debugger “in “Debug”.
Figure 4. Keil Debug option
Click on “Settings” in the “Debug” to enter “cortex –M Target Driver Setup” dialogue box shown
below:
1. Select “AT-Link-CMSIS-DAP”;
2. For Port, select “SW”, then tick “SWJ”
3. ARM SWD debug module is recognized.
Figure 5. Keil Debug settings
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In “Utilities”, you need to first uncheck the “Use Debug Driver” option, select the “CMSIS-DAP
Debugger” from the drop-down menu, and then tick the “Use Debug Driver” option (you need to
first uncheck, and then tick it)
Figure 6. Keil Utilities option
②For IAR compiling system, it is recommended to use IAR 7.0, IAR 6.1 or above.
You need to install the Pack and add theAT32 MCU part numbers in the LAR. The pack is
available from Artery website.
The IAR_AT32F4xx_AddOn needs to be installed. By default, the LAR installation path can be
automatically recognized, if failed or incorrect, you need to manually select LAR installation
path.
Figure 7. Install the IAR_AT32F4xx_AddOn
WhenAT-Link is used in IAR environment, select “CMSIS-DAP” in “Debugger”.
Figure 8. IAR Debug option
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Figure 9. IAR CMSIS-DAP option
③At present, in IAR compiling environment, the Pack does not support bank 3 operations
(external SPI Flash via SPIM interface); If bank3 is needed, please compile it in the Keil
environment.
④Selection of BSP and PACK (six scenarios are described as below)
Table 1. Selection of BSP and PACK
No.
BSP/Pack used
Whether to use
AT32F403 new features
Solutions
1
AT32F403 BSP/Pack
Y
Refer to the BSP related routines
2
SXX32F103
BSP/Pack
N
1.When the HSERDY flag becomes 1, add a delay of
2mS;
2.When the system clock status switches from
SYSCLKSTS to PLL, add a delay of 200uS;
3. Modify the corresponding program according to
3.4 peripheral differences in the migration guide from
SXXF103 to AT32F403.
3
SXX32F103 register
operations
N
1.When the HSERDY flag becomes 1, add a delay of
2mS;
2.When the system clock status switches from
SYSCLKSTS to PLL, add a delay of 200uS;
3. Modify the corresponding program according to
3.4 peripheral differences in the migration guide from
SXXF103 to AT32F403.
4
SXX32F103 BSP +
AT32 Pack
N
1.When HSERDY flag becomes 1, add a delay of
2mS;
2.When the system clock status switches from
SYSCLKSTS to PLL, add a delay of 200uS;
3.Modify the FPU settings;
4. Modify the corresponding program according to
3.4 peripheral differences in the migration guide from
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SXXF103 to AT32F403.
5
SXX32F103 register
operations
Y
1.When the HSERDY flag becomes 1, add a delay of
2mS;
2.When the system clock status switches from
SYSCLKSTS to PLL, add a delay of 200uS;
3. Modify the corresponding program according to
3.4 peripheral differences in the migration guide from
SXXF103 to AT32F403.
6
SXX32F103
BSP/Pack
Y
1.When the HSERDY flag becomes 1, add a delay of
2mS;
2.When the system clock status switches from
SYSCLKSTS to PLL, add a delay of 200uS;
3. Modify the corresponding program according to
3.4 peripheral differences in the migration guide from
SXXF103 to AT32F403.
For detailed information on BSP and Pack, please refer to AT32F4xx BSP & Pack Application note,
which is located in the AT32F4xx_StdPeriph_Lib_V1.x.x folder available from Artery website.
Note: becauseAT32F403has different Flash mechanism from SXX, there is no need to set the following two
Flash wait bits for AT products:
Figure 10. SXX Flash wait bits
This means that the SXX Flash needs to wait for 1-2 clocks at high speed to fetch instructions,
but AT has no such restriction.
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1.1.4. How to quickly replace SXX
Step 1: De-solder SXX32F103 and replace it with the corresponding AT32F403 part
according to the peripheral specifications, Flash size, SRAM size, etc.
Step 2:Add at least 2ms of delay after reading RCC->CR.HSERDY, and add at least 200us
of delay after reading RCC->CR.PLLRDY
Step 3: Download SXX32F103 HEX file or BIN file using Artery ICP, ISP or KEIL/ IAR
Step 4: If necessary, download information other than SXX32F103HEX file or BIN file or
perform system calibration
Step 5: Check if the program can run normally
Step 6: For other issues, please refer to Migration guide from SXX32F103 to AT32F403
Step 7: If the program still cannot work normally after following the above steps, please refer
to other chapters in this document, or contact your agent for assistance.
Note: Since AT32F403 applies a flexible memory extension design, the internal Flash
memory has a non-zero wait area, which will cause some SXX32F103 programs to run poorly
on AT32F403.
For how to improve operating efficiency, please refer to AN0004_Performance_Optimization_
Optimization V1.0.x.pdf.
1.2. Enhanced functions of AT32F403
1.2.1 PLL setting when the clock is greater than 72 MHz
AT32F403 embeds a PLL that can output up to 200 MHz clock, the setting is slightly different.
Thus the PLLRANGE register must be configured depending on the output frequency, that is,
PLLRANGE=1 when greater than 72 MHz, and PLLRANGE=0 when less than or equal to 72
MHz.
SXX32F103 PLL setting example: (HSE=8MHz, PLL=72MHz)
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
AT32F403 PLL setting example: (HSE=8MHz)
#define RCC_CFG_PLLRANGE_LE72MHZ ((uint32_t)0x00000000)
/*!< When PLL frequency is less than or equal to 72MHz */
#define RCC_CFG_PLLRANGE_GT72MHZ ((uint32_t)0x80000000)
/*!< When PLL frequency is greater than 72MHz */
PLL=72MHz:
RCC->CFG|=(uint32_t)(RCC_CFG_PLLRC_HSE| RCC_CFG_PLLMULT9 |
RCC_CFG_PLLRANGE_LE72MHZ);
PLL=200MHz：
RCC->CFG|=(uint32_t)(RCC_CFG_PLLRC_HSE|RCC_CFG_PLLMULT25
|RCC_CFG_PLLRANGE_GT72MHZ);
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