NXP Semiconductors LPC5410x User manual

UM10850
LPC5410x User manual
Rev. 2.4 — 13 September 2016 User manual
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Keywords LPC5410x, ARM Cortex-M4, ARM Cortex-M0+, microcontroller, sensor
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Abstract LPC5410x User Manual

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LPC5410x User manual
Revision history
Rev Date Description
2.4 20160913 •Updated Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124)
bit description”: Changed the system clock rates of the following:
–2 system clocks flash access time (for system clock rates up to 24 MHz).
–3 system clocks flash access time (for system clock rates up to 48 MHz).
–4 system clocks flash access time (for system clock rates up to 72 MHz).
–5 system clocks flash access time (for system clock rates up to 84 MHz).
–Added 0x5, 6 system clocks flash access time (for system clock rates up to 100 MHz).
2.3 20160906 •Added text and a remark to Section 30.1 “How to read this chapter”.
•Added a remark to Section 30.3 “General description”.
•Added text and a remark to Section 30.4 “API description”.
•Added Table 466 “Power API calls in LPCOpen power library”.
•Renamed section 30.4.1 to Section 30.4.1 “Chip_POWER_SetPLL”.
•Renamed section 30.4.2 to Section 30.4.2 “Chip_POWER_SetVoltage”.
•Deleted Param0: mode and Low power mode; was section 30.4.2.1.
•Added Section 30.4.3 “Chip_POWER_EnterPowerMode”.
•Updated Section 30.5 “Functional description”.
2.2 20160331 •Removed Section 4.5.51: Device ID1 register values and moved Table 89 “Device ID1 register
values”to section Section 4.5.50 “Device ID1 register”.
•Removed IrDA mode from Section 21.5 “General description”in Chapter 21 “LPC5410x USARTs
(USART0/1/2/3)”.
•Updated Table 307 “USART Configuration register (CFG, offset 0x00) bit description”. Removed
IOMODE from the table.
•Removed the section: IrDA communication in Chapter 21 “LPC5410x USARTs (USART0/1/2/3)”.
•Added the sentence to Section 22.5 “General description”: Set the RXIGNORE bit to only transmit
data and not read the incoming data. Otherwise, the transmit halts when the receiver buffer is full.
•Added the sentence to Table 328 “SPI Transmitter Data and Control register (TXDATCTL, offset
0x18) bit description”, bit 22, RXIGNORE: The SPI collects receive data, according to SPI clocking,
unless RXIGNORE is set; 0: The SPI transmit halts when the receive data FIFO is full.
•Added the sentence to Section 22.7.7 “Data stalls”: The transmitter will be stalled until data is read
from the receive FIFO. Use the RXIGNORE control bit setting, to avoid the need to read the
received data.

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2.1 20151218 •Added Table 89 “Device ID1 register values”.
•Added text to Section 4.5.47.1 “CPU Control register”: The user can assign Cortex-M0+ to be the
master CPU via this register if needed after it is brought out of reset by Cortex-M4.
•Added text to Section 4.6.3 “Brown-out detection”: On the LPC5410x, the BOD is enabled by
default after power-up. At this time the BOD is set to the lowest value (1.5v) with no factory trimming
applied. In the BOD block the interrupt portion is turned off and only the reset portion is on. After
POR/BOD resets, the BootROM takes over and applies the factory BOD trim value so that the trip
points become accurate. See the LPC5410x data sheet for BOD interrupt/reset voltage levels in the
BOD static characteristics.
•Added section Section 12.5.7 “Channel chaining”.
•Updated Figure 53 “System FIFO conceptual block diagram”.
•Updated description of 15:12,TIMEOUT VALUE; Specifies the maximum time value for timeout at
the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1 (clocks of wdt_clk).
See Table 383 “Configuration register for USARTn (CFGUSART[0:3], address offset
[0x1000:0x1300]) bit description”.
•Updated the values in the sentence: TimeoutValue can be any value from 2 to 15. This gives a
maximum timeout range of 2 counts (too small to be useful) at the bottom end, up to 15 * 32,768
(491,520) counts at the upper end. See Section 24.5.7.1 “Receiver Timeout”
•Updated text in Table 468 “set_voltage routine”: Param1: desired frequency (in Hz); was: Param1:
desired frequency (in MHz).
•Removed text from Section 5.2 “General description”, list 3:
...or for monitoring analog inputs (comparators and internal voltage reference and temperature
sensor via one of the comparators).
•Removed comparator from Section 13.5 “General description”: This provides an extremely powerful
control tool - particularly when the SCT inputs and outputs are connected to other on-chip
resources (ADC triggers, other timers etc.) in addition to general-purpose I/O.
•Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and
set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.4.2
“Programming Deep-sleep mode”.
•Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and
set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.5.2
“Programming Power-down mode”.
•Added registers, DIRSET0, DIRCLR0, DIRNOT0. See Table 134 “Register overview: GPIO port
(base address 0x1C00 0000)” and Section 9.5.10 “GPIO port direction set registers”, Section 9.5.11
“GPIO port direction clear registers”, and Section 9.5.12 “GPIO port direction toggle registers”.
•Added note to Table 223 “SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit
description” and Table 224 “SCT DMA 1 request register (DMAREQ1, address 0x5000 4060) bit
description”.
•Added remark to Section 4.5.37.5.1 “System PLL spread spectrum control register 0”: If the 32 kHz
RTC oscillator is used as the reference input to the PLL, then use fixed values SELI=1, SELP=6
and SELR=0, instead of applying the above rules. These values reduce the PLL loop bandwidth to
combat the effect of reference oscillator jitter on the PLL output signal.
•In Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit
description” replaced offset in table title to address 0x4000 0124.
Revision history …continued
Rev Date Description

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2.1 •Added text to Section 17.2 “Features”: 24-bit interrupt timer clocked from CPU clock.
•Added address to Section 31.3.7.3 “RAM used by IAP command handler”’: Flash programming
commands use the top 32 bytes of on-chip SRAM0, 0x0200 FFE0 - 0x0200 FFFF (see Section
2.1.1 for details of the SRAM configuration). The maximum stack usage in the user allocated stack
space is 128 bytes and grows downwards.
•Removed Receiver Idle from Section 21.2 “Features” and replaced with Transmitter Idle.
•Added the text receiver to List item • “A receiver timeout feature (for USART and SPI) provides a
means to get data left for a time in a FIFO that has not reached its threshold to be transferred.” in
Section 24.3 “Features”.
•Added List item • “Timeouts: The watchdog oscillator must run for the UART and SPI timeout
counter to work. Enable the watchdog oscillator via the PDRUNCFG register (Table 72).” to the
Section 24.2 “Basic configuration”.
•Added text, The source of the timeout clock is the watchdog oscillator with a nominal frequency of
500 kHz to Section 24.5.7.1 “Receiver Timeout”, and Section 24.5.15.1 “Receiver Timeout”.
•Added text to Section 21.5 “General description”: The USART receiver timeout feature can also be
used to identify the USART receiver idle state. Set the bit TIMEOUTCONTONEMPTY in the
respective CFGUSART register to 1 to allow the timeout to flag idle state of the USART peripheral.
•Fixed the reset value of MSTTIME (Master timing configuration); was 0x77, now 0x56. See
Table 340 “Register overview: I2C0/1/2 (register base addresses 0x4009 4000 (I2C0), 0x4009 8000
(I2C1), 0x4009 C000 (I2C2))”.
•Added the Flash Management Registers FMSSTART and FMSSTOPUpdated to Chapter 28
“LPC5410x Flash signature generator”.
•Typographic errors have been corrected and minor pieces of information added or clarified
throughout the document.
2.0 20150410 •Registers supporting use of dual processors on LPC54102 devices has been added to the Syscon
chapter.
•A Power Management chapter has been added.
•Some pins in the Pin description chapter have the type changed to Z for open drain pins.
•A section has been added to the ADC chapter describing how to configure sample times for
different conversion configurations.
•The ADC operating speed is increased to 5 Ms/s.
•Updated Section 4.5.33 “Flash configuration register” text and Table 62.
•Typographic errors have been corrected and minor pieces of information added or clarified
throughout the document.
1.1 20141121 •In the NVIC chapter, the bit numbers for the priority register fields have been corrected.
•In the Syscon chapter, a functional description section has been added following the register
descriptions to provide additional information about some functions.
•The SCTimer/PWM chapter has been revised to better explain the function.
•Description of the ISP-AP interface and commands is added to the Debug chapter.
•References to Timer 0, 1, 2, 3, and 4 have been updated to use the terminology of the Standard
counter/timers chapter (CT32B0, 1, 2, 3, 4).
•Typographic errors have been corrected and minor pieces of information added or clarified
throughout the document.
Revision history …continued
Rev Date Description

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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1.0 20141104 Initial release of the LPC5410x User Manual
Revision history …continued
Rev Date Description

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1.1 Introduction
The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications.
these devices include an optional ARM Cortex-M0+ coprocessor, 104 KB of on-chip
SRAM, 512 KB on-chip flash, five general-purpose timers, one State-Configurable Timer
with PWM capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate Timer
(MRT), a Windowed Watchdog Timer (WWDT), four USARTs, two SPIs, three Fast-mode
plus I2C-bus interfaces with high-speed slave mode, and one 12-bit 5 Msamples/sec
ADC.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. The
Cortex-M4 is the Cortex-M4 with the inclusion of the 32-bit Floating Point Unit.
The ARM Cortex-M0+ coprocessor available on some devices is an energy-efficient and
easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. The
Cortex-M0+ coprocessor offers up to 100 MHz performance with a simple instruction set
and reduced code size.
Refer to LPC5410x data sheets for complete details on specific products and
configurations.
1.2 Features
•Dual processor core: ARM Cortex-M4 and ARM Cortex-M0+ included for LPC54102
devices. Cortex-M4 only is present on LPC54101 devices.
•ARM Cortex-M4 CPU:
–ARM Cortex-M4 processor, running at a frequency of up to 100 MHz.
–Floating Point Unit (FPU) and Memory Protection Unit (MPU).
–The CPU can operate at frequencies of up to 100 MHz.
–ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
–Non-maskable Interrupt (NMI) with a selection of sources.
–Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints. Includes Serial
Wire Output for enhanced debug capabilities.
–System tick timer.
•ARM Cortex-M0+ CPU (present on LPC54102 devices):
–ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz (using the
same clock as the Cortex-M4).
–The CPU can operate at frequencies of up to 100 MHz.
–ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
UM10850
Chapter 1: LPC5410x Introductory information
Rev. 2.4 — 13 September 2016 User manual

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Chapter 1: LPC5410x Introductory information
–Non-maskable Interrupt (NMI) with a selection of sources.
–Serial Wire Debug (SWD) with 4 breakpoints and 2 watchpoints.
–System tick timer.
•On-Chip memory:
–Up to 512 KB on-chip flash programming memory with flash accelerator and 256
Byte page write and erase.
–Up to 104 KB total SRAM composed of:
–Up to 96 KB contiguous main SRAM.
–An additional 8 KB SRAM.
•ROM API support:
–Flash In-Application Programming (IAP) and In-System Programming (ISP).
–Power Control API.
•Serial interfaces:
–Four USART interfaces with synchronous mode and 32 kHz mode for wake-up
from Deep-sleep and Power-down modes. The USARTs include a FIFO buffer, and
share a fractional baud-rate generator.
–Two SPI interfaces, each with 4 slave selects and flexible data configuration. The
SPIs include a FIFO buffer. Able to wake up the device from Deep-sleep and
Power-down modes when used in slave mode.
–Three I2C-bus interfaces supporting fast mode and Fast-mode Plus with data rates
of up to 1Mbit/s and with multiple address recognition and monitor mode. Each
I2C-bus interface also supports High Speed Mode as a slave. The slave function is
able to wake up the device from Deep-sleep and Power-down modes.
•Digital peripherals:
–DMA controller with 22 channels and 20 programmable triggers, able to access all
memories and DMA-capable peripherals.
–Up to 50 General-Purpose I/O (GPIO) pins. Most GPIOs have configurable
pull-up/pull-down resistors, open-drain mode, and input inverter.
–GPIO registers are located on AHB for fast access.
–Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,
falling or both input edges.
–Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
–CRC engine.
•Timers
–Five 32-bit standard general purpose timers/counters, four of which support up to 4
capture inputs and 4 compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests. The fifth timer
does not have external pin connections and may be used for internal timing
operations.
–One State Configurable Timer/PWM (SCTimer/PWM) 6 input and 8 output
functions (including capture and match). Inputs and outputs can be routed to/from
external pins and internally to/from selected peripherals. Internally, the SCT
supports 13 captures/matches, 13 events and 13 states.

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Chapter 1: LPC5410x Introductory information
–32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including Deep power-down, with 1 ms resolution.
–Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
–Windowed Watchdog timer (WWDT).
–Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be
used to wake up the device from low power modes.
–Repetitive interrupt timer for general purpose use and use with debug
time-stamping.
•Analog peripheral: 12-bit ADC with 12 input channels and with multiple internal and
external trigger inputs and sample rates of up to 5 MS/s. The ADC supports two
independent conversion sequences.
•Clock generation:
–12 MHz internal RC oscillator, factory trimmed for accuracy, that can optionally be
used as a system clock.
–External clock input for up 24 MHz.
–Internal, low-power, watchdog oscillator (WDOSC) with a nominal frequency of 500
kHz.
–32 kHz low-power RTC oscillator.
–System PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency external clock. May be run from the internal RC oscillator, the
external clock input CLKIN, or the RTC oscillator.
–Clock output function with divider that can reflect many internal clocks.
–Frequency measurement unit for measuring the frequency of any on-chip or
off-chip clock signal.
•Power control:
–Integrated PMU (Power Management Unit) to minimize power consumption.
–Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode.
–Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI,
and I2C peripherals.
–Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes
from the RTC alarm.
–Power-On Reset (POR).
–Brownout detect.
•JTAG boundary scan supported.
•Unique device serial number (128-bit) for identification.
•Single power supply 1.62 V to 3.6 V.
•Operating temperature range of -40°C to +105°C.
•Available in a 3.288 x 3.288 mm WLCSP49 package and LQFP64 package.

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Chapter 1: LPC5410x Introductory information
1.3 Block diagram
Grey-shaded blocks show peripherals provide DMA request lines or that can provide hardware triggers for DMA transfers.
Fig 1. Block diagram
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Chapter 1: LPC5410x Introductory information
1.4 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is
dedicated for data access (D-code). The use of two core buses allows for simultaneous
operations if concurrent operations target different devices.
A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in
a flexible manner that optimizes performance by allowing peripherals on different slaves
ports of the matrix to be accessed simultaneously by different bus masters. More
information on the multilayer matrix can be found in Section 2.1.3. Connections in the
multilayer matrix are shown in Figure 1.
APB peripherals are connected to the AHB matrix via two APB buses using separate
slave ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller, and also for peripherals on the
asynchronous bridge to have a fixed clock that does not track the system clock.
1.5 ARM Cortex-M4 processor
The Cortex-M4 is a general purpose 32-bit microprocessor, which offers high performance
and very low power consumption. The Cortex-M4 offers a Thumb-2 instruction set, low
interrupt latency, interruptible/continuable multiple load and store instructions, automatic
state save and restore for interrupts, tightly integrated interrupt controller, and multiple
core buses capable of simultaneous accesses.
A 3-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
Information about Cortex-M4 configuration options can be found in Chapter 32.
1.6 ARM Cortex-M0+ processor (present on LPC54102 devices)
The Cortex-M0+ is a general purpose 32-bit microprocessor with extremely low power
consumption. The Cortex-M0+ includes the bulk of the Thumb instruction set and a small
subset of Thumb-2 Instructions. The Cortex-M0+ has a 2-stage pipeline in order to
decrease power consumption, and includes a 32-cycle multiplier.
Information about Cortex-M0+ configuration options can be found in Chapter 32.

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2.1 General description
The LPC5410x incorporates several distinct memory regions. Figure 2 shows the overall
map of the entire address space from the user program viewpoint following reset.
The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals.
Each peripheral is allocated 16 KB of space, simplifying the address decoding.
The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control,
are located on the private peripheral bus.
2.1.1 Main SRAM
The parts contain up to a total 96 KB of contiguous, on-chip static RAM memory (this is in
addition to SRAM2 as noted in the next section below, so the total device SRAM can be
up to 104 KB). For each SRAM configuration, the SRAM is divided into two blocks:
SRAM0 (up to 64 KB) and SRAM1 (up to 32 KB). The bottom 8 KB of SRAM can be
enabled separately in order to allow saving data with minimal power usage during
Power-down mode. The remaining portion of SRAM0 and the entire SRAM1 can also be
disabled or enabled individually in the SYSCON block to save power. See Section 4.5.22
“AHB Clock Control register 0”and Section 4.5.38 “Power Configuration register”.
2.1.1.1 SRAM2
An additional on-chip static RAM memory, SRAM2, is available that is not contiguous to
SRAM0 and SRAM1. This can be used, for example, as the location for the program
stack, or any other use. SRAM2 can be disabled or enabled in the SYSCON block to save
power. See Section 4.5.22 “AHB Clock Control register 0”and Section 4.5.38 “Power
Configuration register”.
2.1.1.2 SRAM usage notes
Although always contiguous on all LPC5410x devices, SRAM0 and SRAM1 are placed on
different AHB matrix ports. This allows user programs to potentially obtain better
performance by dividing RAM usage among the 2 ports. For example, simultaneous
access to SRAM0 by the CPU and SRAM1 by the system DMA controller does not result
in any bus stalls for either master.
UM10850
Chapter 2: LPC5410x Memory mapping
Rev. 2.4 — 13 September 2016 User manual
Table 1. Main SRAM configuration
SRAM0 SRAM1
(total main SRAM = up to 96 KB)
Size Up to 64 KB Up to 32 KB
Address range •Always begins at 0x0200 0000.
•Continues to 0x0200 FFFF (for full 64
KB).
•Begins at end of SRAM0, 0x0201 0000 when SRAM0
is a full 64 KB.
•Ends at 0x0201 7FFF for 32 KB SRAM1 with 64 KB
SRAM0.
Power Control
(via Power API) •First 8 KB is has a separate power switch.
•Remaining SRAM0 has a single power
switch.
•All of SRAM1 has a single power switch.

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Chapter 2: LPC5410x Memory mapping
Generally speaking, the CPU will read or write all peripheral data at some point, even
when all such data is read from or sent to a peripheral by DMA. So, minimizing stalls is
likely to involve putting data to/from different peripherals in RAM on each port.
Alternatively, sequences of data from the same peripheral could be alternated between
RAM on each port. this could be helpful if DMA fills or empties a RAM buffer, then signals
the CPU before proceeding on to a second buffer. the CPU would then tend to access the
data while the DMA is using the other RAM.

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Chapter 2: LPC5410x Memory mapping
2.1.2 Memory mapping
The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.
Fig 2. Memory mapping
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User manual Rev. 2.4 — 13 September 2016 14 of 464
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Chapter 2: LPC5410x Memory mapping
2.1.3 AHB multilayer matrix
The LPC5410x uses a multi-layer AHB matrix to connect the CPU buses and other bus
masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals that are on different slave ports of the matrix to be accessed simultaneously
by different bus masters. Figure 1 shows details of the potential matrix connections.
2.1.4 Memory Protection Unit (MPU)
The Cortex-M4 processor has a memory protection unit (MPU) that provides fine grain
memory control, enabling applications to implement security privilege levels, separating
code, data and stack on a task-by-task basis. Such requirements are critical in many
embedded applications.
The MPU register interface is located on the private peripheral bus and is described in
detail in Ref. 1 “Cortex-M4 TRM”.

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User manual Rev. 2.4 — 13 September 2016 15 of 464
3.1 How to read this chapter
Available interrupt sources may vary with specific LPC5410x device type.
3.2 Features
•Nested Vectored Interrupt Controller that is an integral part of each CPU.
•Tightly coupled interrupt controller provides low interrupt latency.
•Controls system exceptions and peripheral interrupts.
•The NVIC of the Cortex-M4 supports:.
–37 vectored interrupts.
–8 programmable interrupt priority levels with hardware priority level masking.
–Vector table offset register VTOR.
–Software interrupt generation.
•The Cortex- M0+ (present on LPC54102 devices) supports: the first 32 interrupts.
–32 vectored interrupts.
–4 programmable interrupt priority levels with hardware priority level masking.
–Vector table offset register VTOR.
•Support for NMI from any interrupt (see Section 4.5.3).
3.3 General description
The tight coupling to the NVIC to the CPU allows for low interrupt latency and efficient
processing of late arriving interrupts.
3.3.1 Interrupt sources
Table 2 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. The interrupt number does not imply any
interrupt priority.
See Ref. 1 “Cortex-M4 TRM”and Ref. 2 “Cortex-M0+ TRM”for detailed descriptions of
the NVIC and the NVIC registers.
UM10850
Chapter 3: LPC5410x Nested Vectored Interrupt Controller
(NVIC)
Rev. 2.4 — 13 September 2016 User manual
Table 2. Connection of interrupt sources to the NVIC
Interrupt Name Description Flags
0 WDT Windowed watchdog timer interrupt WARNINT - watchdog warning interrupt
1 BOD BOD interrupt BODINTVAL - BOD interrupt level
2 (reserved) - -
3 DMA DMA interrupts Interrupt A and interrupt B, error interrupt

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)
4 GINT0 GPIO group 0 interrupt Enabled pin interrupts
5 PIN_INT0 Pin interrupt 0 or pattern match engine slice 0 int PSTAT - pin interrupt status
6 PIN_INT1 Pin interrupt 1or pattern match engine slice 1 int PSTAT - pin interrupt status
7 PIN_INT2 Pin interrupt 2 or pattern match engine slice 2 int PSTAT - pin interrupt status
8 PIN_INT3 Pin interrupt 3 or pattern match engine slice 3 int PSTAT - pin interrupt status
9 UTICK Micro-tick Timer interrupt INTR
10 MRT Multi-rate timer interrupt Global MRT interrupts: GFLAG0, 1, 2, 3
11 CT32B0 Standard counter/timer CT32B0 interrupt Match and Capture interrupts
12 CT32B1 Standard counter/timer CT32B1 interrupt Match and Capture interrupts
13 CT32B2 Standard counter/timer CT32B2 interrupt Match and Capture interrupts
14 CT32B3 Standard counter/timer CT32B3 interrupt Match and Capture interrupts
15 CT32B4 Standard counter/timer CT32B4 interrupt Match and Capture interrupts
16 SCT0 State configurable timer interrupt EVFLAG SCT event
17 UART0 USART0 interrupt See Table 310.
18 UART1 USART1 interrupt Same as USART0
19 UART2 USART2 interrupt Same as USART0
20 UART3 USART3 interrupt Same as USART0
21 I2C0 I2C0 interrupt See Table 348.
22 I2C1 I2C1 interrupt Same as I2C0
23 I2C2 I2C2 interrupt Same as I2C0
24 SPI0 SPI0 interrupt See Table 325.
25 SPI1 SPI1 interrupt Same as SPI0
26 ADC0_SEQA ADC0 sequence A completion. See Table 428.
27 ADC0_SEQB ADC0 sequence B completion. See Table 428.
28 ADC0_THCMP ADC0 threshold compare and error. See Table 428.
29 RTC RTC alarm and wake-up interrupts See Table 276.
30 (reserved) - -
31 MAILBOX Mailbox interrupt (present on LPC54102 devices) Mailbox Interrupt
The following interrupts are supported only on the Cortex-M4
32 GINT1 GPIO group 1 interrupt Enabled pin interrupts
33 PIN_INT4 Pin interrupt 4 or pattern match engine slice 4 int PSTAT - pin interrupt status
34 PIN_INT5 Pin interrupt 5 or pattern match engine slice 5 int PSTAT - pin interrupt status
35 PIN_INT6 Pin interrupt 6 or pattern match engine slice 6 int PSTAT - pin interrupt status
36 PIN_INT7 Pin interrupt 7 or pattern match engine slice 7 int PSTAT - pin interrupt status
39:37 (reserved) - -
40 RIT Repetitive Interrupt Timer RITINT; masked compare interrupt
Table 2. Connection of interrupt sources to the NVIC
Interrupt Name Description Flags

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NXP Semiconductors UM10850
Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)
3.4 Register description
The NVIC registers are located on the ARM private peripheral bus.
[1] This register is not available for the Cortex-M0+.
Table 3. Register overview: NVIC (base address 0xE000 E000)
Name Access Address
offset Description Reset value Refer- ence
ISER0 R/W 0x100 Interrupt Set Enable Register 0. This register allows enabling interrupts
and reading back the interrupt enables for peripheral functions. 0Table 4
ISER1 R/W 0x104 Interrupt Set Enable Register 1. See ISER0 description. 0 Table 5
ICER0 R/W 0x180 Interrupt Clear Enable Register 0. This register allows disabling
interrupts and reading back the interrupt enables for peripheral functions. 0Table 6
ICER1 R/W 0x184 Interrupt Clear Enable Register 1. See ISER0 description. 0 Table 7
ISPR0 R/W 0x200 Interrupt Set Pending Register 0. This register allows changing the
interrupt state to pending and reading back the interrupt pending state for
peripheral functions.
0Table 8
ISPR1 R/W 0x204 Interrupt Set Pending Register 1. See ISPR0 description. 0 Table 9
ICPR0 R/W 0x280 Interrupt Clear Pending Register 0. This register allows changing the
interrupt state to not pending and reading back the interrupt pending
state for peripheral functions.
0Table 10
ICPR1 R/W 0x284 Interrupt Clear Pending Register 1. See ICPR0 description. 0 Table 11
IABR0 [1] RO 0x300 Interrupt Active Bit Register 0. This register allows reading the current
interrupt active state for specific peripheral functions. 0Table 12
IABR1 [1] RO 0x304 Interrupt Active Bit Register 1. See IABR0 description. 0 Table 13
IPR0 R/W 0x400 Interrupt Priority Register 0. This register contains the 3-bit priority fields
for interrupts 0 to 3. 0Table 14
IPR1 R/W 0x404 Interrupt Priority Register 1. This register contains the 3-bit priority fields
for interrupts 4 to 7. 0Table 15
IPR2 R/W 0x408 Interrupt Priority Register 2. This register contains the 3-bit priority fields
for interrupts 8 to 11. 0Table 16
IPR3 R/W 0x40C Interrupt Priority Register 3. This register contains the 3-bit priority fields
for interrupts 12 to 15. 0Table 17
IPR4 R/W 0x410 Interrupt Priority Register 4. This register contains the 3-bit priority fields
for interrupts 16 to 19. 0Table 18
IPR5 R/W 0x414 Interrupt Priority Register 5. This register contains the 3-bit priority fields
for interrupts 20 to 23. 0Table 19
IPR6 R/W 0x418 Interrupt Priority Register 6. This register contains the 3-bit priority fields
for interrupts 24 to 27. 0Table 20
IPR7 R/W 0x41C Interrupt Priority Register 7. This register contains the 3-bit priority fields
for interrupts 28 to 31. 0Table 21
IPR8 R/W 0x420 Interrupt Priority Register 8. This register contains the 3-bit priority fields
for interrupts 32 to 35. 0Table 22
IPR9 R/W 0x424 Interrupt Priority Register 9. This register contains the 3-bit priority fields
for interrupts 36 to 39. 0Table 23
IPR10 R/W 0x428 Interrupt Priority Register 10. This register contains the 3-bit priority field
for interrupt 40. 0Table 24
STIR [1] WO 0xF00 Software Trigger Interrupt Register, allows software to generate
interrupts. -Table 25

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)
3.4.1 Interrupt Set-Enable Register 0 register
The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are enabled via the ISER1
register (Section 3.4.2). Disabling interrupts is done through the ICER0 and ICER1
registers (Section 3.4.3 and Section 3.4.4).
[1] Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 4. Interrupt Set-Enable Register 0 register
Bit Name Value Function
0 ISE_WDT [1] Watchdog Timer interrupt enable.
1 ISE_BOD [1] BOD interrupt enable.
2 - - Reserved. Read value is undefined, only zero should be written.
3 ISE_DMA [1] DMA interrupt enable.
4 ISE_GINT0 [1] GPIO group 0 interrupt enable.
5 ISE_PINT0 [1] Pin interrupt / pattern match engine slice 0 interrupt.
6 ISE_PINT1 [1] Pin interrupt / pattern match engine slice 1 interrupt.
7 ISE_PINT2 [1] Pin interrupt / pattern match engine slice 2 interrupt.
8 ISE_PINT3 [1] Pin interrupt / pattern match engine slice 3 interrupt.
9 ISE_UTICK [1] Micro-Tick Timer interrupt enable.
10 ISE_MRT [1] Multi-Rate Timer interrupt enable.
11 ISE_CT32B0 [1] Standard counter/timer CT32B0 interrupt enable.
12 ISE_CT32B1 [1] Standard counter/timer CT32B1 interrupt enable.
13 ISE_CT32B2 [1] Standard counter/timer CT32B2 interrupt enable.
14 ISE_CT32B3 [1] Standard counter/timer CT32B3 interrupt enable.
15 ISE_CT32B4 [1] Standard counter/timer CT32B4 interrupt enable.
16 ISE_SCT0 [1] SCT0 interrupt enable.
17 ISE_USART0 [1] USART0 interrupt enable.
18 ISE_USART1 [1] USART1 interrupt enable.
19 ISE_USART2 [1] USART2 interrupt enable.
20 ISE_USART3 [1] USART3 interrupt enable.
21 ISE_I2C0 [1] I2C0 interrupt enable.
22 ISE_I2C1 [1] I2C1 interrupt enable.
23 ISE_I2C2 [1] I2C2 interrupt enable.
24 ISE_SPI0 [1] SPI0 interrupt enable.
25 ISE_SPI1 [1] SPI1 interrupt enable.
26 ISE_ADC0SEQA [1] ADC0 sequence A interrupt enable.
27 ISE_ADC0SEQB [1] ADC0 sequence B interrupt enable.
28 ISE_ADC0THOV [1] ADC0 threshold and error interrupt enable.
29 ISE_RTC [1] Real Time Clock (RTC) interrupt enable.
30 - - Reserved. Read value is undefined, only zero should be written.
31 ISE_MAILBOX [1] Mailbox interrupt enable (present on LPC54102 devices).

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NXP Semiconductors UM10850
Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)
3.4.2 Interrupt Set-Enable Register 1 register
The ISER1 register allows enabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Disabling interrupts is done through the
ICER0 and ICER1 registers (Section 3.4.3 and Section 3.4.4).
[1] Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
3.4.3 Interrupt Clear-Enable Register 0
The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are disabled via the ICER1
register (Section 3.4.4). Enabling interrupts is done through the ISER0 and ISER1
registers (Section 3.4.1 and Section 3.4.2).
3.4.4 Interrupt Clear-Enable Register 1 register
The ICER1 register allows disabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Enabling interrupts is done through the
ISER0 and ISER1 registers (Section 3.4.1 and Section 3.4.2).
3.4.5 Interrupt Set-Pending Register 0 register
The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or
for reading the pending state of those interrupts. The remaining interrupts can have their
pending state set via the ISPR1 register (Section 3.4.6). Clearing the pending state of
interrupts is done through the ICPR0 and ICPR1 registers (Section 3.4.7 and
Table 5. Interrupt Set-Enable Register 1 register
Bit Name Value Function
0 ISE_GINT1 [1] GPIO group 1 interrupt enable.
1 ISE_PINT4 [1] Pin interrupt / pattern match engine slice 4 interrupt.
2 ISE_PINT5 [1] Pin interrupt / pattern match engine slice 5 interrupt.
3 ISE_PINT6 [1] Pin interrupt / pattern match engine slice 6 interrupt.
4 ISE_PINT7 [1] Pin interrupt / pattern match engine slice 7 interrupt.
7:5 - - Reserved. Read value is undefined, only zero should be written.
8 ISE_RIT [1] Repetitive Interrupt Timer interrupt enable.
31:9 - - Reserved. Read value is undefined, only zero should be written.
Table 6. Interrupt Clear-Enable Register 0
Bit Name Function
31:0 ICE_... Peripheral interrupt disables. Bit numbers match ISER0 registers (Table 4). Unused bits are reserved.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Table 7. Interrupt Clear-Enable Register 1 register
Bit Name Function
31:0 ICE_... Peripheral interrupt disables. Bit numbers match ISER1 registers (Table 5). Unused bits are reserved.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.

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Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC)
Section 3.4.8).
3.4.6 Interrupt Set-Pending Register 1 register
The ISPR1 register allows setting the pending state of the second group of peripheral
interrupts, or for reading the pending state of those interrupts. Clearing the pending state
of interrupts is done through the ICPR0 and ICPR1 registers (Section 3.4.7 and
Section 3.4.8).
3.4.7 Interrupt Clear-Pending Register 0 register
The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts,
or for reading the pending state of those interrupts. The remaining interrupts can have
their pending state cleared via the ICPR1 register (Section 3.4.8). Setting the pending
state of interrupts is done through the ISPR0 and ISPR1 registers (Section 3.4.5 and
Section 3.4.6).
3.4.8 Interrupt Clear-Pending Register 1 register
The ICPR1 register allows clearing the pending state of the second group of peripheral
interrupts, or for reading the pending state of those interrupts. Setting the pending state of
interrupts is done through the ISPR0 and ISPR1 registers (Section 3.4.5 and
Section 3.4.6).
Table 8. Interrupt Set-Pending Register 0 register
Bit Name Function
31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER0 registers (Table 4). Unused bits are reserved.
Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
Table 9. Interrupt Set-Pending Register 1 register
Bit Name Function
31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER1 registers (Table 5). Unused bits are reserved.
Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
Table 10. Interrupt Clear-Pending Register 0 register
Bit Name Function
31:0 ICP_... Peripheral interrupt pending clear. Bit numbers match ISER0 registers (Table 4). Unused bits are reserved.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
Table 11. Interrupt Clear-Pending Register 1 register
Bit Name Function
31:0 ICP_... Peripheral interrupt pending clear. Bit numbers match ISER1 registers (Table 5). Unused bits are reserved.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.