ARTERY AT32F421C8T7 User manual

AT32F421 Series Reference Manual
2022.11.11 Page 1 Rev 2.02
ARM®-based 32-bit Cortex®-M4 MCU with 16 to 64 KB Flash, sLib, 10 timers,
ADC, 7 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU
−120 MHz maximum frequency, with a
Memory Protection Unit (MPU), single-cycle
multiplication and hardware division
−DSP instructions
Memories
−16 to 64 KBytes of internal Flash memory
−4 Kbytes of boot code area used as a
Bootloader or as a general instruction/data
memory (one-time-configured)
−sLib: configurable part of main Flash set as a
library area with code executable but
secured, non-readable
−8 to 16 KBytes of SRAM
Clock, reset and power control
−2.4 V ~ 3.6 V application supply and I/Os
−Power-on reset (POR)/ low-voltage reset
(LVR), and power voltage monitor (PVM)
−4 to 25 MHz crystal (HEXT)
−Internal 8 MHz factory-trimmed clock (HICK),
accuracy 1% at TA=25 °C, 2 % at TA=-40 to
+105 °C
−Internal 40 kHz RC oscillator
−32 kHz crystal oscillator (LEXT)
Low power
−Sleep, Deepsleep, and Standby modes
1 x 12-bit A/D converter (up to 15 input
channels)
−Conversion range: 0 V to 3.6 V
1 x COMP, 5 x external input channels
and 1 x internal reference voltage
channel
2 x operational amplifiers
DMA: 5-channel DMA controller
−Peripherals supported: timers, ADC, I2S,
SPI, I2C and USART
Debug mode
−Serial wire debug (SWD) and JTAG
Up to 39 fast GPIOs
−All mappable to external interrupt vectors
−Almost5 V-tolerant
−All fast I/Os, registersaccessible with fAHBspeed
Up to 10 Timers (TMR)
−1 x 16-bit 7-channel advanced timer,6-channel
PWM output with dead-time generator and
emergencystop
−5 x16-bit timers, each with 4 IC/OC/PWMor
pulse counter and encoder input
−1 x 16-bit basic timer
−2x Watchdog timers (WDTand WWDT)
−SysTick timer: 24-bitdowncounter
ERTC: enhanced RTC
Up to 7 communication interfaces
−2 x I2C interfaces (SMBus/PMBus support)
−2x USARTs/UART (ISO7816interface,LIN,
IrDA and modem control)
−2 x SPIs, both with I2Sinterfacemultiplexed
−Infrared transmitter
CRC Calculation Unit
96-bit ID (UID)
Packaging
−LQFP48 7 x 7 mm
−LQFP32 7 x 7 mm
−QFN32 5 x 5 mm
−QFN32 4 x 4 mm
−QFN28 4 x 4mm
−TSSOP20 6.5 x 4.4 mm
List of Models
Internal Flash
Model
64 KBytes
AT32F421C8T7, AT32F421K8T7
AT32F421K8U7, AT32F421K8U7-4
AT32F421F8P7, AT32F421G8U7,
AT32F4212C8T7
32 KBytes
AT32F421C6T7, AT32F421K6T7
AT32F421K6U7, AT32F421K6U7-4
AT32F421F6P7, AT32F421G6U7
16 KBytes
AT32F421C4T7, AT32F421K4T7
AT32F421K4U7, AT32F421K4U7-4
AT32F421F4P7, AT32F421G4U7

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2022.11.11 Page 2 Rev 2.02
Contents
1System architecture...................................................................... 25
1.1 System overview..........................................................................27
1.1.1 ARM CortexTM-M4 processor........................................................ 27
1.1.2 Bit band...................................................................................... 27
1.1.3 Interrupt and exception vectors .................................................... 29
1.1.4 System Tick (SysTick) ................................................................. 31
1.1.5 Reset ......................................................................................... 31
1.2 List of abbreviations for registers ..................................................33
1.3 Device characteristics information.................................................33
1.3.1 Flash memory size register .......................................................... 33
1.3.2 Device electronic signature.......................................................... 33
2Memory resources ........................................................................ 34
2.1 Internal memory address map.......................................................34
2.2 Flash memory..............................................................................35
2.3 SRAM memory.............................................................................35
2.4 Peripheral address map................................................................36
3Power control (PWC)..................................................................... 39
3.1 Introduction .................................................................................39
3.2 Main Features .............................................................................39
3.3 POR/LVR ....................................................................................40
3.4 Power voltage monitor (PVM)........................................................40
3.5 Power domain..............................................................................41
3.6 Power saving modes ....................................................................41
3.7 PWC registers .............................................................................43
3.7.1 Power control register (PWC_CTRL) ............................................ 43
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 44
3.7.3 Power control register 2 (PWC_CTRL2)........................................ 44
4Clock and reset manage (CRM) ..................................................... 45
4.1 Clock ..........................................................................................45

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4.1.1 Clock sources ............................................................................. 45
4.1.2 System clock............................................................................... 46
4.1.3 Peripheral clock .......................................................................... 46
4.1.4 Clock fail detector ....................................................................... 47
4.1.5 Auto step-by-step system clock switch.......................................... 47
4.1.6 Internal clock output.................................................................... 47
4.1.7 Interrupts.................................................................................... 47
4.2 Reset..........................................................................................47
4.2.1 System reset............................................................................... 47
4.2.2 Battery powered domain reset...................................................... 48
4.3 CRM registers .............................................................................48
4.3.1 Clock control register (CRM_CTRL).............................................. 49
4.3.2 Clock configuration register (CRM_CFG) ...................................... 50
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 51
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 52
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) ........................ 53
4.3.6 AHB peripheral clock enable register (CRM_AHBEN) .................... 53
4.3.7 APB2 peripheral clock enable register (CRM_APB2EN) ................. 54
4.3.8 APB1 peripheral clock enable register (CRM_APB1EN) ................. 55
4.3.9 Battery powered domain control register (CRM_BPDC).................. 56
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 56
4.3.11 AHB peripheral reset register (CRM_AHBRST) ............................. 57
4.3.12 PLL configuration register (CRM_PLL).......................................... 57
4.3.13 Additional register (CRM_MISC1)................................................. 58
4.3.14 Additional register (CRM_MISC2)................................................. 59
5Embedded Flash memory controller (FLASH) ............................... 60
5.1 FLASH introduction......................................................................60
5.2 Flash memory operation ...............................................................62
5.2.1 Unlock/lock ................................................................................. 62
5.2.2 Erase operation........................................................................... 62
5.2.3 Programming operation................................................................ 64
5.2.4 Read operation ........................................................................... 65
5.3 Main Flash memory extension area ...............................................65
5.4 User system data area ................................................................. 66

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5.4.1 Unlock/lock ................................................................................. 66
5.4.2 Erase operation........................................................................... 66
5.4.3 Programming operation................................................................ 68
5.4.4 Read operation ........................................................................... 69
5.5 Flash memory protection ..............................................................69
5.5.1 Access protection........................................................................ 69
5.5.2 Erase/program protection............................................................. 70
5.6 Read access................................................................................70
5.7 Special functions .........................................................................70
5.7.1 Security library settings ............................................................... 70
5.7.2 Boot memory used as memory extension area .............................. 71
5.7.3 CRC verify .................................................................................. 72
5.8 Flash memory registers ................................................................72
5.8.1 Flash performance select register (FLASH_PSR) .......................... 73
5.8.2 Flash unlock register (FLASH_UNLOCK) ...................................... 73
5.8.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 73
5.8.4 Flash status register (FLASH_STS) .............................................. 74
5.8.5 Flash control register (FLASH_CTRL)........................................... 75
5.8.6 Flash address register (FLASH_ADDR) ........................................ 76
5.8.7 User system data register (FLASH_USD)...................................... 76
5.8.8 Erase/program protection status register (FLASH_EPPS) .............. 76
5.8.9 Flash security library status register 0 (SLIB_STS0)...................... 77
5.8.10 Flash security library status register1 (SLIB_STS1)....................... 77
5.8.11 Security library password clear register (SLIB_PWD_CLR) ............ 78
5.8.12 Security library additional status register (SLIB_MISC_STS).......... 78
5.8.13 Flash CRC address register (FLASH_CRC_ARR) .......................... 78
5.8.14 Flash CRC control register (FLASH_CRC_CTRL) .......................... 79
5.8.15 Flash CRC check result register (FLASH_CRC_CHKR).................. 79
5.8.16 Security library password setting register (SLIB_SET_PWD).......... 79
5.8.17 Security library address setting register (SLIB_SET_RANGE) ........ 79
5.8.18 Flash extension memory security library setting register (EM_SLIB_SET)
81
5.8.19 Boot memory mode setting register (BTM_MODE_SET) ................. 81
5.8.20 Security library unlock register (FLASH_UNLOCK) ........................ 81

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6General-purpose I/Os (GPIOs)....................................................... 82
6.1 Introduction .................................................................................82
6.2 Functional overview .....................................................................82
6.2.1 GPIO structure ............................................................................ 82
6.2.2 GPIO reset status........................................................................ 82
6.2.3 General-purpose input configuration............................................. 83
6.2.4 Analog input/output configuration ................................................. 83
6.2.5 General-purpose output configuration........................................... 83
6.2.6 GPIO port protection ................................................................... 83
6.2.7 IOMUX structure ......................................................................... 84
6.2.8 Multiplexed function input configuration ........................................ 84
6.2.9 IOMUX function input/output ........................................................ 85
6.2.10 Peripheral multiplexed function configuration ................................ 87
6.2.11 IOMUX map priority ..................................................................... 87
6.2.12 External interrupt/wake-up lines ................................................... 87
6.3 GPIO registers.............................................................................87
6.3.1 GPIO configuration register (GPIOx_CFGR) (x=A…H) ................... 88
6.3.2 GPIO input mode register (GPIOx_OMODE) (x=A…H) ................... 88
6.3.3 GPIO drive capability register (GPIOx_ODRVR) (x=A..H)............... 88
6.3.4 GPIO pull-up/pull-down register (GPIOx_PULL) (x=A..H) ............... 88
6.3.5 GPIO input data register (GPIOx_IDT) (x=A…H) ........................... 89
6.3.6 GPIO output data register (GPIOx_ODT) (x= A…H) ....................... 89
6.3.7 GPIO set/clear register (GPIOx_SCR) (x=A…H) ............................ 89
6.3.8 GPIO write protection register (GPIOx_WPR) (x=A…H) ................. 89
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL) (x=A..H) .... 90
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH) (x=A..H) .. 90
6.3.11 GPIO bit clear register (GPIOx_CLR) (x=A…H) ............................. 90
6.3.12 GPIO huge current control register (GPIOx_HDRV) (x=A..H).......... 90
7System configuration controller (SCFG) ....................................... 91
7.1 Introduction .................................................................................91
7.2 SCFG registers............................................................................91
7.2.1 SCFG configuration register1 (SCFG_CFG1) ................................ 91
7.2.2 SCFG external interrupt configuration register1 (SCFG_ EXINTC1) 92
7.2.3 SCFG external interrupt configuration register2 (SCFG_ EXINTC2) 93

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7.2.4 SCFG external interrupt configuration register3 (SCFG_ EXINTC3) 93
7.2.5 SCFG external interrupt configuration register4 (SCFG_ EXINTC4) 94
8External interrupt/Event controller (EXINT) .................................. 95
8.1 EXINT introduction.......................................................................95
8.2 Function overview and configuration procedure ..............................95
8.3 EXINT registers ...........................................................................96
8.3.1 Interrupt enable register (EXINT_INTEN) ...................................... 96
8.3.2 Event enable register (EXINT_EVTEN) ......................................... 96
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1)...................... 96
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2)...................... 97
8.3.5 Software trigger register (EXINT_ SWTRG)................................... 97
8.3.6 Interrupt status register (EXINT_ INTSTS) .................................... 97
9DMA controller (DMA) ................................................................... 98
9.1 Introduction .................................................................................98
9.2 Main features ..............................................................................98
9.3 Functional overview .....................................................................98
9.3.1 DMA configuration....................................................................... 98
9.3.2 Handshake mechanism ................................................................ 99
9.3.3 Arbiter ........................................................................................ 99
9.3.4 Programmable data transfer width ...............................................100
9.3.5 Errors ........................................................................................101
9.3.6 Interrupts...................................................................................101
9.3.7 Fixed DMA request mapping .......................................................101
9.4 DMA registers............................................................................ 102
9.4.1 DMA interrupt status register (DMA_STS)....................................103
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................104
9.4.3 DMA channel-x configuration register (DMA_CxCTRL) (x = 1…5)105
9.4.4 DMA channel-x number of data register (DMA_CxDTCNT) (x = 1…5)106
9.4.5 DMA channel-x peripheral address register (DMA_CxPADDR) (x = 1…5)
106
9.4.6 DMA channel-x memory address register (DMA_CxMADDR) (x = 1…5)106
10 CRC calculation unit (CRC)......................................................... 107

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10.1 CRC introduction ....................................................................... 107
10.2 CRC registers............................................................................ 107
10.2.1 Data register (CRC_DT)..............................................................107
10.2.2 Common data register (CRC_CDT)..............................................107
10.2.3 Control register (CRC_CTRL)......................................................108
10.2.4 Initialization register (CRC_IDT) .................................................108
11 I2C interface ................................................................................ 109
11.1 I2C introduction.......................................................................... 109
11.2 I2C main features....................................................................... 109
11.3 I2C functional overview............................................................... 109
11.4 I2C interface .............................................................................. 110
11.4.1 I2C slave communication flow......................................................111
11.4.2 I2C master communication flow ...................................................114
11.4.3 Data transfer using DMA.............................................................120
11.4.4 SMBus.......................................................................................121
11.4.5 I2C interrupt requests .................................................................122
11.4.6 I2C debug mode .........................................................................123
11.5 I2C registers .............................................................................. 123
11.5.1 Control register1 (I2C_CTRL1)....................................................123
11.5.2 Control register2 (I2C_CTRL2)....................................................124
11.5.3 Own address register1 (I2C_OADDR1) ........................................125
11.5.4 Own address register2 (I2C_OADDR2) ........................................125
11.5.5 Data register (I2C_DT) ...............................................................126
11.5.6 Status register1 (I2C_STS1) .......................................................126
11.5.7 Status register2 (I2C_STS2) .......................................................128
11.5.8 Clock control register (I2C_ CLKCTRL) .......................................129
11.5.9 Clock rise time register (I2C_TMRISE) ........................................129
12 Universal synchronous/asynchronous receiver/transmitter (USART)130
12.1 USART introduction ................................................................... 130
12.2 Full-duplex/half-duplex selector .................................................. 132
12.3 Mode selector............................................................................ 132
12.3.1Introduction................................................................................132
12.3.2 Configuration procedure .............................................................132

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12.4 USART frame format and configuration........................................ 136
12.5 DMA transfer introduction ........................................................... 137
12.5.1 Transmission using DMA ............................................................137
12.5.2 Reception using DMA .................................................................137
12.6 Baud rate generation.................................................................. 138
12.6.1 Introduction................................................................................138
12.6.2 Configuration .............................................................................138
12.7 Transmitter................................................................................ 139
12.7.1 Transmitter introduction..............................................................139
12.7.2 Transmitter configuration ............................................................139
12.8 Receiver ................................................................................... 140
12.8.1 Receiver introduction..................................................................140
12.8.2 Receiver configuration................................................................140
12.8.3 Start bit and noise detection .......................................................141
12.9 Tx/Rx swap ............................................................................... 142
12.10Interrupt requests ...................................................................... 142
12.11I/O pin control............................................................................ 143
12.12USART registers........................................................................ 143
12.12.1 Status register (USART_STS) ..................................................144
12.12.2 Data register (USART_DT).......................................................145
12.12.3 Baud rate register (USART_BAUDR) ........................................145
12.12.4 Control register1 (USART_CTRL1) ...........................................145
12.12.5 Control register2 (USART_CTRL2) ...........................................146
12.12.6 Control register3 (USART_CTRL3) ...........................................147
12.12.7 Guard time and divider register (USART_GDIV) ........................148
13 Serial peripheral interface (SPI).................................................. 149
13.1 SPI introduction......................................................................... 149
13.2 Functional overview ................................................................... 149
13.2.1 SPI description...........................................................................149
13.2.2 Full-duplex/half-duplex selector ..................................................150
13.2.3 Chip select controller..................................................................152
13.2.4 SPI_SCK controller ....................................................................152
13.2.5 CRC ..........................................................................................152

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13.2.6 DMA transfer..............................................................................153
13.2.7 Transmitter ................................................................................154
13.2.8 Receiver ....................................................................................154
13.2.9 Motorola mode ...........................................................................155
13.2.10 Interrupts ................................................................................157
13.2.11 IO pin control ..........................................................................158
13.2.12 Precautions.............................................................................158
13.3 I2S functional description ........................................................... 158
13.3.1 I2S introduction ..........................................................................158
13.3.2 Operation mode selector.............................................................159
13.3.3 Audio protocol selector ...............................................................160
13.3.4 I2S_CLK controller .....................................................................161
13.3.5 DMA transfer..............................................................................163
13.3.6 Transmitter/Receiver ..................................................................164
13.3.7 I2S communication timings .........................................................165
13.3.8 Interrupts...................................................................................165
13.3.9 IO pin control .............................................................................165
13.4 SPI registers ............................................................................. 166
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........166
13.4.2 SPI control register2 (SPI_CTRL2) ..............................................167
13.4.3 SPI status register (SPI_STS) .....................................................168
13.4.4 SPI data register (SPI_DT) .........................................................168
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................168
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ..............169
13.4.7 SPITxCRC register (SPI_TCRC)..................................................169
13.4.8 SPI_I2S configuration register (SPI_I2SCTRL).............................169
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................170
14 Timer .......................................................................................... 171
14.1 General-purpose timer (TMR6).................................................... 172
14.1.1 TMR6 introduction ......................................................................172
14.1.2 TMR6 main features ...................................................................172
14.1.3 TMR6 functional overview...........................................................172
14.1.3.1 Count clock .......................................................................... 172
14.1.3.2 Counting mode ..................................................................... 172

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14.1.3.3 Debug mode ......................................................................... 173
14.1.4 TMR6 registers ..........................................................................174
14.1.4.1 TMR6 control register1 (TMRx_CTRL1) .................................. 175
14.1.4.2 TMR6 control register2 (TMRx_CTRL2) .................................. 175
14.1.4.3 TMR6 DMA/interrupt enable register (TMRx_IDEN) .................. 175
14.1.4.4 TMR6 interrupt status register (TMRx_ISTS) ........................... 176
14.1.4.5 TMR6 software event register (TMRx_SWEVT)........................ 176
14.1.4.6 TMR6 counter value (TMRx_CVAL) ........................................ 176
14.1.4.7 TMR6 division (TMRx_DIV).................................................... 176
14.1.4.8 TMR6 period register (TMRx_PR)........................................... 176
14.2 General-purpose timer (TMR3).................................................... 177
14.2.1 TMR3 introduction ......................................................................177
14.2.2 TMR3 main features ...................................................................177
14.2.3 TMR3 functional overview ...........................................................177
14.2.3.1 Count clock .......................................................................... 177
14.2.3.2 Counting mode ..................................................................... 181
14.2.3.3 TMR input function................................................................ 184
14.2.3.4 TMR output function.............................................................. 186
14.2.3.5 TMR synchronization............................................................. 190
14.2.3.6 Debug mode ......................................................................... 192
14.2.4 TMR3 registers ..........................................................................192
14.2.4.1 Control register1 (TMR3_CTRL1) ........................................... 193
14.2.4.2 Control register2 (TMR3_CTRL2) ........................................... 194
14.2.4.3 Slave timer control register (TMR3_STCTRL) .......................... 194
14.2.4.4 DMA/interrupt enable register (TMR3_IDEN) ........................... 195
14.2.4.5 Interrupt status register (TMR3_ISTS) .................................... 196
14.2.4.6 Software event register (TMR3_SWEVT)................................. 197
14.2.4.7 Channel mode register1 (TMRx_CM1) .................................... 197
14.2.4.8 Channel mode register2 (TMR3_CM2) .................................... 199
14.2.4.9 Channel control register (TMR3_CCTRL) ................................ 200
14.2.4.10 Counter value (TMR3_CVAL) ............................................. 200
14.2.4.11 Division value (TMR3_DIV) ................................................ 201
14.2.4.12 Period register (TMR3_PR) ................................................ 201
14.2.4.13 Channel 1 data register (TMR3_C1DT) ............................... 201
14.2.4.14 Channel 2 data register (TMR3_C2DT) ............................... 201
14.2.4.15 Channel 3 data register (TMR3_C3DT) ............................... 201
14.2.4.16 Channel 4 data register (TMR3_C4DT) ............................... 202
14.2.4.17 DMA control register (TMR3_DMACTRL)............................. 202

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14.2.4.18 DMA data register (TMR3_DMADT) .................................... 202
14.3 General-purpose timer (TMR14).................................................. 203
14.3.1 TMR14 introduction ....................................................................203
14.3.2 TMR14 main features .................................................................203
14.3.3 TMR14 functional overview .........................................................203
14.3.3.1 Count clock .......................................................................... 203
14.3.3.2 Counting mode ..................................................................... 204
14.3.3.3 TMR input function................................................................ 205
14.3.3.4 TMR output function.............................................................. 206
14.3.3.5 Debug mode ......................................................................... 207
14.3.4 TMR14 registers.........................................................................207
14.3.4.1 Control register1 (TMR14_CTRL1) ......................................... 208
14.3.4.2 Interrupt enable register (TMR14_IDEN) ................................. 208
14.3.4.3 Interrupt status register (TMR14_ISTS) .................................. 208
14.3.4.4 Software event register (TMR14_SWEVT) ............................... 209
14.3.4.5 Channel mode register1 (TMR14_CM1) .................................. 209
14.3.4.6 Channel control register (TMR14_CCTRL) .............................. 212
14.3.4.7 Counter value (TMR14_CVAL) ............................................... 212
14.3.4.8 Division value (TMR14_DIV) .................................................. 212
14.3.4.9 Period register (TMR14_PR) .................................................. 212
14.3.4.10 Channel 1 data register (TMR14_C1DT) ............................. 212
14.3.4.11 Channel input remap register (TMR14_RMP)....................... 213
14.4 General-purpose timer (TMR15).................................................. 214
14.4.1 TMR15 introduction ....................................................................214
14.4.2 TMR15 main features .................................................................214
14.4.3 TMR15 functional overview .........................................................214
14.4.3.1 Count clock .......................................................................... 214
14.4.3.2 Counting mode ..................................................................... 216
14.4.3.3 TMR input function................................................................ 218
14.4.3.4 TMR output function.............................................................. 220
14.4.3.5 TMR brake function............................................................... 224
14.4.3.6 TMR synchronization............................................................. 225
14.4.3.7 Debug mode ......................................................................... 226
14.4.4 TMR15 registers.........................................................................227
14.4.4.1 Control register1 (TMR15_CTRL1) ......................................... 227
14.4.4.2 Control register2 (TMR15_CTRL2) ......................................... 228
14.4.4.3 TMR15 slave timer control register (TMR15_STCTRL) ............. 228

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14.4.4.4 TMR15 DMA/interrupt enable register (TMR15_IDEN) .............. 229
14.4.4.5 TMR15 interrupt status register (TMR15_ISTS) ....................... 230
14.4.4.6 TMR15 software event register (TMR15_SWEVT) .................... 231
14.4.4.7 TMR15 channel mode register1 (TMR15_CM1) ........................ 231
14.4.4.8 TMR15 channel control register (TMR15_CCTRL).................... 234
14.4.4.9 TMR15 Counter value (TMR15_CVAL) .................................... 236
14.4.4.10 TMR15 Division value (TMR15_DIV) ................................... 236
14.4.4.11 TMR15 period register (TMR15_PR) ................................... 236
14.4.4.12 TMR15 repetition period register (TMR15_RPR) .................. 236
14.4.4.13 TMR15 channel 1 data register (TMR15_C1DT) ................... 236
14.4.4.14 TMR15 channel 2 data register (TMR15_C2DT) ................... 236
14.4.4.15 TMR15 brake register (TMR15_BRK) .................................. 237
14.4.4.16 TMR15 DMA control register (TMR15_DMACTRL)................ 238
14.4.4.17 TMR15 DMA data register (TMR15_DMADT) ....................... 238
14.5 General-purpose timer (TMR16 and TMR17) ................................ 239
14.5.1 TMR16 and TMR17 introduction ..................................................239
14.5.2 TMR16 and TMR17 main features ...............................................239
14.5.3 TMR16 and TMR17 functional overview .......................................239
14.5.3.1 Count clock .......................................................................... 239
14.5.3.2 Counting mode ..................................................................... 240
14.5.3.3 TMR input function................................................................ 241
14.5.3.4 TMR output function.............................................................. 242
14.5.3.5 TMR brake function............................................................... 245
14.5.3.6 Debug mode ......................................................................... 246
14.5.4 TMR16 and TMR17 registers.......................................................246
14.5.4.1 TMR16 and TMR17 control register1 (TMRx_CTRL1)............... 247
14.5.4.2 TMR16 and TMR17 control register2 (TMRx_CTRL2) ............... 247
14.5.4.3 TMR16 and TMR17 DMA/interrupt enable register (TMRx_IDEN)248
14.5.4.4 TMR16 and TMR17 interrupt status register (TMRx_ISTS)........ 248
14.5.4.5 TMR16 and TMR17 software event register (TMRx_SWEVT) .... 249
14.5.4.6 TMR16 and TMR17 channel mode register1 (TMRx_CM1) ........ 249
14.5.4.7 TMR16 and TMR17 channel control register (TMRx_CCTRL) .... 252
14.5.4.8 TMR16 and TMR17 counter value (TMRx_CVAL) ..................... 253
14.5.4.9 TMR16 and TMR17 division value (TMRx_DIV)........................ 253
14.5.4.10 TMR16 and TMR17 period register (TMRx_PR) ................... 253
14.5.4.11 TMR16 and TMR17 repetition period register (TMRx_RPR) .. 253
14.5.4.12 TMR16 and TMR17 channel 1 data register (TMRx_C1DT) ... 253
14.5.4.13 TMR16 and TMR17 brake register (TMRx_BRK) .................. 254

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14.5.4.14 TMR16 and TMR17 DMA control register (TMRx_DMACTRL) 255
14.5.4.15 TMR16 and TMR17 DMA data register (TMRx_DMADT) ....... 255
14.6 Advanced-control timers (TMR1) ................................................. 256
14.6.1 TMR1 introduction ......................................................................256
14.6.2 TMR1 main features ...................................................................256
14.6.3 TMR1 functional overview ...........................................................256
14.6.3.1 Count clock .......................................................................... 256
14.6.3.2 Counting mode ..................................................................... 260
14.6.3.3 TMR input function................................................................ 264
14.6.3.4 TMR output function.............................................................. 266
14.6.3.5 TMR brake function............................................................... 270
14.6.3.6 TMR synchronization............................................................. 271
14.6.3.7 Debug mode ......................................................................... 272
14.6.4 TMR1 registers ..........................................................................273
14.6.4.1 TMR1 control register1 (TMR1_CTRL1) .................................. 273
14.6.4.2 TMR1 control register2 (TMR1_CTRL2) .................................. 275
14.6.4.3 TMR1 slave timer control register (TMR1_STCTRL) ................. 275
14.6.4.4 TMR1 DMA/interrupt enable register (TMR1_IDEN).................. 276
14.6.4.5 TMR1 interrupt status register (TMR1_ISTS) ........................... 278
14.6.4.6 TMR1 software event register (TMR1_SWEVT)........................ 279
14.6.4.7 TMR1 channel mode register1 (TMR1_CM1) ........................... 279
14.6.4.8 TMR1 channel mode register2 (TMR1_CM2) ........................... 281
14.6.4.9 TMR1 Channel control register (TMR1_CCTRL)....................... 282
14.6.4.10 TMR1 counter value (TMR1_CVAL) .................................... 284
14.6.4.11 TMR1 division value (TMR1_DIV) ....................................... 284
14.6.4.12 TMR1 period register (TMR1_PR)....................................... 284
14.6.4.13 TMR1 repetition period register (TMR1_RPR)...................... 284
14.6.4.14 TMR1 channel 1 data register (TMR1_C1DT) ...................... 284
14.6.4.15 TMR1 channel 2 data register (TMR1_C2DT) ...................... 284
14.6.4.16 TMR1 channel 3 data register (TMR1_C3DT) ...................... 285
14.6.4.17 TMR1 channel 4 data register (TMR1_C4DT) ...................... 285
14.6.4.18 TMR1 brake register (TMR1_BRK)...................................... 285
14.6.4.19 TMR1 DMA control register (TMR1_DMACTRL) ................... 286
14.6.4.20 TMR1 DMA data register (TMR1_DMADT)........................... 286
15 Window watchdog timer (WWDT) ................................................ 287
15.1 WWDT introduction .................................................................... 287
15.2 WWDT main features ................................................................. 287

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15.3 WWDT functional overview ......................................................... 287
15.4 Debug mode.............................................................................. 288
15.5 WWDT registers ........................................................................ 288
15.5.1 Control register (WWDT_CTRL) ..................................................288
15.5.2 Configuration register (WWDT_CFG)...........................................289
15.5.3 Status register (WWDT_STS)......................................................289
16 Watchdog timer (WDT)................................................................ 290
16.1 WDT introduction ....................................................................... 290
16.2 WDT main features .................................................................... 290
16.3 WDT functional overview ............................................................ 290
16.4 Debug mode.............................................................................. 291
16.5 WDT registers ........................................................................... 291
16.5.1 Command register (WDT_CMD) ..................................................291
16.5.2 Divider register (WDT_DIV).........................................................291
16.5.3 Reload register (WDT_RLD)........................................................292
16.5.4 Status register (WDT_STS).........................................................292
17 Enhanced real-time clock (ERTC) ............................................... 293
17.1 ERTC introduction...................................................................... 293
17.2 ERTC main features................................................................... 293
17.3 ERTC functional overview........................................................... 293
17.3.1 ERTC clock................................................................................293
17.3.2 ERTC initialization......................................................................294
17.3.3 ERTC calibration ........................................................................296
17.3.4 Time stamp ................................................................................296
17.3.5 Tamper detection .......................................................................297
17.3.6 Multiplexed function output .........................................................297
17.3.7 ERTC wakeup ............................................................................297
17.4 ERTC registers.......................................................................... 298
17.4.1 ERTC time register (ERTC_TIME) ...............................................298
17.4.2 ERTC date register (ERTC_DATE) ..............................................299
17.4.3 ERTC control register (ERTC_CTRL)...........................................299
17.4.4 ERTC initialization and status register (ERTC_STS).....................300
17.4.5 ERTC divider register (ERTC_DIV)..............................................301

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17.4.6 ERTC alarm clock A register (ERTC_ALA) ...................................301
17.4.7 ERTC write protection register (ERTC_WP) .................................302
17.4.8 ERTC subsecond register (ERTC_SBS) .......................................302
17.4.9 ERTC time adjustment register (ERTC_TADJ)..............................302
17.4.10 ERTC time stamp time register (ERTC_TSTM) ..........................302
17.4.11 ERTC time stamp date register (ERTC_TSDT) ..........................303
17.4.12 ERTC time stamp subsecond register (ERTC_TSSBS) ...............303
17.4.13 ERTC smooth calibration register (ERTC_SCAL) .......................303
17.4.14 ERTC tamper configuration register (ERTC_TAMP) ...................303
17.4.15 ERTC alarm clock A subsecond register (ERTC_ALASBS) .........305
17.4.16 ERTC battery powered domain data register (ERTC_BPRx) .......305
18 Analog-to-digital converter (ADC)............................................... 306
18.1 ADC introduction ....................................................................... 306
18.2 ADC main features..................................................................... 306
18.3 ADC structure............................................................................ 306
18.4 ADC functional overview............................................................. 307
18.4.1 Channel management.................................................................307
18.4.1.1 Internal temperature sensor ................................................... 308
18.4.1.2 Internal reference voltage...................................................... 308
18.4.2 ADC operation process...............................................................308
18.4.2.1 Power-on and calibration ....................................................... 308
18.4.2.2 Trigger................................................................................. 309
18.4.2.3 Sampling and conversion sequence........................................ 310
18.4.3 Conversion sequence management .............................................310
18.4.3.1 Sequence mode .................................................................... 310
18.4.3.2 Automatic preempted group conversion mode ......................... 310
18.4.3.3 Repetition mode.................................................................... 311
18.4.3.4 Partition mode ...................................................................... 311
18.4.4 Data management ......................................................................312
18.4.4.1 Data alignment ..................................................................... 312
18.4.4.2 Data read ............................................................................. 312
18.4.5 Voltage monitoring .....................................................................313
18.4.6 Status flag and interrupts............................................................313
18.5 ADC registers............................................................................ 313
18.5.1 ADC status register (ADC_STS) ..................................................314

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18.5.2 ADC control register1 (ADC_CTRL1) ...........................................314
18.5.3 ADC control register2 (ADC_CTRL2) ...........................................315
18.5.4 ADC sampling time register 1 (ADC_SPT1)..................................317
18.5.5 ADC sampling time register 2 (ADC_SPT2)..................................318
18.5.6 ADC preempted channel data offset register x (ADC_ PCDTOx) (x=1..4)
320
18.5.7 ADC voltage monitor high threshold register (ADC_VWHB)...........320
18.5.8 ADC voltage monitor low threshold register (ADC_ VWLB)............320
18.5.9 ADC ordinary sequence register 1 (ADC_ OSQ1) .........................321
18.5.10 ADC ordinary sequence register 2 (ADC_OSQ2) .......................321
18.5.11 ADC ordinary sequence register 3 (ADC_OSQ3) .......................321
18.5.12 ADC preempted sequence register (ADC_ PSQ)........................322
18.5.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............322
18.5.14 ADC ordinary data register (ADC_ ODT) ...................................322
19 Comparator (COMP) .................................................................... 323
19.1 COMP introduction..................................................................... 323
19.2 Main features ............................................................................ 323
19.3 Interrupt management ................................................................ 323
19.4 Design tips ................................................................................ 324
19.5 Functional overview ................................................................... 324
19.5.1 Analog comparator .....................................................................324
19.5.2 Glitch filter.................................................................................325
19.6 CMP registers............................................................................ 325
19.6.1 Comparator control and status register 1 (COMP_CTRLSTS) ........326
19.6.2 Glitch filter enable register (G_FILTER_EN) ................................327
19.6.3 Glitch filter high pulse count (HIGH-PULSE) ................................327
19.6.4 Glitch filter low pulse count (LOW-PULSE) ..................................328
20 Operational amplifer (OPA) ......................................................... 329
20.1 Introduction ............................................................................... 329
20.2 Main features ............................................................................ 329
20.3 Functional description ................................................................ 329
21 Infrared timer (IRTMR) ................................................................ 331

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22 Debug (DEBUG) .......................................................................... 332
22.1 Debug introduction..................................................................... 332
22.2 Debug and trace ........................................................................ 332
22.3 I/O pin control............................................................................ 332
22.4 DEBUG registers ....................................................................... 332
22.4.1 DEBUG device ID (DEBUG_IDCODE)..........................................333
22.4.2 DEBUG control register (DEBUG_CTRL) .....................................334
23 Revision history.......................................................................... 336

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List of figures
Figure 1-1 AT32F421 Series microcontrollers system architecture................................................................. 26
Figure 1-2 Internal block diagram of Cortex®-M4........................................................................................ 27
Figure 1-3 Comparison between bit-band region and its alias region: image A ......................................... 27
Figure 1-4 Comparison between bit-band region and its alias region: image B ......................................... 28
Figure 1-5 Reset process ............................................................................................................................ 31
Figure 1-6 Example of MSP and PC initialization........................................................................................ 32
Figure 2-1AT32F421 address mapping....................................................................................................... 34
Figure 3-1 Block diagram of each power supply ......................................................................................... 39
Figure 3-2 Power-on reset/Low voltage reset waveform............................................................................. 40
Figure 3-3 PVM threshold and output ......................................................................................................... 41
Figure 4-1 AT32F421 clock tree .................................................................................................................. 45
Figure 4-2 System reset circuit.................................................................................................................... 48
Figure 5-1 Flash memory sector erase process.......................................................................................... 63
Figure 5-2 Flash memory mass erase process........................................................................................... 64
Figure 5-3 Flash memory programming process ........................................................................................ 65
Figure 5-4 System data area erase process ............................................................................................... 67
Figure 5-5 System data area programming process................................................................................... 68
Figure 6-1 GPIO basic structure.................................................................................................................. 82
Figure 6-2 IOMUX structure ........................................................................................................................ 84
Figure 8-1 External interrupt/Event controller block diagram...................................................................... 95
Figure 9-1 DMA block diagram .................................................................................................................... 98
Figure 9-2 Re-arbitrate after request/acknowledge..................................................................................... 99
Figure 9-3 PWIDTH: byte, MWIDTH: half-word ........................................................................................ 100
Figure 9-4 PWIDTH: half-word, MWIDTH: word ....................................................................................... 100
Figure 9-5 PWIDTH: word, MWIDTH: byte ............................................................................................... 100
Figure 11-1 I2C bus protocol...................................................................................................................... 109
Figure 11-2 I2C function block diagram ......................................................................................................110
Figure 11-3 Transfer sequence of slave transmitter...................................................................................112
Figure 11-4 Transfer sequence of slave receiver .......................................................................................113
Figure 11-5 Transfer sequence of master transmitter ................................................................................114
Figure 11-6 Transfer sequence of master receiver.....................................................................................116
Figure 11-7 Transfer sequence of master receiver when N>2...................................................................117
Figure 11-8 Transfer sequence of master receiver when N=2...................................................................118
Figure 11-9 Transfer sequence of master receiver when N=1...................................................................119
Figure 12-1 USART block diagram............................................................................................................ 130
Figure 12-2 BFF and FERR detection in LIN mode .................................................................................. 133
Figure 12-3 Smartcard frame format ......................................................................................................... 133
Figure 12-4 IrDA DATA(3/16) – normal mode ........................................................................................... 134
Figure 12-5 Hardware flow control ............................................................................................................ 134
Figure 12-6 Mute mode using Idle line or Address mark detection........................................................... 135
Figure 12-7 8-bit format USART synchronous mode................................................................................ 135
Figure 12-8 Word length............................................................................................................................ 136
Figure 12-9 Stop bit configuration ............................................................................................................. 137

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Figure 12-10 TDC/TDBE behavior when transmitting............................................................................... 139
Figure 12-11 Data sampling for noise detection........................................................................................ 142
Figure 12-12 Tx/Rx swap........................................................................................................................... 142
Figure 12-13 USART interrupt map diagram............................................................................................. 143
Figure 13-1 SPI block diagram.................................................................................................................. 149
Figure 13-2 SPI two-wire unidirectional full-duplex connection ................................................................ 150
Figure 13-3 Single-wire unidirectional receive only in SPI master mode.................................................. 150
Figure 13-4 Single-wire unidirectional receive only in SPI slave mode .................................................... 151
Figure 13-5 Single-wire bidirectional half-duplex mode ............................................................................ 151
Figure 13-6 Master full-duplex communications ....................................................................................... 155
Figure 13-7 Slave full-duplex communications.......................................................................................... 156
Figure 13-8 Slave full-duplex communications.......................................................................................... 156
Figure 13-9 Slave half-duplex receive....................................................................................................... 156
Figure 13-10 Slave half-duplex transmit.................................................................................................... 157
Figure 13-11 Master half-duplex receive ................................................................................................... 157
Figure 13-12 SPI interrupts ....................................................................................................................... 157
Figure 13-13 I2S block diagram ................................................................................................................. 158
Figure 13-14 I2S slave device transmission .............................................................................................. 159
Figure 13-15 I2S slave device reception.................................................................................................... 159
Figure 13-16 I2S master device transmission............................................................................................ 160
Figure 13-17 I2S master device reception................................................................................................. 160
Figure 13-18 CK & MCK source in master mode...................................................................................... 162
Figure 13-19 Audio standard timings......................................................................................................... 165
Figure 13-20 I2S interrupts......................................................................................................................... 165
Figure 14-1 Basic timer block diagram...................................................................................................... 172
Figure 14-2 Counter timing diagram, CK_INT divided by 1 ...................................................................... 172
Figure 14-3 Counter structure ................................................................................................................... 173
Figure 14-4 Overflow event when PRBEN=0............................................................................................ 173
Figure 14-5 Overflow event when PRBEN=1............................................................................................ 173
Figure 14-6 Counter timing diagram, internal clock divided by 4.............................................................. 173
Figure 14-7 Block diagram of general-purpose timer................................................................................ 177
Figure 14-8 Count clock block diagram..................................................................................................... 178
Figure 14-9 Use CK_INT to drive counter, with TMRx_DIV=0x0 and TMRx_PR=0x16 ........................... 178
Figure 14-10 Block diagram of external clock mode A.............................................................................. 179
Figure 14-11 Counting in external clock mode A, with PR=0x32 and DIV=0x0........................................ 179
Figure 14-12 Block diagram in external clock mode B.............................................................................. 179
Figure 14-13 Counting in external clock mode B, with PR=0x32 and DIV=0x0 ....................................... 180
Figure 14-14 Counter timing with prescaler value changing from 1 to 4 .................................................. 180
Figure 14-15 Counter structure ................................................................................................................. 181
Figure 14-16 Overflow event when PRBEN=0.......................................................................................... 181
Figure 14-17 Overflow event when PRBEN=1.......................................................................................... 182
Figure 14-18 Counter timing diagram, internal clock divided by 4............................................................ 182
Figure 14-19 Counter timing diagram, internal clock divided by 1, TMRx_PR=0x32 ............................... 183
Figure 14-20 Encoder mode structure....................................................................................................... 183
Figure 14-21 Example of counter behavior in encoder interface mode (encoder mode C)...................... 184

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Figure 14-22 Input/output channel 1 main circuit...................................................................................... 185
Figure 14-23 Channel 1 input stage.......................................................................................................... 185
Figure 14-24 PWM input mode configuration............................................................................................ 186
Figure 14-25 PWM input mode.................................................................................................................. 186
Figure 14-26 Capture/compare channel output stage (channel 1 to 4) .................................................... 187
Figure 14-27 C1ORAW toggles when counter value matches the C1DT value ....................................... 188
Figure 14-28 Upcounting mode and PWM mode A................................................................................... 188
Figure 14-29 Up/down counting mode and PWM mode A........................................................................ 188
Figure 14-30 One-pulse mode................................................................................................................... 189
Figure 14-31 Clearing CxORAW(PWM mode A) by EXT input................................................................. 189
Figure 14-32 Example of reset mode........................................................................................................ 190
Figure 14-33 Example of suspend mode .................................................................................................. 190
Figure 14-34 Example of trigger mode...................................................................................................... 190
Figure 14-35 Master/slave timer connection ............................................................................................. 191
Figure 14-36 Using master timer to start slave timer ................................................................................ 191
Figure 14-37 Starting master and slave timers synchronously by an external trigger.............................. 192
Figure 14-38 Block diagram of general-purpose TMR14.......................................................................... 203
Figure 14-39 Count clock........................................................................................................................... 203
Figure 14-40 Use CK_INT to drive counter, with TMRx_DIV=0x0 and TMRx_PR=0x16 ......................... 203
Figure 14-41 Counter timing with prescaler value changing from 1 to 4 .................................................. 204
Figure 14-42 Counter structure ................................................................................................................. 204
Figure 14-43 Overflow event when PRBEN=0.......................................................................................... 205
Figure 14-44 Overflow event when PRBEN=1.......................................................................................... 205
Figure 14-45 Input/output channel 1 main circuit...................................................................................... 205
Figure 14-46 Channel 1 input stage.......................................................................................................... 206
Figure 14-47 Capture/compare channel output stage (channel 1) ........................................................... 206
Figure 14-48 C1ORAW toggles when counter value matches the C1DT value ....................................... 207
Figure 14-49 Upcounting mode and PWM mode A................................................................................... 207
Figure 14-50 Block diagram of general-purpose TMR15.......................................................................... 214
Figure 14-51 Count clock........................................................................................................................... 214
Figure 14-52 Use CK_INT to drive counter, with TMRx_DIV=0x0 and TMRx_PR=0x16......................... 215
Figure 14-53 Block diagram of external clock mode A.............................................................................. 215
Figure 14-54 Counting in external clock mode A, with PR=0x32 and DIV=0x0........................................ 216
Figure 14-55 Counter timing with prescaler value changing from 1 to 4 .................................................. 216
Figure 14-56 Counter structure ................................................................................................................. 217
Figure 14-57 Overflow event when PRBEN=0.......................................................................................... 217
Figure 14-58 Overflow event when PRBEN=1.......................................................................................... 217
Figure 14-59 OVFIF when RPR=2 ............................................................................................................ 218
Figure 14-60 Input/output channel 1 main circuit...................................................................................... 218
Figure 14-61 Channel 1 input stage .......................................................................................................... 219
Figure 14-62 PWM input mode configuration............................................................................................ 220
Figure 14-63 PWM input mode.................................................................................................................. 220
Figure 14-64 Channel 1 output stage........................................................................................................ 220
Figure 14-65 Channel 2 output stage........................................................................................................ 221
Figure 14-66 C1ORAW toggles when counter value matches the C1DT value ....................................... 222