ASIX AX99100 User manual

ASIX ELECTRONICS CORPORATION Release Date: 06/06/2016
4F, NO.8, Hsin Ann Rd., HsinChu Science Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: [phone]
FAX: [phone]
http://www.asix.com.tw
AX99100
PCIe to Multi I/O Controller
Features
PCI Express
Single-lane (X1) PCI Express End-point
Controller with PHY integrated
Compliant with PCI Express 2.0 Gen 1
Compliant with PCI Express card specifications
Compliant with PCI Power Management 1.2
Supports four PCI Express functions
Supports both legacy and MSI Interrupts
Supports ASPM Power Management
Serial Port Interface
Dual or Quad UARTs
Supports RS-232/RS-422/RS-485
multiprotocol
Bi-directional speeds up to 25 Mbps per port
Full Serial Modem Control
Supports Hardware, Software Flow Control
Supports 5, 6, 7, 8 and 9-bit Serial format
Supports Even, Odd, None, Space and Mark
parity
Supports Custom baud rate by internal PLL or
external clock
Supports On Chip 256 Byte depth FIFOs in
Transmit, Receive path of each Serial Port
Supports remote wakeup and power
management features
Serial Port transceiver shutdown support
Supports Slow IrDA mode (up to 115200bps)
on all Serial Ports
Supports multi-drop application for 9-bit mode
Supports DMA burst transfer
Parallel Port
Compatible with IEEE 1284 –SPP/Byte/ECP
Mode
SPI Master Interface
Programmable SPI clock frequency up to 42MHz
Supports Mode 0, Mode 1, Mode 2 and Mode 3
timing modes
Supports MSB/LSB first transfer fashion
Programmable peripheral chip select, selecting up
to 7 SPI devices
Supports Non-Burst-Type transfer up to 8 bytes
and/or Burst-Type transfer via DMA mode for
high performance
Supports to fragment large data block into several
smaller transfers on SPI bus to reduce software
loading
Supports programmable transfer 0 ~ 8 bytes
OP-Code field in each transfer automatically to
reduce software loading
Supports wakeup by SWAKEn pin from Slave
Local Bus Interface
Supports memory or I/O access through PCIe
BAR0/1 to local bus interface, each BAR
mapping to local bus' chip select (CS0n and
CS1n)
Supports direct access and bus master access
(auto-increment and fixed address)
Supports 8-bit or 16-bit data bus width (little
and big endian bus swap)
Supports up to 2 Kbytes address space and 2
chip select outputs when separated address/data
bus style
Supports up to 64 Kbytes address space and 2
chip select outputs when multiplexed
address/data bus style
Supports programmable local chip select region
Supports “Slave Request based DMA” access
for interfacing with external device with bus
master
Supports clock out, CLKO, up to 62.5MHz
Supports asynchronous or synchronous Local
Bus with required clock output, CLKO
Supports programmable bus access cycles,
self-terminated bus access cycles and
back-to-back turnaround cycles
Supports programmable RSTO, ALE, RDY,
DREQ0/1, DACK0/1, CLKO polarity, and
INT0/1 level/edge trigger
Supports wakeup by INT0/1 and DREQ0/1 pins
Supports I2C Master Interface
Up to 24 bi-directional GPIO lines including 8
dedicated GPIO and 16 multi-function GPIO
Integrates on-chip power-on reset circuit
On Chip 3.3 to 1.2V Regulator
68-pin QFN RoHS compliant package
Operating temperature range: 0 to 70°C or -40 to
+85°C
Document No: AX99100/V0.24/06/06/16

2
AX99100
PCIe to Multi I/O Controller
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
Product Description
The AX99100 is a single chip solution that fully integrates PCIe 2.0 Gen 1 end-point controller and SerDes with a
variety of peripherals such as four High Speed Serial Ports, one Parallel Port, I2C Master, High Speed SPI, Local
Bus (ISA-Like), and GPIOs. It consists of four main configurations such as 4S (PCIe to Quad Serial), 2S+1P (PCIe
to Dual Serial and Single Parallel), 2S+SPI (PCIe to Dual Serial and SPI), and LB (PCIe to Local Bus/ISA-Like)
for different kinds of applications.
The AX99100, in 68-pin QFN, are available with RoHS compliant package and supports commercial grade
operating temperature range from 0 to 70°C and industrial grade from -40 to 85°C.
Target Applications

3
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
Copyright © 2016ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX
may make changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “Reserved”,
“Undefined”or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them. Always contact ASIX to get the latest document
before starting a design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the
property of their respective owners.

4
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
Table of Contents
1INTRODUCTION......................................................................................................................................... 6
GENERAL DESCRIPTION ........................................................................................................................... 61.1 AX99100 BLOCK DIAGRAM .................................................................................................................... 71.2 AX99100 PINOUT DIAGRAM ................................................................................................................... 81.3 SIGNAL DESCRIPTION .............................................................................................................................. 91.4
1.4.1 GPIO and Mode Setting................................................................................................................ 11
1.4.2 Serial Interface for COM Port ...................................................................................................... 12
1.4.3 Serial Interface for Multi-Protocol Transceiver ........................................................................... 13
1.4.4 Serial Port with GPIO enabled..................................................................................................... 14
1.4.5 Serial Port with Function Disabled............................................................................................... 15
1.4.6 Parallel Port.................................................................................................................................. 16
1.4.7 SPI Interface.................................................................................................................................. 17
1.4.8 Local Bus Interface ....................................................................................................................... 18
2FUNCTION DESCRIPTION..................................................................................................................... 19
CLOCKS/RESETS AND POWER ................................................................................................................ 192.1 PCIE OPERATION................................................................................................................................... 192.2 I2CCONTROLLER................................................................................................................................... 212.3 SERIAL PORT (SP).................................................................................................................................. 212.4 PARALLEL PORT (PP)............................................................................................................................. 212.5 SPI MASTER CONTROLLER (SPI)........................................................................................................... 222.6 LOCAL BUS CONTROLLER (LB)............................................................................................................. 232.7 GPIO FUNCTION.................................................................................................................................... 242.8 POWER MANAGEMENT........................................................................................................................... 242.9
3CHIP CONFIGURATION......................................................................................................................... 25
BOOT STRAPPING PINS FOR CHIP MODE ................................................................................................ 253.1 DTR BOOT STRAPPING PINS FOR SERIAL PORT ..................................................................................... 263.2 HARDWARE CONFIGURATION EEPROM ............................................................................................... 273.3
3.3.1 Configuration EEPROM Memory Map for None Local Bus Interface ......................................... 28
3.3.2 Configuration EEPROM Memory Map for Local Bus Interface................................................... 34
3.3.3 Hardware Default Values Summary.............................................................................................. 43
3.3.4 Disable Unused PCIe Function in HWCFGEE............................................................................. 46
PCIE CONFIGURATION SPACE MAP........................................................................................................ 493.4
4ELECTRICAL SPECIFICATIONS ......................................................................................................... 51
DC CHARACTERISTICS........................................................................................................................... 514.1
4.1.1 Absolute Maximum Ratings........................................................................................................... 51
4.1.2 Recommended Operating Condition ............................................................................................. 51
4.1.3 Leakage Current and Capacitance................................................................................................ 51
4.1.4 DC Characteristics of 3.3V with 5V Tolerant I/O Pins................................................................. 52
4.1.5 DC Characteristics of Voltage Regulator ..................................................................................... 52
PCIE SPECIFICATIONS............................................................................................................................ 534.2 POWER CONSUMPTION........................................................................................................................... 544.3 POWER–UP/DOWN AND POWER MANAGEMENT SEQUENCE.................................................................... 554.4 AC TIMING CHARACTERISTICS.............................................................................................................. 564.5
4.5.1 PCIe Reference Clock Timing ....................................................................................................... 56
4.5.2 I2C Timing..................................................................................................................................... 56
4.5.3 Serial Port Timing......................................................................................................................... 57
4.5.4 SPI Timing..................................................................................................................................... 58
4.5.5 Local Bus Timing .......................................................................................................................... 59
5PACKAGE INFORMATION.................................................................................................................... 68
6ORDERING INFORMATION.................................................................................................................. 69

5
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
7REVISION HISTORY................................................................................................................................ 69
List of Figures
FIGURE 1-1: AX99100 BLOCK DIAGRAM ................................................................................................................ 7
FIGURE 1-2: AX99100 PINOUT DIAGRAM ............................................................................................................... 8
FIGURE 4-1: TXD1 AND RXD1 TIMING DIAGRAM ................................................................................................ 57
FIGURE 4-2: HIGH SPEED SPI MASTER CONTROLLER TIMING DIAGRAM AND TABLE ........................................... 58
FIGURE 4-3: NON-MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................... 59
FIGURE 4-4: ISA-LIKE BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM......................................................... 60
FIGURE 4-5: NON-MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM ............................. 61
FIGURE 4-6: MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM .................................................. 62
FIGURE 4-7: NON-MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................... 63
FIGURE 4-8: ISA-LIKE BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM......................................................... 64
FIGURE 4-9: NON-MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM ............................. 65
FIGURE 4-10: MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ................................................ 66
List of Tables
TABLE 1-1: COMMON PIN DESCRIPTION .................................................................................................................. 9
TABLE 1-2: PCIE PIN DESCRIPTION ....................................................................................................................... 10
TABLE 1-3: POWER/GROUND PIN DESCRIPTION..................................................................................................... 10
TABLE 1-4: GPIO AND MODE SETTING PIN DESCRIPTION ..................................................................................... 11
TABLE 1-5: SERIAL INTERFACE FOR COM PORT PIN DESCRIPTION ....................................................................... 12
TABLE 1-6: SERIAL INTERFACE FOR MULTI-PROTOCOL TRANSCEIVER PIN DESCRIPTION ..................................... 13
TABLE 1-7: SERIAL INTERFACE FOR GPIO ENABLED PIN DESCRIPTION ................................................................ 14
TABLE 1-8: SERIAL INTERFACE WITH PORT2AND PORT4DISABLED PIN DESCRIPTION......................................... 15
TABLE 1-9: PARALLEL PORT PIN DESCRIPTION ..................................................................................................... 16
TABLE 1-10: SPI PIN DESCRIPTION........................................................................................................................ 17
TABLE 1-11: LOCAL BUS PIN DESCRIPTION........................................................................................................... 18
TABLE 3-1: CHIP MODE SELECTION PINS .............................................................................................................. 25
TABLE 3-2: CHIP MODE SELECTION TABLE........................................................................................................... 26
TABLE 3-3: DTR MODE SELECTION PINS............................................................................................................... 26
TABLE 3-4: CONFIGURATION EEPROM MEMORY MAP FOR NONE LOCAL BUS MODE.......................................... 28
TABLE 3-5: CONFIGURATION EEPROM MEMORY MAP FOR LOCAL BUS.............................................................. 34
TABLE 3-6: HARDWARE DEFAULT VALUES IN EACH CHIP_MODE SETTING ....................................................... 43
TABLE 3-7: THE HWCHGEE CONTENT FOR 1S SETTING....................................................................................... 46
TABLE 4-1: I2CMASTER CONTROLLER TIMING TABLE.......................................................................................... 56
TABLE 4-2: LOCAL BUS TIMING TABLE................................................................................................................. 67

6
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1Introduction
General Description1.1
AX99100, PCI Express to Multi-I/O Controller, is a single chip solution for PCI express-based high performance
Serial, Parallel port, SPI and Local Bus connectivity. It provides rich features and highly configurability for variety
products.
AX99100 is a fully integrated, single-lane PCI express end-point controller and SerDes with rich high
performance peripherals such as four High Speed Serial Ports, one Parallel Port, I2C Master, one High Speed SPI
and Local Bus interface. AX99100 also provides rich GPIO ports can be controlled by software driver for some
automation control applications.
The High Speed Serial Ports with the throughput up to 25Mbps, it can works with RS-232/RS-422/RS-485
multi-protocol transceivers and allow easy reconfigured Full/Half-duplex, Loopback and Termination resistors by
software. The Parallel Port is compatible with IEEE 1284 and supports SPP, Nibble, Byte and ECP modes. An I2C
interface is provided to configure AX99100 device options through an external EEPROM after chip reset and also
supports to access other I2C device. SPI master provides a full-duplex, synchronous serial communication
interface (4 wires) to flexibly work with numerous SPI peripheral devices. Local Bus interface provides
configurable asynchronous or synchronous, 8 or 16 bits data bus width with specified endian type and address/data
multiplexed or separated bus type access mode to support variety slave interface access types. All the GPIO pins
are programmable and can be used as Input or Output. AX99100 supports 8 dedicated GPIO and every serial port
pins can be configured as GPIO by software.
Generally, the clock source of AX99100 is from PCIe slot. AX99100 don’t need any other clock source for the
main operations. But AX99100 still supports a clock input from external oscillator for those special baud rate
generated for UART, SPI and Local Bus used. AX99100 also integrates power-on reset circuit and 3.3V to 1.2V
voltage regulator on-chip to provide simplifies reset and power supply for the core power of the chip. It supports
single power operation and reduces the overall BOM cost.
AX99100 is available in 68-pin QFN RoHS compliant package and supports commercial grade operating
temperature range from 0 to 70°C and Industrial grade operating temperature range from -40 to 85°C.
AX99100 provides cost effective solution to enable simple, easy, and low cost integration capability for PCIe to
rich interface conversion applications. It could also provide highly programmable flexibility and compatibility for
many applications such as serial, parallel and Bridge for home automation and Industrial control.

7
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
AX99100 Block Diagram1.2
Figure 1-1: AX99100 Block Diagram
RXD[4:1],
TXD[4:1],
CTS[4:1],
DSR[4:1]
RI[4:1],
DCD[4:1],
RTS[4:1]
DTR[4:1]
STROBEn,
AUTOLFn
INITn,
SELECTINn,
ACKn,
BUSY,
PAPEREND,
SELECT,
PP_DIR
DATA[7:0]
PCIe PHY
&
Controller
SPI
Local Bus
LDO
Serial Port x 4
24 GPIO
POR &
Reset Gen.
I2C
CLKN, CLKP,
REXT,
DIN,DIP,
DON, DOP,
WAKEn
CLKREQn,
RSTn
SS[2:0],
SCLK,
MOSI,
MISO,
SWAKEn
VCC33A_REG,
VO12
SCL, SDA
RSTn
GPIO[23:0]
Parallel Port
PCIe
Arbiter
OSC &
Clock Gen.
EXT_CLK,
EXT_CLK_PDn
CLKO,
RSTO,
CS0n,
CS1n,
ALE,
A[9:0],
AD[15:0],
RDn,
WRn,
RDY,
INT[1:0],
DREQ[1:0],
DACK[1:0]

8
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
AX99100 Pinout Diagram1.3
AX99100 is housed in a 68-pin QFN package.
Figure 1-2: AX99100 Pinout Diagram
GPIO0 / CLKO / FAULTn TXD3 / A4 / DATA0 DTR3 / A5 / DATA1 RTS3 / A6 / DATA2 RXD3 / A7 / DATA3 RI3 / DREQ0 / DATA4 DSR3 / DACK0 / DATA5 DCD3 / DREQ1 / DATA6 CTS3 / DACK1 / DATA7 TXD4 / CS0n / STROBEn DTR4 / CS1n / AUTOLFn / SS2 RTS4 / ALE / INITn / SS1 VCCIO RXD4 / RDn / SELECTINn / SWAKEn VCCK VCC33A_REG VO12
AX99100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CTS1 / AD7
DCD1 / AD6
RI1 / AD4
DSR1 / AD5
RXD1 / AD3
VCCIO
RTS1 / AD2
DTR1 / AD1
TXD1 / AD0
VCCK
DOP
DON
VCC12A_TX
VCC12A_D
DIP
DIN
REXT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RI4 / WRn / ACKn / SS0
DSR4 / RDY / BUSY / MISO
DCD4 / INT0 / PAPEREND / MOSI
CTS4 / INT1 / SELECT / SCLK
SDA
EXT_CLK_PDn
TEST_MODE
SCL
VCCIO
EXT_CLK
RSTn
CLKREQn
VCCK
WAKEn
CLKN
CLKP
VCC12A_AUX
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GPIO1 / RSTO / PP_DIR
GPIO2 / A3
GPIO3 / A2 / CHIP_MODE[0]
VCCIO
GPIO4 / A1 / CHIP_MODE[1]
VCCK
GPIO5 / A0 / CHIP_MODE[2]
GPIO6 / A8
GPIO7 / A9
CTS2 / AD15
DCD2 / AD14
DSR2 / AD13
RI2 / AD12
RXD2 / AD11
RTS2 / AD10
DTR2 / AD9
TXD2 / AD8

9
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
Signal Description1.4
Following abbreviations are used in “Type” column of following pin description tables. Note that some I/O pins with
multiple signal definitions on the same pin may have different attribute in “Type” column for different signal
definition.
AB
Analog Bi-directional I/O
O5
Output, 3.3V with 5V tolerant
AI
Analog Input
PU
Internal Pull-Up (75K)
AO
B3
Analog Output
Bi-directional I/O, 3.3V
PD
CU
Internal Pull-Down (75K)
Controllable internal Pull-Up
B5
Bi-directional I/O, 3.3V with 5V tolerant
P
S
Power and ground pin
Schmitt Trigger
I3
Input, 3.3V
T
Tri-state
I5
Input, 3.3V with 5V tolerant
4m
4mA driving strength
O3
Output, 3.3V
8m
8mA driving strength
For example, pin 5 in AX99100 package can be RXD1 or AD3. If RXD1 is selected, its Type is I5/PU; if AD3 is
selected, its Type is B5/4m. In other words, the PU (internal pull-up) only takes effect in RXD1 signal mode while
AD3 signal mode doesn’t. User should refer to the table specific to desired function for exact pin type definition.
The multi-function pin settings are configured by pin 54, 56 and 58 to decide the chip operating mode. Please
reference to Section 3 in detailed. The following abbreviations are used in pin description tables.
HWCFGEE I2C Hardware Configuration EEPROM
CHIP_MODE Chip Operating Mode, Setting by external pull the pin 54, 56 and 68
Table 1-1: Common Pin Description
Common Pins
Pin Name
Type
Pin No
Pin Description
TEST_MODE
I5/PD
28
Test Mode enable. For normal operation, please always tie to logic low or NC.
EXT_CLK
I5
25
External Clock Input from external Oscillator.
EXT_CLK_PDn
B5
29
External Clock Power Down enable.
0: Power down external Oscillator.
1: Enable external Oscillator.
Note: When external Oscillator existed, this pin should be pull down by external
resistor for boot strapping latch. Otherwise, please pull-up by external
resistor to indicate NO external Oscillator existed.
SCL
O5/T/4
m
27
I2C Serial Clock line for I2C master controller.
SCL is a tri-stateable output, which requires an external pull-up resistor.
SDA
B5/T/4
m
30
I2C Serial Data line for I2C master controller.
SDA is a tri-stateable output, which requires an external pull-up resistor.

10
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
Table 1-2: PCIe Pin Description
PCIe interface
Pin Name
Type
Pin No
Pin Description
CLKN
AI
20
PCIe PHY differential PLL reference clock.
CLKP
AI
19
PCIe PHY differential PLL reference clock.
REXT
AO
17
Bandgap External Resistor
Connect this pin to ground through an external resistor of 20KΩ, ±1%. The total
parasitic capacitor of this pin to ground must be less than 10 pF
DIN
AI
16
PCIe PHY differential negative serial data input.
DIP
AI
15
PCIe PHY differential positive serial data input.
DOP
AO
11
PCIe PHY differential positive serial data output.
DON
AO
12
PCIe PHY differential negative serial data output.
WAKEn
O5/T/4m
21
An open-drain, active low signal that is driven low by a PCI Express function to
reactivate the PCI Express Link hierarchy’s main power rails and reference
clocks.
CLKREQn
O5/T/4m
23
Reference clock request signal
This pin is an open drain, active low signal that is driven low by the PCI Express
Mini Card function to request that the PCI Express reference clock be available
(active clock state) in order to allow the PCI Express interface to send/receive
data.
RSTn
I5/PU/S/
4m
24
Active low asynchronous reset from PCIe.
Indicates when the applied main power is within the specified tolerance and
stable.
Table 1-3: Power/Ground Pin Description
Power/Ground Pins
Pin Name
Type
Pin No
Pin Description
VCCIO
P
6, 26, 39,
55
Digital Power for I/O pins, 3.3V
Please add a 0.1uF bypass capacitor between each VCCIO and GND.
VCCK
P
10, 22,
37, 57
Digital Power for core, 1.2V
Please add a 0.1uF bypass capacitor between each VCCK and GND.
GND
P
EPAD
Ground for all Analog and Digital Power.
VCC33A_REG
P
36
Analog Power for Regulator, 3.3V
VO12
P
35
1.2V Power Output of on-chip 3.3V to 1.2V Regulator.
The regulator requires an external capacitor (at least 3.3 μF) with low ESR for
frequency compensation and stability maintenance.
VCC12A_TX
P
13
Analog Power for PCIe Transmitter, 1.2V.
Please add a 0.1 and 10 uF bypass capacitor between VCC12A_TX and GND.
VCC12A_D
P
14
Analog Power for PCIe Transceiver, 1.2V.
Please add a 0.1 and 10 uF bypass capacitor between VCC12A_D and GND.
VCC12A_AUX
P
18
Analog Power for PCIe Auxiliary, 1.2V.
Please add a 0.1 and 10 uF bypass capacitor between VCC12A_AUX and
GND.

11
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.1 GPIO and Mode Setting
Table 1-4: GPIO and Mode Setting Pin Description
GPIO and Mode Setting Pins
Pin Name
Type
Pin No
Pin Description
GPIO[23:8]
B5/CU/4m
31, 32,
33, 34,
38, 40,
41, 42,
43, 44,
45, 46,
47, 48,
49, 50
General Purpose I/O signal
GPIO[15:8] are only valid when CHIP_MODE = 100 and 110.
GPIO[23:16] are only valid when CHIP_MODE = 100 and 110 and Port 4 was
disabled by HWCFGEE. Please reference to Section 3.
GPIO7
B5/CU/8m
60
General Purpose Output signal
GPIO7 has an optional function is external wakeup pin in input direction. When
AX99100 entered to L2 mode, this pin can be used to wakeup AX99100 also.
GPIO6
B5/CU/8m
59
General Purpose Output signal
GPIO6 has an optional function is a power-down control signal to power down
the external transceiver when AX99100 entered to L2 mode. This function can be
enabled by setting bit1 and the polarity selection is bit0 in configuration
EEPROM, offset 0x55.
GPIO5/
CHIP_MODE[2]
O5/ 8m
58
General Purpose Output signal when chip exited reset and operating in normal
functional mode.
These pins are input direction during chip reset use to bootstrap the mode setting
to decide the chip operation mode. Please reference to Section 3.1.
GPIO4/
CHIP_MODE[1]
O5/8m
56
GPIO3/
CHIP_MODE[0]
O5/8m
54
GPIO2
O5/8m
53
General Purpose Output signal when chip exited reset and operating in normal
functional mode.
This pin should be connected to the AUX 3.3V in PCIe slot via an external
pull-up resistor. It is used to detect the 3.3V AUX is existed or not.
GPIO1
B5/CU/8m
52
General Purpose I/O signal
GPIO0
B5/CU/8m
51
General Purpose I/O signal
Note: Above GPIO[7:0] are only valid when CHIP_MODE ≠000.

12
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.2 Serial Interface for COM Port
Table 1-5: Serial Interface for COM Port Pin Description
Serial Interface for COM Port
Pin Name
Type
Pin No
Pin Description
TXD1
TXD2
TXD3
TXD4
O5/4m
9
68
50
42
Transmit data output to transceiver or IrDA data output to IR LED
DTR1
DTR2
DTR3
DTR4
B5/PD/4m
8
67
49
41
Data Terminal Ready
These pins have internal pull-down during reset. If there is the external pull-up
resisters connected to these pins separately, it will work for RS-232 function with
active low. Otherwise, it will work for RS-485 function (DXEN) with active high
and the output can be enabled by register (the default is disabled). Please
reference to Section 3.2.
RTS1
RTS2
RTS3
RTS4
O5/4m
7
66
48
40
Request to send (Active Low)
Note: These pins will be changed to RXEN when Software enabled RS-485
function for the corresponding ports.
RXD1
RXD2
RXD3
RXD4
I5/PU
5
65
47
38
Serial received data input from transceiver or IrDA data input from IrDA
detector.
RI1
RI2
RI3
RI4
I5
3
64
46
34
Ring Indicator (Active Low)
DSR1
DSR2
DSR3
DSR4
I5
4
63
45
33
Data Set Ready (Active Low)
DCD1
DCD2
DCD3
DCD4
I5
2
62
44
32
Data Carrier Detect (Active Low)
CTS1
CTS2
CTS3
CTS4
I5
1
61
43
31
Clear to send (Active Low)
Note 1: Serial Port 1 and 2 are only valid when CHIP_MODE = 001, 011, 101 and 110.
Note 2: Serial Port 3 and 4 are only valid when CHIP_MODE = 011.

13
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.3 Serial Interface for Multi-Protocol Transceiver
Table 1-6: Serial Interface for Multi-Protocol Transceiver Pin Description
Serial interface for Multi-Protocol Transceiver
Pin Name
Type
Pin No
Pin Description
TXD1
TXD2
TXD3
TXD4
O5/4m
9
68
50
42
Transmit data output to transceiver or IrDA data output to IR LED
DXEN1
DXEN2
DXEN3
DXEN4
B5/PD/4m
8
67
49
41
Driver Enable
These pins have internal pull-down during reset. If there is the external pull-up
resisters connected to these pins separately, it will work for RS-232 function with
active low. Otherwise, it will work for RS-485 function with active high and the
output can be enabled by register (the default is disabled). Please reference to
Section3.2.
RTS1
RTS2
RTS3
RTS4
O5/4m
7
66
48
40
Request to send (Active Low)
RXD1
RXD2
RXD3
RXD4
O5/PU/4m
5
65
47
38
Serial received data input from transceiver or IrDA data input from IrDA
detector.
485EN1
485EN2
485EN3
485EN4
O5/4m
3
64
46
34
Interface Selection
1: RS-485 selected
0: RS-232 selected
485TE1
485TE2
485TE3
485TE4
O5/4m
4
63
45
33
RS485 Termination Enable for transceiver.
RXEN1
RXEN2
RXEN3
RXEN4
O5/4m
2
62
44
32
Receiver Enable
1: Enable Receiver
0: Disable Receiver
Note: Software should enable RS-485 function for the corresponding ports first.
CTS1
CTS2
CTS3
CTS4
I5
1
61
43
31
Clear to send (Active Low)
Note 1: Serial Port 1 and 2 are only valid when CHIP_MODE = 010, 100 and 111.
Note 2: Serial Port 3 and 4 are only valid when CHIP_MODE = 101 and 111.

14
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.4 Serial Port with GPIO enabled
Table 1-7: Serial Interface for GPIO Enabled Pin Description
Enable Serial Port for GPIO mode
Pin Name
Type
Pin No
Pin Description
TXD1
TXD2
TXD3
TXD4
O5/4m
9
68
50
42
Transmit data output to transceiver or IrDA data output to IR LED
SP1_GPIO0
SP2_GPIO0
SP3_GPIO0
SP4_GPIO0
B5/CU/4m
8
67
49
41
Serial Port GPIO
SP1_GPIO1
SP2_GPIO1
SP3_GPIO1
SP4_GPIO1
B5/CU/4m
7
66
48
40
Serial Port GPIO
RXD1
RXD2
RXD3
RXD4
O5/PU/4m
5
65
47
38
Serial receives data input from transceiver or IrDA data input from IrDA detector.
SP1_GPIO5
SP2_GPIO5
SP3_GPIO5
SP4_GPIO5
B5/CU/4m
3
64
46
34
Serial Port GPIO
SP1_GPIO3
SP2_GPIO3
SP3_GPIO3
SP4_GPIO3
B5/CU/4m
4
63
45
33
Serial Port GPIO
SP1_GPIO4
SP2_GPIO4
SP3_GPIO4
SP4_GPIO4
B5/CU/4m
2
62
44
32
Serial Port GPIO
SP1_GPIO2
SP2_GPIO2
SP3_GPIO2
SP4_GPIO2
B5/CU/4m
1
61
43
31
Serial Port GPIO
Note: Above Serial Port GPIO function are valid when Software enabled the GPIO function by register setting in each
functions.

15
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.5 Serial Port with Function Disabled
Table 1-8: Serial Interface with Port2 and Port4 Disabled Pin Description
Serial Interface with Port2 and Port4 Disabled
Pin Name
Type
Pin No
Pin Description
TXD2
TXD4
O5/4m
68
42
No any function for this pin due to disable.
SP1_GPIO0
SP3_GPIO0
B5/CU/4m
67
41
Serial Port GPIO(Note 2)
SP1_GPIO1
SP3_GPIO1
B5/CU/4m
66
40
Serial Port GPIO
RXD2
RXD4
O5/PU/4m
65
38
No any function for this pin due to disable.
SP1_GPIO5
SP3_GPIO5
B5/CU/4m
64
34
Serial Port GPIO
SP1_GPIO3
SP3_GPIO3
B5/CU/4m
63
33
Serial Port GPIO
SP1_GPIO4
SP3_GPIO4
B5/CU/4m
62
32
Serial Port GPIO
SP1_GPIO2
SP3_GPIO2
B5/CU/4m
61
31
Serial Port GPIO
Note 1: If Port 2 or Port 4 are disabled by setting HWCFGEE when CHIP_MODE setting for those serial port
interface, all pins for Port 2 or Port 4 (excluded TXD and RXD) will be re-directed to the GPIO function of
Port 1 and Port 3. Thus the pins of Port 1 and Port 3 cannot be set for GPIO function by software register
setting.
Note 2: Pin 67 and 41 will be re-directed to DTR1/DXEN1 and DTR3/DXEN3 also. However software can enable it
to GPIO function as SP1_GPIO0 and SP3_GPIO0.

16
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.6 Parallel Port
Table 1-9: Parallel Port Pin Description
Parallel Port Interface
Pin Name
Type
Pin No
Pin Description
STROBEn
SPP:
O5/T/4m
Others:
O5/4m
42
Set active low by the host to transfer data into the input latch of the peripheral.
Data are valid while STROBEn is low.
The pin is open-drain when operation in SPP mode, otherwise, is direct drive
logic 0 or logic 1.
AUTOLFn
SPP:
O5/T/4m
Others:
O5/4m
41
The interpretation of this signal varies from peripheral to peripheral. Set low by
host to put some printers into auto-line feed mode
The pin is open-drain when operation in SPP mode, otherwise, is direct drive
logic 0 or logic 1.
INITn
SPP:
O5/T/4m
Others:
O5/4m
40
Pulsed low by the host in conjunction with IEEE 1284 Active low to reset the
interface and force a return to Compatibility Mode idle phase
The pin is open-drain when operation in SPP mode, otherwise, is direct drive
logic 0 or logic 1.
SELECTINn
SPP:
O5/T/4m
Others:
O5/4m
38
Set low by host to select peripheral
The pin is open-drain when operation in SPP mode, otherwise, is direct drive
logic 0 or logic 1.
PP_DIR
O5/4m
52
Parallel Port Data Transfer Direction Indications
ACKn
I5
34
Pulsed low by the peripheral to acknowledge transfer of a data byte from the host
BUSY
I5
33
Driven high by the peripheral to indicate that it is not ready to receive data
PAPEREND
I5
32
Driven high by the peripheral to indicate that is has encountered an error in its
paper path. The meaning of this signal varies from peripheral to peripheral.
Peripherals shall set FAULTn low whenever PAPEREND is set high
SELECT
I5
31
Set high to indicate that the peripheral is online
FAULTn
I5
51
Set low by the peripheral to indicate that an error has occurred. The meaning of
this signal varies from peripheral to peripheral
DATA[7:0]
B5/4m
43, 44,
45, 46,
47, 48,
49, 50
Driven by the host in Compatibility Mode and the negotiation phase, not used in
Nibble Mode, and bidirectional in all other modes
Note: Above signals are only valid when CHIP_MODE = 010 and 001.

17
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.7 SPI Interface
Table 1-10: SPI Pin Description
SPI Interface
Pin Name
Type
Pin No
Pin Description
SS[2:0]
O5/4m
41, 40, 34
SPI Slave Select for SPI master.
SS[2:0] is a tri-stateable output, which requires an external pull-up resistor.
SCLK
O5/4m
31
SPI CLocK for SPI master.
SCLK is a tri-stateable output. At Mode 0 or 2, SCLK requires external pull-down
resistor; while at Mode 1 or 3, SCLK requires external pull-up resistor.
MOSI
O5/4m
32
SPI Master Output Slave Input line for SPI master.
When High Speed SPI controller is operating in master module, MOSI is used to
transmit serial data and is a tri-stateable output.
MISO
I5
33
SPI Master Input Slave Output line for SPI master.
When High Speed SPI controller is operating in master module, MISO is used to
receive serial data.
SWAKEn
I5/PU
38
SPI External Wakeup
SWAKEn is external wakeup for SPI interface.
GPIO16
B5/8m
42
General Purpose I/O signal
Note: Above signals are only valid when CHIP_MODE = 100 and 110.

18
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
1.4.8 Local Bus Interface
Table 1-11: Local Bus Pin Description
Local Bus Interface
Pin Name
Type
Pin No
Pin Description
A0/ CHIP_MODE[2]
O5/4m
58
Local Bus Address Bus, A[2:0]
These pins are input direction during chip reset use to bootstrap the mode setting
to decide the operation mode. Please reference to Section 3.1.
In Local Bus mode, These pins should always use external pull-down resistors to
ground.
A1/ CHIP_MODE[1]
O5/4m
56
A2/ CHIP_MODE[0]
O5/4m
54
A3
O5/4m
53
Local Bus Address Bus, A[3]
This pin should be connected to the 3.3V AUX in PCIe slot via an external
pull-up resistor. It is used to detect the 3.3V AUX is existed or not.
A[9:4]
O5/4m
60, 59,
47, 48,
49, 50
Local Bus Address Bus, A[9:4]
The A[9:0] are outputs and provide up to 10 Local Bus address lines in
non-multiplexed address and data bus format
AD[15:0]
B5/4m
61, 62,
63, 64,
65, 66,
67, 68,
1, 2,
4, 3,
5, 7,
8, 9
Data and Address bus
Multiplexed mode: address on bus when ALE issued, other time data on bus
Non-multiplexed mode: data always on bus
RSTO
B5/4m
52
Local Bus Reset Output
The output polarity can be decided by adding external pull up/down resistor. If
connected this pin to VCCIO via external pull-up resistor, means RSTO is active
high. If pull-down to ground, means active low.
CLKO
B5/8m
51
Local Bus Clock Output
CS1n
CS0n
O5/4m
41
42
Local Bus Chip Select 1
Local Bus Chip Select 0
DREQ[1:0]
I5
44, 46
DMA Request
DACK[1:0]
O5/4m
43, 45
DMA Acknowledge
INT[1:0]
I5
31, 32
Interrupt
ALE
O5/4m
40
Address Latch Enable
When in non-multiplexed mode, ALE can choice remap to A[10] (detail
description same as above A[9:0]) or address latch enable for ISA bus type
When in multiplexed mode, ALE for address latch enable
RDn
O5/4m
38
Local Bus Read Cycle
WRn
O5/4m
34
Local Bus Write Cycle
RDY
I5
33
Local Bus Device Ready
Note: Above signals are only valid when CHIP_MODE = 000.

19
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
2Function Description
Clocks/Resets and Power2.1
The AX99100 requires an external clock from PCIe connector (CLKP and CLKN) as the main clock source. PCIe
PHY feeds this 100 MHz differential clock to internal PLL to generate the 125MHz clock for PCIe PHY and
Controller or other peripherals used. The AX99100 also supports a clock input from external oscillator for those
special baud rate generated for UART, SPI and Local Bus used if needs. Thus there are three different clock sources
(100Mhz, 125Mhz and EXT_CLK) in this chip can be selected for some interfaces to generate the desired baud rate to
meet the application requirement.
There are two reset sources in the AX99100. During the VCCK power-on, the internal Power-On-Reset (POR) can
generate a reset pulse to reset all the function blocks when the VCCK power pin rise to certain threshold voltage level.
Another reset is RSTn pin, which is from PCIe slot to perform the PCIe Fundamental Reset. If AX99100 is not in L2
power sate, this reset pin will logical and with POR reset to reset all the function blocks also. AX99100 is designed to
meet the PCIe standard for Power Management State.
The AX99100 contains an internal 3.3V to 1.2V low-dropout-voltage regulator. The internal regulator provides up to
150mA of driving current for the 1.2V core and analog power of this chip to satisfy the worst-case power
consumption scenario.
In order to support PCIe power management, all VCCIO power and the regulator power supply should connect to
PCIe Auxiliary Power (3.3Vaux) to maintain the deep sleep and wakeup event.
PCIe Operation2.2
PCIe is divided into three major blocks as Physical layer, Data link layer and Transaction layer. Physical link layer
and Transaction layer together comprises PCIe core. Their functionality is explained below.
PCIe PHY
The Physical Layer isolates the Transaction and Data Link Layers from the signaling technology used for Link data
interchange. The Physical Layer is divided into the logical and electrical functional sub-blocks.
The logical sub-block has two main sections: A transmit section that prepares outgoing information passed from the
Data Link Layer for transmission by the electrical sub-block, and a receiver section that identifies and prepares
received information before passing it to the Data Link Layer. The logical sub-block and electrical sub-block
coordinate the state of each transceiver through a status and control register interface or functional equivalent. The
logical sub-block directs control and management functions of the Physical Layer.
The electrical sub-block contains a Transmitter and a Receiver. The Transmitter is supplied by the logical sub-block
with Symbols which it serializes and transmits onto a Lane. The Receiver is supplied with serialized Symbols from
the Lane. It transforms the electrical signals into a bit stream which is de-serialized and supplied to the logical
sub-block along with a Link clock recovered from the incoming serial stream.
The Physical Layer is responsible for the following
Power management
Width and lane negotiation
Reset/hot-plug control
8-bit/10-bit encoding/decoding
Scrambling/de-scrambling
Embedded clock tuning and alignment
Transmission and reception circuit
Elastic buffer
Data Link Layer

20
Copyright © 2016 ASIX Electronics Corporation. All rights reserved.
AX99100
PCIe to Multi I/O Controller
The Data Link Layer
The Data Link Layer acts as an intermediate stage between the Transaction Layer and the Physical Layer. The Data
Link Layer is responsible for reliably conveying Transaction Layer Packets (TLPs) supplied by the Transaction
Layer across a PCI Express Link to the other component’s Transaction Layer
The Data Link Layer is responsible for the following
Link management including TLP acknowledgment
Retry mechanism in case of a non-acknowledged packet
Flow control across the Link (transmission and reception)
Power management
CRC generation and CRC checking
Error reporting
Transaction Layer/User Interface Layer
Transaction layer and User interface layer together perform all transaction layer functionalities. User interface layer
defines a plug-and-play type interface mechanism to accept TLPs from user space for transmission, and to pass
received TLPs on reception.
The Transaction Layer is primarily responsible for the following
Assembly and disassembly of Transaction Layer packets (TLPs)
Storage of configuration information
Converts received Completion packets into data payloads,
Updates status information
Responsible for flow control services
Ordering rules
Power management services
PCIe Bridge
Master Slave Bridge is divided into PCIe packet formatter, PCIe target interface block, Mater arbiter, Slave
de-mux and VCI interface block.
All detail description for PCIe operation, please reference to the standard of “PCI Express Base Specification”.