ASIX AX11001 User manual

ASIX ELECTRONICS CORPORATION Release Date: 5/3/2006
4F, NO.8, Hsin Ann Rd., HsinChu Science Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: [phone]
FAX: [phone]
http://www.asix.com.tw
AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
Document No: AX1100x/V0.6/05/03/06
Features
MCU
8-bit pipelined RISC, single cycle per
instruction with maximum operating frequency
of 100Mhz (100 MIPS)
100% software compatible with standard
8051/80390
2 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority
levels
Support power management unit,
programmable watchdog timer, and 3 16-bit
timer/counters
Debug port for connecting to In-Circuit
Emulation (ICE) adaptor
5 channels of programmable counter array
On-chip Program and Data Memory
Embed 128K (AX11001) or 512KB (AX11005)
Flash memory without bank select, and 16KB
SRAM for program code mirroring
Support initial Flash memory programming via
UART or ICE adaptor, the so-called In System
Programming (ISP)
Support run-time firmware or driver update
through Ethernet or UART, the so-called In
Application Programming (IAP)
Embed 32KB SRAM for data memory
Buffer Management
Embed DMA engine and memory arbiter.
Support 3 DMA channels for high performance
data movement needed for network protocol
stack processing
On-chip 10/100M Fast Ethernet MAC and PHY
Integrate IEEE 802.3 10BASE-T/100BASE-TX
compatible Fast Ethernet MAC and PHY with
dedicated 12KB SRAM for Ethernet packet
buffering. Support full-duplex and half-duplex
operations
Support twisted pair crossover detection and
auto-correction
Support wakeup via Link-up, Magic packet,
Wakeup frame or external input pin
TCP/IP
Build in TCP/IP accelerator in hardware to
improve network transfer throughput. Support
IP/TCP/UDP/ICMP/IGMP checksum and ARP
in hardware
Support TCP, UDP, ICMP, IGMP, IPv4,
DHCP, BOOTP, ARP, and HTTP in software
Communication Interface
3 UART interface (with 1 supporting
921.6Kbps and Modem control)
1 I2C interface (master and slave mode)
SPI/Micro wire interface (3 masters or 1 slave
mode)
1 1-Wire controller interface (master mode)
10/100 Ethernet PHY interface
Support network boot over Ethernet using DHCP and
TFTP
Integrate on-chip voltage regulator and require single
power supply of 3.3V only
Integrate on-chip oscillator and PLL. Require only
one 25Mhz crystal to operate
Integrate on-chip power-on reset circuit
80-pin LQFP RoHS package
Operating temperature: 0 to 70°C or -40 to 85°C
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product Description
The AX11001/AX11005, Single Chip Micro-controller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a
System-on-Chip (SoC) solution which offers a high performance embedded micro-controller and rich communication
peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol
stack, the AX11001/AX11005 provides very cost effective networking solution to enable simple, easy, and low cost
Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial
equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote
management. In addition to stand-alone application, the AX11001/AX11005, with popular TCP/IP protocol suite on-chip
and built-in I2C bus or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from
system CPU in an embedded system.
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
Target Applications
Figure 1: Target Application Diagram
Typical System Block Diagrams
I2C bus
Temperature Sensor
Humidit
y
Senso
r
Figure 2: Environment Monitoring or Network Sensor and Remote Control
1-Wire bus
Rain Gau
g
e Senso
r
Barometric Pressure Sensor
Wind Direction Senso
r
Solar Radiance Senso
r
Thermocou
p
le Senso
r
EEPROM
AX11001/
AX11005
Ma
g
netic + RJ45
GPIO Relay
LED
ASIX ELECTRONICS CORPORATION
2

AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
Figure 3: Serial to Ethernet Converter
Figure 4: ZigBee to Ethernet Converter
Figure 5: BlueTooth to Ethernet Converter
Figure 6: Network Co-processor for Embedded CPU
UART
RS232 Transceiver
ZigBee Transceiver
SPI bus
I2C bus
I2C bus or SPI bus
AX11001/ EEPROM I2C bus
AX11005
Ma
g
netic + RJ45
AX11001/ EEPROM
AX11005
Ma
g
netic + RJ45
UART
Embedded CPU
(ARM, MISP,
x86, PowerPC)
BlueTooth Transceiver
I2C bus
AX11001/ I2C bus
EEPROM AX11001/
AX11005
AX11005 EEPROM
Ma
g
netic + RJ45 Ma
g
netic + RJ45
ASIX ELECTRONICS CORPORATION
3

AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
Table of Contents
1.0 INTRODUCTION...................................................................................................................7
1.1 GENERAL DESCRIPTION....................................................................................................................................... 7
1.2 AX11001/AX11005 BLOCK DIAGRAM ............................................................................................................... 7
1.3 AX11001/AX11005 PINOUT DIAGRAM .............................................................................................................. 8
1.4 SIGNAL DESCRIPTION .......................................................................................................................................... 9
2.0 FUNCTION DESCRIPTION.................................................................................14
2.1 CLOCK GENERATION ......................................................................................................................................... 14
2.2 RESET GENERATION .......................................................................................................................................... 14
2.3 VOLTAGE REGULATOR ...................................................................................................................................... 14
2.4 CPU CORE AND DEBUGGER .............................................................................................................................. 15
2.4.1 CPU Core .................................................................................................................................................15
2.4.2 Debugger ..................................................................................................................................................15
2.5 ON-CHIP FLASH MEMORY................................................................................................................................. 17
2.6 MEMORY ARBITER AND BOOT LOADER ............................................................................................................ 18
2.6.1 Boot Loader..............................................................................................................................................18
2.6.2 Memory Arbiter.........................................................................................................................................18
2.6.3 Flash Programming Controller................................................................................................................18
2.7 DMA ENGINE.................................................................................................................................................... 19
2.8 INTERRUPT CONTROLLER .................................................................................................................................. 19
2.9 WATCHDOG TIMER............................................................................................................................................ 20
2.10 POWER MANAGEMENT UNIT ............................................................................................................................. 21
2.10.1 PMM.........................................................................................................................................................21
2.10.2 STOP Mode...............................................................................................................................................22
2.11 TIMERS AND COUNTERS .................................................................................................................................... 22
2.12 UARTS.............................................................................................................................................................. 23
2.12.1 UART 0 and UART 1 ................................................................................................................................23
2.12.2 UART 2 .....................................................................................................................................................24
2.13 GPIOS............................................................................................................................................................... 25
2.14 TCP/IP OFFLOAD ENGINE ................................................................................................................................. 25
2.15 10/100M ETHERNET MAC................................................................................................................................26
2.16 10/100M ETHERNET PHY ................................................................................................................................. 27
2.17 PROGRAMMABLE COUNTER ARRAY .................................................................................................................. 27
2.18 I2C CONTROLLER.............................................................................................................................................. 28
2.19 1-WIRE CONTROLLER........................................................................................................................................ 29
2.20 SPI CONTROLLER .............................................................................................................................................. 29
3.0 MEMORY MAP DESCRIPTION...................................................................31
3.1 I2C CONFIGURATION EEPROM MEMORY MAP ............................................................................................... 31
3.1.1 Length (0x00)............................................................................................................................................31
3.1.2 Flag (0x01) ...............................................................................................................................................32
3.1.3 Multi-function Pin Setting (0x02~0x03)....................................................................................................32
3.1.4 Programmable Output Driving Strength (0x04).......................................................................................33
3.1.5 Node ID (0x06~0x0B)...............................................................................................................................34
3.1.6 Maximum Packet Size (0x0C~0x0D) ........................................................................................................34
3.1.7 Primary/Secondary PHY Type and PHY ID (0x0E~0x0F) .......................................................................34
3.1.8 Pause Frame Low Water and High Water Mark (0x10~0x11).................................................................34
3.1.9 TOE TX VLAN Tag (0x14~0x15)..............................................................................................................35
3.1.10 TOE RX VLAN Tag (0x16~0x17)..............................................................................................................35
3.1.11 TOE ARP Cache Timeout (0x18)..............................................................................................................35
3.1.12 TOE Source IP Address (0x19~0x1C) ......................................................................................................35
3.1.13 TOE Subnet Mask (0x1D~0x20)...............................................................................................................35
3.1.14 TOE L4 DMA Transfer Gap (0x21)..........................................................................................................35
3.2 PROGRAM MEMORY MAP.................................................................................................................................. 36
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
3.3 EXTERNAL DATA (XDATA) MEMORY MAP...................................................................................................... 36
3.4 INTERNAL DATA MEMORY AND SFR REGISTER MAP ....................................................................................... 36
4.0 DETAILED FUNCTION DESCRIPTION..........................................38
4.1 CLOCK GENERATION ......................................................................................................................................... 38
4.2 RESET GENERATION .......................................................................................................................................... 38
4.3 VOLTAGE REGULATOR ...................................................................................................................................... 38
4.4 CPU CORE & DEBUGGER.................................................................................................................................. 38
4.5 ON-CHIP FLASH MEMORY................................................................................................................................. 38
4.6 MEMORY ARBITER & BOOT LOADER ................................................................................................................ 38
4.7 DMA ENGINE.................................................................................................................................................... 38
4.8 INTERRUPT CONTROLLER .................................................................................................................................. 38
4.9 WATCHDOG TIMER............................................................................................................................................ 38
4.10 POWER MANAGEMENT UNIT ............................................................................................................................. 38
4.11 TIMERS AND COUNTERS .................................................................................................................................... 38
4.12 UART ............................................................................................................................................................... 38
4.13 GPIO................................................................................................................................................................. 38
4.14 TCP/IP OFFLOAD ENGINE ................................................................................................................................. 38
4.15 10/100M ETHERNET MAC................................................................................................................................38
4.16 10/100M ETHERNET PHY ................................................................................................................................. 38
4.16.1 Ethernet PHY Register Description..........................................................................................................38
4.17 PROGRAMMABLE COUNTER ARRAY .................................................................................................................. 39
4.18 I2C CONTROLLER.............................................................................................................................................. 39
4.19 ONE-WIRE CONTROLLER................................................................................................................................... 39
4.20 SPI CONTROLLER .............................................................................................................................................. 39
5.0 ELECTRICAL SPECIFICATIONS............................................................40
5.1 DC CHARACTERISTICS ...................................................................................................................................... 40
5.1.1 Absolute Maximum Ratings ......................................................................................................................40
5.1.2 Recommended Operating Condition.........................................................................................................40
5.1.3 Leakage Current and Capacitance...........................................................................................................41
5.1.4 DC Characteristics of 3.3V I/O Pins ........................................................................................................41
5.1.5 DC Characteristics of 3.3V with 5V Tolerant I/O Pins.............................................................................41
5.1.6 DC Characteristics of Voltage Regulator.................................................................................................42
5.2 POWER CONSUMPTION ...................................................................................................................................... 43
5.3 POWER-UP SEQUENCE ....................................................................................................................................... 44
5.4 AC TIMING CHARACTERISTICS ......................................................................................................................... 45
5.4.1 Clock Timing.............................................................................................................................................45
5.4.2 I2C Interface Timing.................................................................................................................................46
5.4.3 SPI Interface Timing.................................................................................................................................47
5.4.4 One-Wire Interface Timing.......................................................................................................................48
5.4.5 Programmable Counter Array Interface Timing ......................................................................................50
5.4.6 Timer 0/1/2 Interface Timing....................................................................................................................51
5.4.7 10/100M Ethernet PHY Interface Timing.................................................................................................52
6.0 PACKAGE INFORMATION...............................................................................53
7.0 ORDERING INFORMATION............................................................................54
8.0 REVISION HISTORY....................................................................................................54
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
List of Figures
FIGURE 1: TARGET APPLICATION DIAGRAM........................................................................................................................ 2
FIGURE 2: ENVIRONMENT MONITORING OR NETWORK SENSOR AND REMOTE CONTROL ................................................... 2
FIGURE 3: SERIAL TO ETHERNET CONVERTER..................................................................................................................... 3
FIGURE 4: ZIGBEE TO ETHERNET CONVERTER .................................................................................................................... 3
FIGURE 5: BLUETOOTH TO ETHERNET CONVERTER ............................................................................................................ 3
FIGURE 6: NETWORK CO-PROCESSOR FOR EMBEDDED CPU ............................................................................................... 3
FIGURE 7: AX11005 BLOCK DIAGRAM (AX11001 IS THE SAME BUT WITH EMBEDDED 128KB FLASH MEMORY)............. 7
FIGURE 8: AX11001/AX11005 PINOUT DIAGRAM ............................................................................................................. 8
FIGURE 9: TYPICAL DEBUGGER AND HARDWARE ASSISTED DEBUGGER (HAD2) SYSTEM DIAGRAM .............................. 16
FIGURE 10: FLASH MEMORY PROGRAMMING SYSTEM CONFIGURATION .......................................................................... 19
FIGURE 11: WATCHDOG TIMER BLOCK DIAGRAM ............................................................................................................ 21
FIGURE 12: TIMERS 0, 1, AND 2 BLOCK DIAGRAM ............................................................................................................ 23
FIGURE 13: I/O BUFFER OF RXD0 PIN OF UART 0 AND RXD1 PIN OF RXD1.................................................................. 24
FIGURE 14: THE I/O BUFFER OF GPIO PINS...................................................................................................................... 25
FIGURE 15:PROGRAMMABLE COUNTER ARRAY BLOCK DIAGRAM.................................................................................... 27
FIGURE 16: I2C CONTROLLER BLOCK DIAGRAM .............................................................................................................. 28
FIGURE 17: 1-WIRE CONTROLLER BLOCK DIAGRAM ........................................................................................................ 29
FIGURE 18: SPI CONTROLLER BLOCK DIAGRAM .............................................................................................................. 30
FIGURE 19: THE PROGRAM MEMORY MAP OF 1T 80390 CPU CORE ................................................................................ 36
FIGURE 20: THE EXTERNAL DATA MEMORY MAP OF 1T 80390 CPU CORE..................................................................... 36
FIGURE 21: THE INTERNAL MEMORY MAP OF 1T 80390 CPU CORE................................................................................ 37
FIGURE 22: POWER-UP SEQUENCE TIMING DIAGRAM AND TABLE .................................................................................... 44
FIGURE 23: XTL25P CLOCK TIMING DIAGRAM AND TABLE............................................................................................. 45
FIGURE 24: LB_CLK CLOCK TIMING DIAGRAM AND TABLE............................................................................................ 45
FIGURE 25: SPI MASTER CONTROLLER TIMING DIAGRAM AND TABLE ............................................................................ 47
FIGURE 26: SPI SLAVE CONTROLLER TIMING DIAGRAM AND TABLE ............................................................................... 47
FIGURE 27: ONE-WIRE RESET PULSE AND PRESENCE PULSE TIMING DIAGRAM AND TABLE ............................................ 48
FIGURE 28: ONE-WIRE WRITE AND READ TIME SLOT TIMING DIAGRAM AND TABLE ...................................................... 49
FIGURE 29: ONE-WIRE STPZ RESET AND READ WRITE TIMING DIAGRAM AND TABLE ................................................... 49
FIGURE 30: ECI TIMING DIAGRAM AND TABLE ................................................................................................................ 50
FIGURE 31: CEX[4:0] TIMING DIAGRAM AND TABLE ....................................................................................................... 50
FIGURE 32: TM_CK[2:0] TIMING DIAGRAM AND TABLE ................................................................................................. 51
FIGURE 33: TM_GT[2:0] TIMING DIAGRAM AND TABLE.................................................................................................. 51
FIGURE 34: 10/100M ETHERNET PHY TRANSMITTER WAVEFORM AND SPEC.................................................................. 52
List of Tables
TABLE 1: PINOUT DESCRIPTION .......................................................................................................................................... 9
TABLE 2: INTERRUPT CONTROLLER SUMMARY................................................................................................................. 20
TABLE 3: I2C CONFIGURATION EEPROM MEMORY MAP................................................................................................ 31
TABLE 4: SFR REGISTER MAP .......................................................................................................................................... 37
TABLE 5: I2C MASTER CONTROLLER TIMING TABLE ....................................................................................................... 46
TABLE 6: I2C SLAVE CONTROLLER TIMING TABLE .......................................................................................................... 46
TABLE 7: 10/100M ETHERNET PHY RECEIVER SPEC........................................................................................................ 52
ASIX ELECTRONICS CORPORATION
6

AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
1.0 Introduction
1.1 General Description
The AX11001/AX11005, Single Chip Micro-controller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a
System-on-Chip (SoC) solution which offers a high performance embedded micro-controller and rich communication
peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol
stack, the AX11001/AX11005 provides very cost effective networking solution to enable simple, easy, and low cost
Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial
equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote
management. In addition to stand-alone application, the AX11001/AX11005, with popular TCP/IP protocol suite on-chip
and built-in I2C bus or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from
system CPU in an embedded system.
The AX11001/AX11005 needs only a 25Mhz crystal to operate and its internal operating frequency is programmable
from 25Mhz, 50Mhz, and 100Mhz, depending on system performance and power consumption trade-off.
AX11001/AX11005 integrate an internal voltage regulator that requires only single power supply of 3.3V to operate, and
an internal power-on-reset circuitry that simplifies the external reset circuitry on PCB. The package is 80-pin low-profile
LQFP RoHS package and the operating temperature range are 0 to 70°C or -40 to 85°C. Please refer to ordering
information for part number details.
1.2 AX11001/AX11005 Block Diagram
DB_DO
DB_CLKO
DB_DI
Figure 7: AX11005 Block Diagram (AX11001 is the same but with embedded 128KB Flash Memory)
3 UART
16 GPIO
5 Prog. Counter Array
I2C (Master/Slave)
SPI (Master/Slave)
1-Wire
(
Master
)
Memory Arbiter &
Boot Loade
r
Watchdog Time
r
Power Management Uni
t
3 Timer/Counters
Interru
p
t Controlle
r
DMA Engine
TCP/IP Offload Engine
10/100 Ethernet MAC
12KB SRAM
10/100 Ethernet PHY
512KB Flash Memory
16KB Program SRAM
32KB Data SRAM
Debugger
1T 8051/80390 Core
3.3 to 1.8V
Regulator
XTL25P, XTL25N
OSC & PLL
& Clock Gen.
SYSCK_SEL[1:0],
EXT_WKUP
Power-On-Reset
& Reset Gen.
TM[2:1]_CK, TM[2:1]_GT,
INT[1:0]
RXD[2:0], TXD[2:0], CTS, DSR,
RI, DCD, RTS, DTR, DE, RE_N
P0[7:0], P1[7:0]
ECI, CEX[4:0]
SCL, SDA
SCLK, MOSI, MISO, SS[2:0]
DQ, STPZ
TXOP, TXON, RXIP, RXIN,
FD_CL_LED, SPD_LED,
LNK_LED, RSET_BG
RST_N
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
1.3 AX11001/AX11005 Pinout Diagram
The AX11001/AX11005 is housed in an 80-pin LQFP package.
P01 / TXD2
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16
21
22
23
24
25
26
27
28
29
30
31
ASIX
AX11001
AX11005
17 18 19 20
32
33
34
35
36
37
38
39
40
62
61
69
68
67
66
63
64
65
76
75
74
73
70
71
72
80
77
78
79
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P07/DTR
VCC
K
VCCIO
TM2_CK / CEX3
P03 / DS
R
XDATA2
XDATA3
VCCIO
TM2_GT / CEX4
P04 / RI
SS1 / DQ
SS2 / STPZ
GND
P15 VCCIO
P13/RE_N
VCC
K
P11 P10
VCC18 P12/DE
VCC3A
P17
TXD0
P16
P14
SCL
K
RSET_BG
VCCIO
GND
XTL25N
VCC18A
GND3A
VCCK
TXON GND3R
XDATA6
VCC3R
RXD1/ECI
TXD1/CEX_0
EXT_WKUP/INT0
SCL
SDA
INT1
RST_N
MISO
LB_CL
K
GND
VCCIO
VCC
K
MOSI
VCC
K
DB_CLKO / SPD_LED
SS0
RXD0
P02 / CTS
P00 / RXD2
VCC
K
P05 / DCD
GND
DB_DI / LNK_LED
P06/RTS
VCCK
XDATA0
XDATA1
XDATA4
XDATA5
SYSCK_SEL1
XTL25P
GND18A
RXIP RXIN
TXOP VCC18A
GND18A
SYSCK_SEL0
TM1_GT / CEX2
TM1_CK / CEX1
DB_DO / FD_CL_LED
Figure 8: AX11001/AX11005 Pinout Diagram
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
1.4 Signal Description
The following abbreviations apply to the following pin description table. Please note some I/O pins with multiple signal
definitions on the same pin may have different pin attribute in the “Type” column for different signal definition. For
example, pin 9 can be defined as P00 or RXD2. In the case of P00 the Type = B5/T/4m/8m/PU, while in the case of RXD2
the Type = I5. In other words, the PU (internal pull-up) only takes effective during P00 signal mode, and RXD2 signal
mode will not have the PU.
I18 Input, 1.8V 4m
4mA driving strength
I3 Input, 3.3V 8m
8mA driving strength
I5 Input, 3.3V with 5V tolerant PU
Internal Pull-Up (75K)
O18 Output, 1.8V PD
Internal Pull-Down (75K)
O3 Output, 3.3V P
Power and ground pin
O5 Output, 3.3V with 5V tolerant S
Schmitt Trigger
B3
B5 Bi-directional I/O, 3.3V
Bi-directional I/O, 3.3V with 5V
tolerant
T AB Tri-state
Analog Bi-directional I/O
AO
Analog Output
Table 1: Pinout Description
Pin Name Type Pin No Pin Description
CPU Debugger/Interrupt/Timers/GPIO Interface
DB_DI I5/PU 18 CPU debugger data input.
Note that this is a multi-function pin (DB_DI/LNK_LED), depending on the
setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for
details.
DB_CKO O5/8m 19 CPU debugger clock output.
Note that this is a multi-function pin (DB_CKO/SPD_LED), depending on the
setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for
details.
DB_DO O5/8m 20 CPU debugger data output.
Note that this is a multi-function pin (DB_DO/FD_CL_LED), depending on the
setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for
details.
INT [1:0] I5/PU 73, 70 Interrupt inputs, active low or falling edge trigger.
Note that the INT0 is a dual-function input pin sharing with EXT_WKUP pin.
TM[2:1]_CK I5 7, 5 Timer 2, 1 external clock input.
Note that these are multi-function pins (TM2_CK/CEX3, TM1_CK/CEX1),
depending on the setting of TM_PSEL bits in I2C EEPROM offset 0x03, see
section 3.1.3 for details.
TM[2:1]_GT I5 8, 6 Timer 2, 1 external gate control input.
Note that these are multi-function pins (TM2_GT/CEX4, TM1_GT/CEX2),
depending on the setting of TM_PSEL bits in I2C EEPROM offset 0x03, see
section 3.1.3 for details.
P0 [7:0] B5/T/4m/8
m/PU
22, 21,
16, 14,
12, 11,
10, 9
Port 0 general purpose input and output pins.
Note that these are multi-function pins (P07/DTR, P06/RTS, P05/DCD, P04/RI,
P03/DSR, P02/CTS, P01/TXD2, P00/RXD2), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The
output driving strength is programmable, by P0_ODS bit in I2C Configuration
EEPROM offset 0x04. See section 3.1.4 for details.
P1 [7:0] B5/T/4m/8
m/PU
62, 61,
60, 58,
57, 55,
54, 53
Port 1 general-purpose input and output pins.
Note that these are multi-function pins (P17, P16, P15, P14, P13/RE_N, P12/DE,
P11, P10), depending on the setting of P1_PSEL bits in I2C EEPROM offset
0x02, see section 3.1.3 for details. The output driving strength is programmable,
by P1_ODS bit in I2C Configuration EEPROM offset 0x04. See section 3.1.4 for
details. UART Interface
RXD0 B5/4m/PU 65 UART 0 serial receive data.
TXD0 O5/4m 67 UART 0 serial transmit data.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
RXD1 B5/4m/PU 68 UART 1 serial receive data.
Note that this is a multi-function pin (RXD1/ECI), depending on the setting of
U1_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details.
TXD1 O5/4m/8m 69 UART 1 serial transmit data.
Note that this is a multi-function pin (TXD1/CEX0), depending on the setting of
U1_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The
output driving strength is programmable, by PCA_ODS bit in I2C Configuration
EEPROM offset 0x04. See section 3.1.4 for details.
RXD2 I5 9 UART 2 serial receive data.
Note that this is a multi-function pin (P00/RXD2), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details.
TXD2 O5/4m/8m 10 UART 2 serial transmit data.
Note that this is a multi-function pin (P01/TXD2), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The
output driving strength is programmable, by P0_ODS bit in I2C Configuration
EEPROM offset 0x04. See section 3.1.4 for details.
CTS I5 11 UART 2 clear to send.
Note that this is a multi-function pin (P02/CTS), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details.
DSR I5 12 UART 2 data set ready.
Note that this is a multi-function pin (P03/DSR), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details.
RI I5 14 UART 2 ring indicator.
Note that this is a multi-function pin (P04/RI), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details.
DCD I5 16 UART 2 data carriers detect.
Note that this is a multi-function pin (P05/DCD), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details.
RTS O5/4m/8m 21 UART 2 request to send.
Note that this is a multi-function pin (P06/RTS), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The
output driving strength is programmable, by P0_ODS bit in I2C Configuration
EEPROM offset 0x04. See section 3.1.4 for details.
DTR O5/4m/8m 22 UART 2 data terminal ready.
Note that this is a multi-function pin (P07/DTR), depending on the setting of
P0_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The
output driving strength is programmable, by P0_ODS bit in I2C Configuration
EEPROM offset 0x04. See section 3.1.4 for details.
DE O5/4m/8m 55 UART 2 transceiver driver output enable.
Note that this is a multi-function pin (P12/DE), depending on the setting of
P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The
output driving strength is programmable, by P1_ODS bit in I2C Configuration
EEPROM offset 0x04. See section 3.1.4 for details.
RE_N O5/4m/8m 57 UART 2 transceiver receiver output enable, active low.
Note that this is a multi-function pin (P13/RE_N), depending on the setting of
P1_PSEL bits in I2C EEPROM offset 0x02, see section 3.1.3 for details. The
output driving strength is programmable, by P1_ODS bit in I2C Configuration
EEPROM offset 0x04. See section 3.1.4 for details.
Serial Interface
SCL B5/4m/8m/
PU
71 I2C serial clock line for operating in either master or slave mode.
Note that the output driving strength is programmable, by I2C_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
SDA B5/4m/8m/
PU
72 I2C serial data line for operating in either master or slave mode.
Note that the output driving strength is programmable, by I2C_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
SS0 B5/T/4m 77 SPI slave select 0. This is a tri-stateable output when operating in SPI master
mode or an input when operating in SPI slave mode. When operating in SPI
master mode, it needs an external pulled-up resistor.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
SS[2:1] O5/T/4m/8
m
3, 2 SPI slave select 2, 1. These are tri-stateable outputs (an external pulled-up resistor
needed) and used in SPI master mode only.
Note that these are multi-function pins (SS2/STPZ, SS1/DQ), depending on the
setting of SPI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for
details. The output driving strength is programmable, by SPI_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
SCLK B5/T/4m/8
m
79 SPI clock. This is a tri-stateable output when operating in SPI master mode or an
input when operating in SPI slave mode. In SPI master mode operating at mode 0
or 2, user should pull low this pin with external resistor, while operating at mode
1 or 3, user should pull up this pin with external resistor.
Note that the output driving strength is programmable, by SPI_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
MISO B5/T/4m/8
m
1 SPI master input slave output line. This is used to receive serial data when the SPI
controller is configured as SPI master or to transmit serial data when it is
configured as SPI slave. When operating in SPI slave mode, this is a tri-stateable
output, which needs an external pulled-up resistor.
Note that the output driving strength is programmable, by SPI_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
MOSI B5/T/4m/8
m
80 SPI master output slave input line. This is used to transmit serial data when the
SPI controller is configured as SPI master or to receive serial data when it is
configured as SPI slave. When operating in SPI master mode, this is a
tri-stateable output, which needs an external pulled-up resistor.
Note that the output driving strength is programmable, by the SPI_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
DQ B5/4m/8m 2 One-wire serial data input and output. This is an open-drain pin, which needs an
external pulled-up resistor or a strong pull-up through a PMOS transistor.
Note that this is a multi-function pin (SS1/DQ), depending on the setting of
SPI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The
output driving strength is programmable, by the SPI_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
STPZ O5/4m/8m 3 One-wire strong pull-up is used for device with a stiff power supply for high
current application. This is active low.
Note that this is a multi-function pin (SS2/STPZ), depending on the setting of
SPI_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details. The
output driving strength is programmable, by the SPI_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
Programmable Counter Array Interface
ECI I5 68 Programmable counter array external clock input.
Note that this is a multi-function pin (RXD1/ECI), depending on the setting of
U1_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for details.
CEX [4:0] B5/4m/8m 8, 7, 6, 5,
69
Programmable counter array module 4~0 input and output.
Note that these are multi-function pins (TM2_GT/CEX4, TM2_CK/CEX3,
TM1_GT/CEX2, TM1_CK/CEX1, TXD1/CEX0), depending on the setting of
U1_PSEL and TM_PSEL bits in I2C EEPROM offset 0x03, see section 3.1.3 for
details. The output driving strength is programmable, by the PCA_ODS bit in I2C
Configuration EEPROM offset 0x04. See section 3.1.4 for details.
Ethernet PHY Interface
RXIP AB 44 Receive differential data input positive pin for 10BASE-T/100BASE-TX in MDI
mode or transmit differential data output positive pin in MDIX mode.
RXIN AB 45 Receive differential data input negative pin for 10BASE-T/100BASE-TX in MDI
mode or transmit differential data output negative pin in MDIX mode.
TXOP AB 47 Transmit differential data output positive pin for 10BASE-T/100 BASE-TX in
MDI mode or receive differential data input positive pin in MDIX mode.
TXON AB 48 Transmit differential data output negative pin for 10BASE-T/100 BASE-TX in
MDI mode or receive differential data input negative pin in MDIX mode.
RSET_BG AO 41 For Ethernet PHY’s internal biasing. Please connect to GND3A through a
12.3Kohm +/-1% resistor.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
LNK_LED O5/8m 18 Link status LED indicator. This pin drives low continuously when the Ethernet
link is up and drives low and high in turn (blinking) when Ethernet PHY is in
receiving or transmitting state.
Note that this is a multi-function pin (DB_DI/LNK_LED), depending on the
setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for
details.
SPD_LED O5/8m 19 Ethernet speed LED indicator. This pin drives low when the Ethernet PHY is in
100BASE-TX mode and drives high when in 10BASE-T mode.
Note that this is a multi-function pin (DB
_
CKO/SPD_LED), depending on the
setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for
details.
FD_CL_LED O5/8m 20 Full duplex and collision detected LED indicator. This pin drives low when the
Ethernet PHY is in full-duplex mode and drives high when in half duplex mode.
When in half duplex mode and the Ethernet PHY detects collision, it will be
driven low.
Note that this is a multi-function pin (DB_DO/FD_CL_LED), depending on the
setting of DBG_PSEL bit in I2C EEPROM offset 0x01, see section 3.1.2 for
details. Misc. Pins
RST_N I5/PU/S 74 Chip reset input, active low. This is the external reset source used to reset this
chip. This input feeds to the internal power-on reset circuitry, which then provides
the main reset source of this chip.
XTL25P I18 39 25Mhz crystal or oscillator clock input. The recommended reference frequency is
25Mhz +/- 0.005% (i.e. 25Mhz +/- 1250hz).
XTL25N I18 38 25Mhz crystal or oscillator clock input. The recommended reference frequency is
25Mhz +/- 0.005% (i.e. 25Mhz +/- 1250hz).
LB_CLK B5/8m 64 This pin can be a clock source for the system logic or a clock output of the
operating system clock. When used as clock source, the input frequency should
be either 25Mhz or 50Mhz (so that the internal timer/counter can work properly).
When used as clock output, it shall output the operating system clock for external
peripheral device use. The mode of operation is determined by XDATA1 and
XDATA2 state during chip hardware reset.
XDATA1 XDATA2 LB_CLK
Pulled-up Pulled-up The LB_CLK instead of internal 100Mhz PLL is
the clock source for operating system clock. In
this case, user can provide either 25Mhz or
50Mhz clock input to this pin. Also, the
SYSCK_SEL should be set to 00 or 01
accordingly so that the internal timer/counter can
work properly.
Pulled-down Pulled-up The LB_CLK is a clock output, which provides
the operating system clock of the chip to the
external peripheral device.
Pulled-up Pulled-down The LB_CLK is not used. In this case, please add
a pulled-up resistor to this pin such that it draws
minimum current.
SYSCK_SEL[
1:0]
I3 32, 26 Operating system clock frequency selection:
00: Set the operating CPU clock to 25Mhz.
01: Set the operating CPU clock to 50Mhz.
10: Reserved.
11: Set the operating CPU clock to 100Mhz.
EXT_WKUP I5/PU 70 External remote-wakeup trigger input pin, rising edge.
Note that the EXT_WKUP is a dual-function input pin sharing with INT0 pin.
XDATA0 B3/8m 24 For normal operation, please pull down with 10Kohm during chip hardware reset.
N
ote that after removal of chip hardware reset, this pin shall toggle during normal
operation. Therefore, user should not tie it directly to GND for configuration
purpose.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
XDATA1 B3/8m 25 For normal operation, please pull up with 10Kohm during chip hardware reset.
N
ote that after removal of chip hardware reset, this pin shall toggle during normal
operation. Therefore, user should not tie it directly to VCC for configuration
purpose.
XDATA2 B3/8m 27 For normal operation, please pull down with 10Kohm during chip hardware reset.
N
ote that after removal of chip hardware reset, this pin shall toggle during normal
operation. Therefore, user should not tie it directly to GND for configuration
purpose.
XDATA3 B3/8m 28 For normal operation, please pull down with 10Kohm during chip hardware reset.
N
ote that after removal of chip hardware reset, this pin shall toggle during normal
operation. Therefore, user should not tie it directly to GND for configuration
purpose.
XDATA4 B3/8m 30 This is used as BURN_FLASH_EN.
Pull up with 1Kohm during chip hardware reset to temporarily enable Flash
programming via UART0. This will put the CPU in reset state during Flash
programming. Pull down with 10Kohm during chip hardware reset to allow the
CPU to run normally after reset and disable Flash programming via UART0.
N
ote that after removal of chip hardware reset, this pin shall toggle during Flash
programming or normal operation. Therefore, user should not tie it directly to
VCC or GND for configuration purpose.
XDATA5 B3/8m 31 This is used as BURN_FLASH_921K.
Pull up with 10Kohm during chip hardware reset when the BURN_FLASH_EN
is also pulled up to enable Flash memory programming at higher speed as
921.6Kbps baud rate. When the BURN_FLASH_EN is pulled down, this has no
effect. Pull down with 10Kohm during chip hardware reset when the
BURN_FLASH_EN is also pulled up to enable Flash memory programming at
normal speed as 115.2Kbps baud rate. When the BURN_FLASH_EN is pulled
down, this has no effect.
N
ote that after removal of chip hardware reset, this pin shall toggle during Flash
programming or normal operation. Therefore, user should not tie it directly to
VCC or GND for configuration purpose.
XDATA6 B3/8m 33 This is used as I2C_BOOT_DIS.
Pull up with 10Kohm during chip hardware reset if the optional I2C EEPROM is
not used for storing configuration data. Pull down with 10Kohm during chip
hardware reset if the I2C EEPROM is used for storing configuration data.
Note that after removal of chip hardware reset, this pin shall toggle during normal
operation. Therefore, user should not tie it directly to VCC or GND for
configuration purpose.
On-chip Regulator Pins
VCC3R P 51 3.3V power supply to on-chip 3.3V to 1.8V voltage regulator.
GND3R P 50 Ground pin of on-chip 3.3V to 1.8V voltage regulator.
VCC18 P 52 1.8V voltage output of on-chip 3.3V to 1.8V voltage regulator. Please add 1uF
capacitor between VCC18 and GND3R.
Power and Ground Pins
VCCK P 4, 15,
23, 36,
56, 66,
75
Digital core power, 1.8V.
VCCIO P 13, 29,
35, 59,
76
Digital I/O power, 3.3V.
GND P 17, 34,
63, 78
Digital ground for core and I/O.
VCC18A P 37, 46 Analog power for oscillator, PLL, and Ethernet PHY differential I/O pins, 1.8V
GND18A P 40, 49 Analog ground for oscillator, PLL, and Ethernet PHY differential I/O pins.
VCC3A P 42 Analog power for bandgap, 3.3V.
GND3A P 43 Analog ground for bandgap.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
2.0 Function Description
2.1 Clock Generation
The AX11001/AX11005 integrates an internal 25Mhz oscillator, which allows the chip to operate cost effectively with
just an external 25Mhz crystal. The 25Mhz oscillator provides reference clock to the internal PLL circuit, which generate
a free-run 100Mhz clock source for system logic and a 125Mhz clock source for the internal Ethernet PHY use. The
operating system clock is derived from the 100Mhz clock source from PLL and is programmable between 25Mhz,
50Mhz, and 100Mhz, based on the setting of SYSCK_SEL [1:0] input pins. The users can trade off between system
performance and power consumption to decide the best operating system clock frequency.
The AX11001/AX11005 supports a deep power-down mode (CPU STOP mode) where the internal 25Mhz crystal
oscillator and PLL circuit can be completely disabled to consume minimum power. The AX11001/AX11005 also
supports the Power Management Mode (PMM) where the operating system clock frequency is reduced to 1/100 of the
original frequency (i.e., 0.25Mhz, 0.5Mhz, and 1Mhz) to reduce power consumption during PMM mode.
The AX11001/AX11005 also has an external clock source input pin called LB_CLK, which can be used as clock source
for system logic. For more details on chip clock configuration and distribution, please refer to section 4.1.
2.2 Reset Generation
The AX11001/AX11005 integrates an internal power-on-reset circuit, which can simplify the external reset circuitry on
PCB design. The power-on-reset circuit shall generate a reset pulse to reset system logic after 1.8V core power ramping
up to 1.2V (typical threshold). The external hardware reset input pin, RST_N, is fed directly to the input of power-on-reset
circuit and can also be used as additional hardware reset source to reset the system logic.
If the internal power-on-reset circuit is used as main reset source, user shall connect RST_N pin to a simple RC reset,
which shall generate a low level of at least 4 msec intervals after 1.8V core power ramping up to 1.8V to correctly reset the
system logic. If the system has a dedicated reset source connecting to RST_N, this reset source shall also generate a low
level of at least 4 msec intervals after 1.8V core power ramping up to 1.8V to correctly reset the system logic. For more
details on chip reset distribution, please refer to section 4.2.
2.3 Voltage Regulator
The AX11001/AX11005 contains an internal 3.3V to 1.8V low-dropout-voltage and low-standby-current voltage
regulator. The internal regulator provides up to 240mA of driving current for the 1.8V core/analog power of the chip to
satisfy the worst-case power consumption scenario. Also for the purpose of lowering power consumption in deep
power-down mode or PMM mode, the internal regulator can operate in standby mode to consume less current when the
required driving current is less than 30mA. For more details on voltage regulator DC characteristic, please refer to section
5.1.6.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
2.4 CPU Core and Debugger
2.4.1 CPU Core
The 1T 8051/80390 CPU core of AX11001/AX11005 is an ultra high performance, speed optimized, 8-bit embedded
controller dedicated for operation with fast (on-chip) memories. The CPU core has been designed with a special concern
about performance to power consumption ratio. The CPU core is 100% binary-compatible with the industry standard
8051 8-bit micro-controller. The CPU core can address up to 128KB/512 KB of linear program space. The CPU core has
Pipelined RISC architecture, which can be 10 times faster compared to standard architecture and executes 100 million
instructions per second when operating in 100Mhz. The main features of 1T 8051/80390 CPU core are listed below, for
more details, please refer to section 4.4.
 100% software compatible with industry standard 8051
 Maximum operating clock frequency of 100M Hz
 Pipelined RISC architecture enables to execute instructions 10 times faster compared to standard 8051
○19-bit FLAT program addressing mode – 80C390 instructions set
○16-bit LARGE program addressing mode – 80C51 instructions set
 24 times faster multiplication
 12 times faster addition
 256 bytes of internal (on-chip) Data Memory
 Up to 128K/512K bytes of Program Memory
○On-chip SRAM used for mirrored program: 0 to 16K bytes
○On-chip Flash memory used for program: 0 to 128K/512K bytes in FLAT mode
 Up to 32K bytes of External Data Memory
○On-chip SRAM used for External Data Memory: 0 to 32K bytes
 User programmable Program Memory wait states for wide range of memory speed
 User programmable External Data Memory wait states for wide range of memory speed
2.4.2 Debugger
The Debugger inside AX11001/AX11005 provides an in-circuit emulator feature and it is used to connect to an external
In-Circuit-Emulation (ICE) adaptor board, which manages communication between the Debugger inside
AX11001/AX11005 and the Debug Software on a PC. As shown in Figure 9, the Hardware Assisted Debugger (HAD2) is
the ICE adaptor board.
The HAD2 is a small hardware adapter that manages communication between the Debugger inside AX11001/AX11005
and an USB port of the host PC running Debug Software. The USB communication interface to target host PC is at USB
Full speed and its power supply comes directly from the USB port.
The Debug Software is a Windows based application. It is fully compatible with all existing 8051/80390 C compilers and
Assemblers. The Debug Software allows user to work in two major modes: software simulator mode and hardware
debugger mode. Those two modes assure software validation in simulation mode and then real-time debugging of
developed software inside AX11001/AX11005 using debugger mode. Once loaded, the program may be observed in
Source Window, run at full-speed, single stepped by machine or C level instructions, or stopped at any of the breakpoints.
For more detailed description about the Debug Software, please refer to AX11000 Serise Software Debugging Tool User
Guide.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
Figure 9: Typical Debugger and Hardware Assisted Debugger (HAD2) System Diagram
The main features of Debugger inside AX11001/AX11005 are listed below,
 Processor execution control
○Run, Halt
○Reset
○Step into instruction
○Skip Instruction
 Read-write all processor contents
○Program Counter (PC)
○Program Memory
○Internal (direct) Data Memory
○Special Function Registers (SFRs)
○External Data Memory
 Code execution breakpoints - one real-time PC breakpoint
 Hardware execution watch-points
○Two at Internal (direct) Data Memory
○Two at Special Function Registers (SFRs)
○Two at External Data Memory
 Hardware watch-points activated at a
○certain address by any write into memory
○certain address by any read from memory
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
○certain address by write into memory a required data
○certain address by read from memory a required data
 Unlimited number of software watch-points
○Internal (direct) Data Memory
○Special Function Registers (SFRs)
○External Data Memory
 Unlimited number of software breakpoints - Program Memory (PC)
 Automatic adjustment of debug data transfer speed rate between HAD and CPU core
 Communication interface - DTAG three wire communication
2.5 On-Chip Flash Memory
The AX11001/AX11005 embeds an on-chip Flash memory of 128/512K bytes. The main features of the Flash memory
are listed below,
 Requires only 3.3V power for read, erase and program operations
 Fast read access time: 55ns
 Command register architecture
 Byte programming time: 9us (typical)
 Sector Erase (Sector structure of AX11001: 16K Byte x 1, 8K Byte x 2, 32K Byte x1, and 64K Byte x1)
 Sector Erase (Sector structure of AX11005: 16K Byte x 1, 8K Byte x 2, 32K Byte x1, and 64K Byte x7)
 Auto Erase (chip & sector) and Auto Program
 Automatically erase any combination of sectors with Erase Suspend capability
 Automatically program and verify data at specified address
 Erase Suspend/Erase Resume
 Suspends sector erase operation to read data from, or program data to, any sector that is not being erased,
then resumes the erase operation.
 Status Reply
 Data# Polling & Toggle bit for detection of program and erase operation completion.
 Sector protection
 Hardware method to disable any combination of sectors from program or erase operations
 Temporary sector unprotect allows code changes in previously locked sectors.
 100,000 minimum erase/program cycles
 20 years data retention
For more detailed description, please refer to section 4.5.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
2.6 Memory Arbiter and Boot Loader
The memory arbiter and boot loader of AX11001/AX11005 support three major functions - Boot loader, Memory arbiter,
and Flash programming controller, as described in following sections.
2.6.1 Boot Loader
The boot loader shall activate right after hardware reset (either power-on-reset or RST_N input) or software reboot
command (via SFR register CSREPR). It shall automatically perform copying the program code from Flash memory to
on-chip 16KB SRAM for “program code mirroring”.
The “program code mirroring” allows the program code residing on on-chip Flash memory space 0~16K bytes to be
mirrored to on-chip 16Kbytes SRAM before the 1T 80390 CPU starts running. This on-chip 16Kbytes SRAM located at
program memory space 0~16K bytes of the 1T 80390 CPU will be used to execute program code with 0 wait state to
achieve top performance of 100 MIPS. During time of firmware update via Ethernet or UART, the 16K bytes of mirrored
program code on SRAM shall perform Flash write commands to write new firmware into the Flash memory. This allows
the program code being executed continuously while the Flash memory is being updated. For more details, please refer to
section 4.6.
2.6.2 Memory Arbiter
The memory arbiter manages Program memory and External Data (xDATA) memory bus access. It arbitrates the access
of xDATA memory between 1T 80390 CPU and the Direct Memory Access (DMA) engine.
The xDATA memory access could come from 1T 80390 CPU and the DMA from TCP/IP Offload Engine (TOE). The
arbitration priority is that, the 1T 80390 CPU’s access to Program memory and xDATA memory has higher priority and
the DMA for TOE is lower. For more details, please refer to section 4.6.
2.6.3 Flash Programming Controller
The Flash programming controller supports In-System-Programming (ISP) for on-chip Flash memory of
AX11001/AX11005 on PCB via UART 0 interface of AX11001/AX11005. When enabled (via BURN_FLASH_EN pin),
it allows on-chip Flash memory to be programmed by ASIX’s Flash Programming utilities software on a PC with a
standard RS-232 port, as shown in Figure 10. The link speed of AX11001/AX11005’s UART 0 used for communicating
to the PC’s RS-232 port can be chosen to be either 921.6K or 115.2K bps (via BURN_FLASH_921K pin). When
developing software for AX11001/AX11005 or manufacturing the system with AX11001/AX11005 on it, the ASIX’s
Flash Programming utilities software can provide easy and fast Flash memory update capability.
During Flash programming process, the Flash Programming Controller (FPC) in AX11001/AX11005 shall receive
commands from Flash Programming utilities software through the UART 0 interface. The commands received are in form
of packets from which FPC will decode, execute, and then acknowledge the result back to the software utilities. The
command handshaking structure is simple and flexible to simplify the FPC design while at the same time addressing the
long programming time, complex programming procedures, command compatibility issues of Flash memory. For more
details, please refer to section 4.6.
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
COM port
UART0
RS232 XCVR
Running ASIX’s
Flash Programming
utilities software
Flash Programming
Controller
On-chip Flash
memory
AX11001/AX11005
Figure 10: Flash Memory Programming System Configuration
2.7 DMA Engine
The direct memory access (DMA) engine of AX11001/AX11005 handles External Data (xDATA) memory read and
write access for TCP/IP Offload Engine (TOE) as well as bulk data copy for software DMA.
The TOE can receive packets from Ethernet MAC and store them in xDATA memory via DMA write access, or it can
transmit packets to Ethernet MAC from xDATA memory via DMA read access.
The DMA engine also can support software DMA, which performs bulk data copy from one region of xDATA memory to
another region in a timely manner, based on software configuration. The hardware based DMA engine can greatly reduce
the time spending in bulk data movement very often needed in network protocol stack processing, and, hence, help
achieve better performance on micro-controller computing power. For more details, please refer to section 4.7.
2.8 Interrupt Controller
The interrupt controller of AX11001/AX11005 supports 2 external interrupt pins, INT0 and INT1, with each having two
levels of interrupt priority control. They can be in high or low-level priority group (setting via SFR register IP, EIP). The
2 external interrupt pins can be activated at low level or by a falling edge.
As shown in Table 2 below, the interrupt controller also supports various interrupt requests internal to the
AX11001/AX11005, again each having two levels of interrupt priority control. For more details, prefer to section 4.8.
Interrupt
Sources Function Description Active level Vector Natural Priority
INT 0 The external interrupt input pin, INT0 Active low
or falling
edge
0x03 1
Timer 0 The internal Timer 0 interrupt request 0x0B 2
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AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
INT 1 The external interrupt input pin, INT1 Active low
or falling
edge
0x13 3
Timer 1 The internal Timer 1 interrupt request 0x1B 4
UART 0 The internal UART 0 interrupt request 0x23 5
Timer 2 The internal Timer 2 interrupt request 0x2B 6
UART 1 The internal UART 1 interrupt request 0x33 7
INT 2 The internal DMA transfer interrupt request for TOE/SW DMA mode,
please set to high priority
0x3B 8
INT 3 The internal programmable counter array interrupt request 0x43 9
INT 4 The internal peripheral interrupt request for TOE, MAC/PHY, I2C, SPI,
1-Wire, UART2, etc.
0x4B 10
INT 5 The internal SW DMA complete and SW timer timeout interrupt 0x53 11
INT 6 The wake-up interrupt request (to resume from CPU STOP mode) 0x5B 12
Watchdog Internal watchdog interrupt 0x63 13
Table 2: Interrupt Controller Summary
2.9 Watchdog Timer
The watchdog timer of AX11001/AX11005 is a user programmable clock counter that can serve as:
 A time-base generator
 An event timer
 System supervisor
As shown in Figure 11, the watchdog timer is driven by the main system clock, which is supplied to a series of dividers.
The divider output is selectable, and determines interval between timeouts. When the timeout is reached, an interrupt flag
will be set, and if enabled, a reset will occur (to reset CPU core). The interrupt flag will cause an interrupt to occur if its
individual enable bit is set and the global interrupt enable is set. The reset and interrupt are discrete functions that may be
acknowledged or ignored, together or separately for various applications. For more details, please refer to section 4.9.
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