Atmel ATA6264 User manual

Features
•Maximum Supply Voltage 40V
•One Programmable/Adjustable Boost Converter
•Two Programmable Buck Converters
•One Programmable Linear Regulator
•OTP Customer Mode
•16-bit Serial Interface
•Two ISO9141 Interfaces (One Interface Programmable to LIN Functionality)
•Watchdog
•Various Diagnosis Functions
•5 Voltage Sources Tailored to Resistor Measurement
•Charge Pump
•Small, 44-pin Package
•ESD Protection Against 2kV and 4kV
1. Description
With the introduction of the ATA6264, Atmel®introduces a new generation of airbag
power supplies for future airbag systems tailored to the needs of the automotive
industry. It is designed in Atmel’s 0.8 micron BCDMOS technology. ATA6264 contains
all the necessary blocks to supply the microcontroller, the firing capacitors, and
peripheral components of the airbag system. The power supply specifically fulfills the
power requirements of dual-voltage microcontrollers used in modern ECUs. The inte-
grated watchdog and diagnosis blocks additionally support the safety aspects. The
8-MHz 16-bit SPI enables a high communication speed. Despite the high-level func-
tionality, ATA6264 comes in a space-saving QFP44 package.
Airbag Power
Supply IC
ATA6264
Preliminary
4929B–AUTO–01/07

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4929B–AUTO–01/07
ATA6264 [Preliminary]
Figure 1-1. Block Diagram
VVCORE
VVPERI
VVSAT
VEVZ
CP Logic
VCORE-
Regulator
Internal Supply
Reference
VPERI-
Regulator
EVZ-
Regulator
VSAT-
Regulator
K30
GEVZ
SVSAT
VSAT
COMCOI
COMCOO
VCORE
SVCORE
VPERI
SVPERI
COMSATI
COMSATO
COMEVZO
FBEVZ
EVZ
GNDB
OCEVZ
GKEY-
Logic
UZP
USP
AMUX
ISO9141
IASG
Serial Interface
Watchdog
Reset
RESQ2
IASG1
IASG2
IASG4
ISENS
GNDA
UZP
IASG5
IASG3
K2
K1
GNDD
RESQ
MOSI
VSAT
SVSAT
VBATT
VBATT
CP_OUT
IREF
VINT USP SCLK
SSQ
CP
K15
MISO
RxD2
TxD1
RxD1
TxD2

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4929B–AUTO–01/07
ATA6264 [Preliminary]
1.1 Block Description
1.1.1 Integrated Boost Converter EVZ
With an external n-channel FET, the integrated boost converter EVZ provides 3 different volt-
ages adjustable via the serial interface for the energy reserve and firing capacitors. Two
voltages are fixed values; one voltage can be adjusted using an external resistive divider.
1.1.2 Integrated Buck Converter VSAT
The integrated buck converter VSAT is a fully integrated step-down converter supplied by the
boost converter, EVZ, and providing 7.8V, 9.1V, or 10.4V. The user can program the voltage via
an OTP system.
1.1.3 Integrated Buck Converter VCORE
The integrated buck converter VCORE is a fully integrated step-down converter supplied either
by the boost converter, EVZ, or by the battery, and providing 1.88V, 2.5V, or 5V. The user can
program the voltage via an OTP system.
1.1.4 Linear Regulator VPERI
The linear regulator, VPERI, is supplied from the buck converter VSAT and provides an accurate
voltage of 3.3V ±3% or 5V ±4% as a supply for sensitive elements such as sensors and ADC
references with the current capability of 100 mA. The user can program the voltage via an OTP
system. With a sophisticated power-sequencing concept of VCORE and VPERI, ATA6264 sup-
ports dual-voltage-supply microcontrollers, so that under all conditions the voltage difference
between the two linear regulator voltages never drops below a defined value. This measure
guarantees the safe operation of the system.
1.1.5 Blocks Included
• A general purpose comparator USP, for, for example, low battery voltage detection
• A band gap as reference for all internal voltages and currents
• Two ISO9141 interfaces, one of which is configurable via OTP in accordance with the LIN
specification
• Five constant voltage sources with current-to-voltage mirrors used for resistance
measurements, such as buckle switch detection in the range from –0.5 mA to –40 mA
• An AMUX block with push-pull buffer stage provides the output of all analog values such as
voltage sources, low voltage detection, or the chip temperature for continuous diagnosis
• A 16-bit serial interface for the communication with the microcontroller which includes a 16-bit
shift register, a 16-bit latch, and a decoder-logic block
• A watchdog to monitor the microcontroller and to generate reset signals in the case of failure
• Internal oscillator generates internal clock signals
• GKEY function to control the main switch of the ECU via a logic signal

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4929B–AUTO–01/07
ATA6264 [Preliminary]
2. Pin Configuration
Figure 2-1. Pinning QFP44
K15
EVZ
VSAT
GNDD
VINT
COMSATI
SVPERI
VPERI
GNDA
VCORE
SVSAT
USP
K30
K2
IASG1
IASG2
IASG3
ISENS
TxD1
IASG5
IASG4
K1
RESQ
RxD2 RxD1
TxD2
MISO
SSQ
SCLK
MOSI
RESQ2
IREF
UZP
COMEVZO GNDB GEVZ OCEVZ FBEVZ CP SVCORE CP-OUT COMCOO COMCOI COMSATO
1
2
3
4
9
10
11
5
6
8
7
33
32
31
30
25
24
23
29
28
26
27
44 43 42 41 35 343638 373940
12 13 14 15 21 222018 191716
Table 2-1. Pin Description
Pin Symbol Function
1 USP Comparator input
2 K30 Continuous connection to the car battery
3 K1 Bus line of 1st ISO9141 interface
4 K2 Bus line of 2nd ISO9141 interface
5 IASG1 Output of voltage source 1
6 IASG2 Output of voltage source 2
7 IASG3 Output of voltage source 3
8 IASG4 Output of voltage source 4
9 IASG5 Output of voltage source 5
10 ISENS Output of the current mirror from the IASGx interface
11 TXD1 Data input of the 1st ISO9141 interface
12 RESQ Reset output
13 RXD2 Data output of the 2nd ISO9141 interface
14 RXD1 Data output of the 1st ISO9141 interface
15 TXD2 Data input of the 2nd ISO9141 interface
16 MISO Data output of the serial interface
17 SSQ Chip select of the serial interface
18 SCLK Clock input of the serial interface
19 MOSI Data input of the serial Interface
20 RESQ2 Redundant reset output
21 IREF Connection for the external reference resistor
22 UZP Analog measurement output

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ATA6264 [Preliminary]
23 VPERI Input for the VPERI regulator, internally used VPERI supply
24 SVPERI Output of VPERI regulator power transistor
25 GNDA Analog GND
26 VCORE Input for VCORE regulator
27 COMSATI Input of the VSAT externally compensated error amplifier
28 VINT Output of internal supply voltage
29 GNDD Digital GND
30 VSAT Input for VSAT regulator, internally used VSAT supply
31 SVSAT Output of VSAT regulator power transistor
32 EVZ Input for EVZ regulator, internally used EVZ supply
33 K15 Connection to car battery via the ignition key
34 COMSATO Output of the VSAT externally compensated error amplifier
35 COMCOI Input of the VCORE externally compensated error amplifier
36 COMCOO Output of the VCORE externally compensated error amplifier
37 CP-OUT Switchable output of charge pump voltage
38 SVCORE Output of VCORE regulator power transistor
39 CP Charge pump output
40 FBEVZ Input for external resistor divider to adjust EVZ voltage
41 OCEVZ Input for overcurrent measurement of the EVZ regulator
42 GEVZ Gate driver output for the external FET of the EVZ regulator
43 GNDB GND connection of all power stages
44 COMEVZO Output of the EVZ externally compensated error amplifier
Table 2-1. Pin Description
Pin Symbol Function

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ATA6264 [Preliminary]
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.
Parameters Remark Minimum Maximum Unit
Voltage at pins, connected directly or
indirectly to the car battery
(K30, K15, USP)
Any combination of one or more pins
applied with any voltage between the
limits
K30 and K15 connected via diode to VBatt.
USP connected via minimum 5 kΩto VBatt
(maximum reverse current 5 mA).
–0.3 +45 V
Voltage at pins, connected directly or
indirectly to the car battery (K1, K2)
Any combination of one or more pins
applied with any voltage between the
limits
–25 +45 V
Voltage at pins, connected directly or
indirectly to the car battery (IASG1,
IASG2, IASG3, IASG4, IASG5)
Any combination of one or more pins
applied with any voltage between the
limits
Voltage
necessary to
drive –40 mA
stored in 20 µH
45 V
Voltage at ECU internal pins (FBEVZ,
EVZ, VSAT)
Any combination of one or more pins
applied with any voltage between the
limits
–0.3 +45 V
Maximum rate of change at pin VSAT 1V/µs
Voltage at ECU internal pins (SVSAT,
SVCORE)
Any combination of one or more pins
applied with any voltage between the
limits
–1 +45 V
Voltage at ECU internal pins (CP,
CP-OUT)
Any combination of one or more pins
applied with any voltage between the
limits
–0.3 +56 V
Voltage at ECU internal pins (GEVZ,
OCEVZ)
Any combination of one or more pins
applied with any voltage between the
limits
–0.3 +10 V
Voltage at ECU internal pins (COMEVZO,
COMSATO, COMSATI, VPERI, SVPERI,
VCORE, COMCOI, COMCOO, IREF, UZP,
ISENS, RXD1, TXD1, RXD2, TXD2,
RESQ, RESQ2, MISO, MOSI, SSQ,
SCLK, VINT)
These voltages can be applied in any
combination with any voltage between the
limits
–0.3 +7 V
Current at logic pins Connected to voltages outside of
maximum voltage ratings via resistor –3 +3 mA
ESD classification at pins connected to
devices outside the ECU (K30, K15)
Human body model (HBM) HBM
AEC Q100-002
±4000 V

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ATA6264 [Preliminary]
ESD classification at pins connected to
devices outside the ECU (IASG1 to
IASG5)
Human body model (HBM) HBM
AEC Q100-002
±3000 V
ESD classification at pins connected to
devices outside the ECU (K1 and K2)
Human body model (HBM) HBM
AEC Q100-002
±2500 V
General ESD classification for all other
pins
Human body model (HBM)
Charged device model (CDM) – no corner
pins
Charged device model (CDM) – corner
pins
HBM
AEC Q100-002
CDM
ESD STM5.3.1-1999
±1500
±500
±750
V
V
V
3. Absolute Maximum Ratings (Continued)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.
Parameters Remark Minimum Maximum Unit

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ATA6264 [Preliminary]
4. Functional Range
Within the functional range, the ATA6264 works as specified. All voltages are referenced to the
ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.
At the beginning of each specification table, supply voltage and temperature conditions are
described.
Table 4-1. Electrical Characteristics – Functional Range
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.1 Voltage on pins K30, K15,
USP –0.3 +40 V
1.1a Voltage on pins K1, K2 –25 +40 V
1.2 Rate of supply voltage rise
(K30, K15, K1, K2) 50 V/µs
1.3 Supply voltage EVZ –0.3 +40 V
1.4 Supply voltage VSAT –0.3 +14 V
1.5 Supply voltages VCORE,
VPERI –0.3 +5.5 V
1.6 Supply voltage CP, CP-OUT –0.3 +50 V
1.7 Voltage on digital I/O pins –0.3 +5.5 V
1.8 Voltage on pins SVSAT,
SVCORE –1.0 +40 V
1.9
Voltage on pins UZP,
ISENS, COMCOI,
COMCOO, COMSATO,
COMSATI, COMEVZO,
FBEVZ, IREF, VINT
–0.3 +5.5 V
1.10 Voltage on pins GEVZ,
OCEVZ –0.3 +10 V
1.11 Voltage on pin SVPERI –0.3 +6 V
1.12 Voltage on pins IASGx
(x = 1 to 5)
Voltage
necessary to
drive –40 mA
stored in 20 µH
40 V
1.14
Temperatures:
Operating ambient
temperature range
Operating junction
temperature range
Storage ambient/junction
temperature range
–40
– 40
– 55
+ 90
+150
+105
°C
°C
°C
1.15 Thermal resistance junction
ambient 60 K/W
1.16
Substrate current which can
be drawn without
disturbances to upper
defined blocks/functions(1)
–40 mA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. No substrate current occurs at pins K1, K2 down to VK1, VK2 > –25V

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ATA6264 [Preliminary]
4.1 Protection Against Substrate Currents
Due to the fact that the ATA6264 is connected to the wiring harness and to components outside
of the ECU, negative voltages at the following pins might occur:
• IASG interface: IASG1, IASG2, IASG3, IASG4, IASG5
• USP comparator: USP
If substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the
following blocks and functions will happen:
• No disturbance of RESET block.
• No voltage changes of any regulators outside of their tolerances.
• No impact on digital circuitry (for example, changes of latches, status register, etc.)
• No latch up of any circuitry

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ATA6264 [Preliminary]
5. Supply Currents
A minimum current has to flow into each pin for proper functioning of the IC.
Table 5-1. Electrical Characteristics – Supply currents
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
2.1 Supply current at K30 Standby mode: 0V = VK30 = 18V,
VK15 = 3V and KEYLATCH = OFF K30 IK30 050µAA
2.1a Supply current at K30 Standby mode: 18V < VK30 = 40V,
VK15 = 3V and KEYLATCH = OFF K30 IK30 05mAA
2.1b Supply current at K30
Startup mode: 0V < VK30 = 18V,
VK15 > 4.15V or KEYLATCH = ON,
VEVZ = 0V, CCP = 47 nF
K30 IK30 07mAA
2.1c Supply current at K30
Startup mode: 18V < VK30 = 40V
VK15 > 4.15V or KEYLATCH = ON
VEVZ = 0V, CCP = 47 nF
K30 IK30 010mAA
2.1d Supply current at K30
Normal mode: 0V < VK30 = 18V,
VEVZ > VK30, VK15 > 4V or
KEYLATCH = ON, SVCORE open,
AMUX Measurement K30 active
K30 IK30 06.5mAA
2.1e Supply current at K30
Normal mode: 18V < VK30 = 40V,
VEVZ > VK30, VK15 > 4.15V or
KEYLATCH = ON, SVCORE open,
AMUX Measurement K30 active
K30 IK30 010mAA
2.2 Supply current at EVZ
Startup mode: 0V < VEVZ = 40V,
VSAT = VPERI = VCORE = 0V,
VK30 >5V,V
K15 > 4.15V, SVCORE
and SVSAT open
EVZ IEVZ 05mAA
2.2a Supply current at EVZ
Normal mode: 0V < VEVZ = 40V,
VPERI and VCORE > Reset
Threshold, VEVZ > VK30,
VSAT = 10V, VK30 > 5V,
VK15 > 4.15V, SVCORE and
SVSAT open, AMUX Measurement
EVZ active
EVZ IEVZ 06mAA
2.2b Supply current at EVZ
Autonomous mode:
0V < VEVZ = 40V, VPERI and VCORE
> Reset Threshold, VEVZ > VK30,
VSAT = 10V, VK30 < 3.85V,
VK15 < 3V, SVCORE and SVSAT
open, AMUX Measurement EVZ
active
EVZ IEVZ 010mAA
2.3 Supply current at VSAT 0V < VSAT = 14V, SVPERI open,
AMUX measurement VSAT active VSAT IVSAT 01.5mAA
2.4 Supply current at
VPERI
0V < VPERI = 5.3V, AMUX
measurement VPERI active VPERI IVPERI –0.2 2.2 mA A
2.5 Supply current at
VCORE
0V < VCORE = 5.3V, AMUX
measurement VCORE active VCORE IVCORE –0.45 1 mA A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

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ATA6264 [Preliminary]
5.1 Discharger Circuit
Applications using the ATA6264 usually use a reverse polarity protection diode (D1 in Figure
5-1) in the power supply to prevent any damage if the wrong polarity is applied to VK30. Unfortu-
nately, this method includes some risk as can be seen in the following description:
During Standby mode (VK15 < 3V and KEYLATCH = OFF) the IC consumes only a low current,
IK30. Any peaks on the supply voltage (VPulse in Figure 5-1) will gradually charge the blocking
capacitor (C1). D1 prevents the capacitor from being discharged via the power supply and the
very small quiescent current via the IC can also be neglected. This means that during long peri-
ods of Standby mode, the IC’s supply voltage could increase continuously until finally the
maximum supply voltage limit would be exceeded and the IC could be damaged. ATA6264
therefore features a discharger circuit which avoids such unwanted effects. If VK30 exceeds a
threshold value of approximately 26.8V, the blocking capacitor is discharged via an integrated
resistor until VK30 again falls below the threshold.
Figure 5-1. Discharger Circuit
5.2 Initial Programming of the ATA6264
The ATA6264 supports different output voltages at the VSAT, VPERI and the VCORE regula-
tors. In addition, different modes at the ISO9141 interfaces can be adjusted at the initial
programming (IP). The memory cells are one-time programmable (OTP) and cannot be changed
after the IP (default values are “0”). In general, the IP is done after mounting the ATA6264 on the
PCB with an in-circuit tester. The programming voltage of 11.7V has to be applied on pin VSAT.
It is also possible to use the VSAT regulator as the programming voltage because VSAT is pro-
grammed to 11.7V (±0.5V) as long as the Test mode is entered and the lock bit is not set. To
ensure proper programming of the ATA6264, at least a 10-µF electrolytic cap and a 100-nF
ceramic cap have to be applied at pin VSAT.
VPuls
e
VBatt
26.8V
K30 D1
C18 kΩ

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ATA6264 [Preliminary]
The following settings can be made at the initial programming:
MSBit LSBit
VR1 VR2 VR3 VR4 EXT ISO/LIN Parity Lock bit
Table 5-2. Initial Programming Settings
VR1 VR2 VR3 VR4 VCORE VPERI VSAT
0 0 0 0 All regulators deactivated (default)
0 0 0 1 1.88V 3.3V 7.8V
0 0 1 0 1.88V 3.3V 9.1V
0 0 1 1 1.88V 3.3V 10.4V
0 1 0 0 2.5V 3.3V 7.8V
0 1 0 1 2.5V 3.3V 9.1V
0 1 1 0 2.5V 3.3V 10.4V
0 1 1 1 1.88V 5V 7.8V
1 0 0 0 1.88V 5V 9.1V
1 0 0 1 1.88V 5V 10.4V
1 0 1 0 2.5V 5V 7.8V
1 0 1 1 2.5V 5V 9.1V
1 1 0 0 2.5V 5V 10.4V
1 1 0 1 5V 5V 7.8V
1 1 1 0 5V 5V 9.1V
1 1 1 1 5V 5V 10.4V
Set to 0 Set to 1
EXT No external transistor at VPERI (default) External transistor at VPERI applied
Set to 0 Set to 1
ISO/LIN ISO9141 mode is activated at K1 (default) LIN mode is activated at K1

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ATA6264 [Preliminary]
The IP data is valid only if the parity is odd. If the IP data is not valid, or if the lock bit is not set,
the programming will not be executed.
Figure 5-2. Programming Sequence
Remove all voltages and pinloads
to get out of Test mode
Transmit IP command A9xx(h)
via SPI to configure ATA6264
Wait 1 ms
Wait until VSAT = 11.7V
Transmit 5A5A(h) via SPI
to Enable Testmode
Set RESQ and TxD1 to GND
and RESQ2 and TxD2 to 5V
Apply 12V at K15, K30 and5V
at VPERI
Contact pins RESQ, RESQ2
TxD1, TxD2, SSQ, MOSI,
SCLK, VPERI, K15, K30

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ATA6264 [Preliminary]
5.3 Start-up and Power-down Procedure
The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is con-
nected to the ignition key line K15. In order to detect an interruption on one of these pins
correctly, resistors are implemented at these pins. Normally, the main supply pin of ATA6264 is
pin K30. In the case of a missing or a too-low voltage at pin K30, the whole IC is supplied from
the backup power supply capacitor hooked up to pin EVZ.
Figure 5-3. Block Diagram Start-up and Power-down Procedure
VCP
VCP
K30
EVZ
VEVZ
VVSAT
VVPERI
Comp
VEVZ
K15GOOD
VK15 = 3V to 4.15V
(40 mV to 175mV Hysteresis)
Serial interface
(KEY - LATCH)
VSAT
VCP
Comp
CORE_EN
VPERI = 1.25V to 1.7V
(50 mV to 150 mV Hysteresis)
Comp
VSATGOOD
VSAT = 6.77V to 7.2V
(200 mV to 500 mV Hysteresis)
Comp
VEVZ
VCP
K15
K30
CP
GEVZEVZEN
CORESWAP
5V
IREF lost
signal
VK30 = 3.85V to 5V
(50 mV to 150 mV Hysteresis)
Power
sequencing
VSAT
driver SVSAT
EVZ
VVCOR
E
VCORE
SVCORE
VK30
IP
VEVZ
driver
Comp
K30GOOD
VCORE
driver
VCore
driver
VPERI
driver
VPERI
SVPER
IP
VK30 = 6.1V to 8.1V (ON)
(0.5V to 1V Hysteresis)
Comp
EVZGOOD
VEVZ = 7.5V to 9V (ON)
VEVZ = 5.5V to 6.2V (OFF)

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ATA6264 [Preliminary]
Depending on the initial programming of the ATA6264, the start-up procedure takes place in dif-
ferent phases.
5.3.1 Start-up Procedure if VVCORE is Programmed to Be 5V or 2.5V
Phase1: After switching on the ignition key, K15 voltage will apply at pin K15. If, in addition, the
voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal
K15GOOD can be replaced by the serial interface command KEYLATCH which can be set via
the serial interface.
Phase2: If VEVZ is larger than 7.5V to 9V the VSAT regulator starts operating and the VCORE
regulator will be enabled.
Phase3: After VVSAT has reached 6.77V to 7.2V, the VPERI regulator starts working. The
VCORE regulator starts operating depending on the charge pump voltage.
5.3.2 The Power-down Procedure Takes Place in Different Phases
Phase1: If the ignition key is switched off, K15 voltage will vanish at pin K15. If the serial inter-
face command KEYLATCH is not set, the EVZ regulator stops working. The external charge
pump is still working because EVZ is above VSAT and the VSAT regulator is not in Perma-
nent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE
regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ.
Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops to
low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on mode,
the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage. If
the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off. Depending
on the charge-pump voltage, the VCORE regulator stops working.
Phase3: When the voltage at the EVZ capacitor gets to be lower than 5.5V to 6.2V, VSAT is
switched off.

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ATA6264 [Preliminary]
Figure 5-4. Start-Up and Power-Down Procedure if VVCORE Programmed to Be 5V or 2.5V
5.3.3 Start-up Procedure if VVCORE Programmed to Be 1.88V
Phase1: After switching on the ignition key, the K15 voltage will appear at pin K15. If, in addi-
tion, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The
signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be
set by the serial interface.
Phase2: If VEVZ is larger than 7.5V to 9V, the VSAT regulator starts operating.
Phase3: After VVSAT has reached 6.77V to 7.2V, the VPERI regulator starts working.
Phase4: If VVPERI is higher than 1.25V to 1.7V, the VCORE regulator will be enabled.
t
VK30
3V to 4.15V3V to 4.15V
5.5V to 6.2V
too low EVZ voltage
VSAT goes into On Mode
charge pump deactivated
6.77V to 7.2V 7V to 6.27V
7.5V to 9V
VGEVZ
VEVZ
VVSAT
VK15
VVCORE
VVPERI
t
t
t
t
t
t
Threshold to enable
VCORE regulator
Threshold to start
VCORE regulator

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ATA6264 [Preliminary]
5.3.4 The Power-down Procedure for VVCORE is Programmed to be 1.88V
Phase1: If the ignition key is switched off, the K15 voltage will vanish at pin K15. If the serial
interface command KEYLATCH is not set, the EVZ regulator stops working. The external charge
pump is still working because EVZ is above VSAT and the VSAT regulator is not in the Perma-
nent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE
regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ.
Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops
too low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on
mode, the external charge pump stops working and the VSAT voltage falls analog to the EVZ
voltage. If the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off.
Depending on the charge-pump voltage, the VCORE regulator stops working. The power
sequencing function for the VPERI regulator is still active and guarantees a maximum voltage
difference between VPERI and VCORE of 2.8V
Phase3: After VVPERI becomes lower than 1.1V to 1.55V, the VCORE regulator has to stop
working.
Phase4: When the voltage at the EVZ capacitor is lower than 5.5V to 6.2V, VSAT is switched
off.
Figure 5-5. Start-up and Power-down Procedure if VVCORE Programmed to Be 1.88V
3V to 4.15V3V to 4.15V
5.5V to 6.2V
too low EVZ voltage
VSAT goes into On Mode
charge pump deactivated
7.5V to 9V
7V to 6.27V6.77V to 7.2V
1.1V to 1.55V1.25V to 1.7V
VGEVZ
VEVZ
VVSAT
VK15
VK30
VVCORE
VVPERI
t
t
t
t
t
t
t

18
4929B–AUTO–01/07
ATA6264 [Preliminary]
6. Power Supply Sequencing
(Only active when initial programming sets VVCORE = 1.88V and VVPERI = 3.3V)
In order to meet the requirements of several dual-voltage-supply microcontrollers, a
power-sequencing function is implemented. The ATA6264 ensures that the voltage difference
VPERI – VCORE will not exceed 2.8V.
The voltage difference between VPERI and VCORE is monitored. In error cases, for example, if
the VCORE regulator does not start to work, the difference may rise above the 2.8V threshold. In
this case, the VPERI regulator is switched off before reaching this level and switched on again if
the voltage difference drops below a hysteresis value.
Figure 6-1. Example for Incorrect Ramp Up
Necessary for operation:
VEVZ = 0V to 40V, VINT = 3.7V to 5.47V
Operating conditions of all other supply pins:
VK30, VVSAT, VVPERI and VVCORE are within functional range limits, Tj= –40°C to 150°C
Other pins:
As defined in Section 4. ”Functional Range” on page 8.
1.88V
Not allowed area:
V
VPERI
- V
VCORE >
2.8V
3.3V
V
VPERI
V
VCORE
t
t
Table 6-1. Electrical Characteristics – Power Supply Sequencing
No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*
5.1 Maximum voltage difference
VVPERI – VVCORE
VPERI,
VCORE
VVPERI
– VVCORE 02.8VA
5.2a Voltage level VVPERI – VVCORE to
switch off VPERI regulator
VPERI,
VCORE
VVPERI
– VVCORE 2.3 2.8 V A
5.2b Hysteresis for VVPERI – VVCORE to
enable VPERI regulator VHYS 100 mV A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

19
4929B–AUTO–01/07
ATA6264 [Preliminary]
Figure 6-2. Block Diagram Power Supply Sequencing
VEVZ
VVSAT
VVPERI
Comp
VEVZ
K15GOOD
VK15 = 3V to 4.15V
(40 mV to 175mV Hysteresis)
Serial interface
(KEY - LATCH)
VSAT
VCP
Comp
VSATGOOD
VSAT = 6.77V to 7.2V
VCORE - Regulator
(200 mV to 500 mV Hysteresis)
Comp
VEVZ
VCP
K15
K30
CP
GEVZEVZEN
CORESWAP
5V
IREF lost
signal
VK30 = 3.85V to 5V
(50 mV to 150 mV Hysteresis)
VSAT
driver SVSAT
EVZ
VVCOR
E
VCORE
SVCORE
VK30
IP
VEVZ
driver
Comp
K30GOOD
VPERI
driver
Delta
< 2.8V
VPERI
SVPER
IP
VK30 = 6.1V to 8.1V (ON)
(0.5V to 1V Hysteresis)
Comp
EVZGOOD
VEVZ = 7.5V to 9V (ON)
VEVZ = 5.5V to 6.2V (OFF)

20
4929B–AUTO–01/07
ATA6264 [Preliminary]
7. Charge Pump
To supply the VSAT and VCORE drivers, an external charge pump is provided. Both FETs(1) are
driven by the high charge pump voltage VCP to ensure that they can be switched to a low-ohmic
state. For correct function of the charge pump, an external capacitor of C = 47 nF has to be con-
nected to pin SVSAT, and another of C = 100 nF to pin CP. A double diode has to be
implemented for proper function of the charge pump. An external series resistor is recom-
mended to suppress spikes during switching of the SVSAT. The CP block is supplied by EVZ
and VSAT voltage and starts to operate as soon as the thresholds for VK15, K30 and EVZ are
achieved. An additional start-up circuitry is implemented to support the VSAT driver during the
start-up phase, thus enabling a reliable system startup.
The charge pump has an output CP-OUT to supply the external circuitry, and can be switched
via the SPI. It is capable of 250 µA.
Figure 7-1. Block Diagram Charge Pump
Note: 1. Connected to the drivers (see Figure 5-3)
SVSATVSAT
REFREF
CP
I = 1.4 mA
Status
register
External circuit
Status
register
Serial
interface
EVZ
CP-Out