Atmel SAM9X25 User manual

Features
•Core
– ARM926EJ-S™ ARM®Thumb®Processor running at up to 400 MHz @ 1.0V +/- 10%
– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
•Memories
– One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash,
SDCard, DataFlash®or serial DataFlash. Programmable order.
– One 32-Kbyte internal SRAM, single-cycle access at system speed
– High Bandwidth Multi-port DDR2 Controller
– 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static
Memories
– MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error
Correcting Code (PMECC)
•System running at up to 133 MHz
– Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval
Timer, Watchdog Timer and Real Time Clock
– Boot Mode Select Option, Remap Command
– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
– Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
– One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
– Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
– Dual Peripheral Bridge with dedicated programmable clock for best performance
– Two dual port 8-channel DMA Controllers
– Advanced Interrupt Controller and Debug Unit
– Two Programmable External Clock Signals
•Low Power Mode
– Shut Down Controller with four 32-bit Battery Backup Registers
– Clock Generator and Power Management Controller
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
•Peripherals
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with
dedicated On-Chip Transceiver
– Two 10/100 Mbps Ethernet MAC Controllers
– Two High Speed Memory Card Hosts
– Two CAN Controllers
– Two Master/Slave Serial Peripheral Interface
– Two Three-channel 32-bit Timer/Counters
– One Synchronous Serial Controller
– One Four-channel 16-bit PWM Controller
– Three Two-wire Interfaces
– Four USARTs, two UARTs
– One 12-channel 10-bit Analog-to-Digital Converter
– Soft Modem
•I/O
– Four 32-bit Parallel Input/Output Controllers
– 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
– Individually Programmable Open-drain, Pull-up and pull-down resistor,
Synchronous Output
•Package
– 217-ball BGA, pitch 0.8 mm
AT91SAM
ARM-based
Embedded MPU
SAM9X25
11054A–ATARM–27-Jul-11

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11054A–ATARM–27-Jul-11
SAM9X25
1. Description
The SAM9X25 is a high-performance ARM926-based embedded microprocessor unit, running
at 400 MHz and featuring multiple networking/connectivity peripherals, optimized for industrial
applications such as building automation, gateways and medical.
The SAM9X25 features two 2.0A/B compatible Controller Area Network (CAN) interfaces and
two IEEE Std 802.3-compatible 10/100Mbps Ethernet MACs. Additional communication inter-
faces include a soft modem supporting exclusively the Conexant SmartDAA line driver, HS USB
Device and Host, FS USB Host, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S,
TWIs and 10-bit ADC.
To ensure uninterrupted data transfer with minimum processor overhead, the SAM9X25 offers a
10-layer bus matrix coupled with 2 x 8 central DMA channels and dedicated DMAs for the high-
speed connectivity peripherals.
The External Bus Interface incorporates controllers for 8-bank DDR2/LPDDR, SDRAM/LPS-
DRAM, static memories, and specific circuitry for MLC/SLC NAND Flash with integrated ECC.
The SAM9X25 is available in a 217-ball BGA package with 0.8mm ball pitch.

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11054A–ATARM–27-Jul-11
SAM9X25
2. Block Diagram
Figure 2-1. SAM9X25 Block Diagram
AIC
APB
PLLA
System Controller
PMC
PLLUTMI
PIT
WDT
OSC 32K
SHDC
RSTC
POR
DBGU
4
GPBR
USART0 USART1 USART2 USART3
SPI0
OSC12M
PIOB
POR
PIOC
RTC
RC
PIOD
HS
Transc.
DMA
HS
Transceiver
DMA
SSC
PIO
PIO
HS EHCI /
FS OHCI
USB HOST
ARM926EJ-S
JTAG / Boundary Scan
In-Circuit Emulator
MMU
Bus Interface
ID
ICache
16 KB
DCache
16 KB
PIOA
NPCS2
NPCS1
SPCK
MOSI
MISO
NPCS0
NPCS3
RTS0-3
SCK0-3
TXD0-3
RDX0-3
CTS0-3
DFSDP/HFSDPA,
DFSDM/HFSDMA
DHSDP/HHSDPA,
DHSDM/HHSDMA
HFSDPB,HFSDMB
HHSDPB,HHSDMB
TDI
TDO
TMS
TCK
JTAGSEL
RTCK
BMS
VBG
FIQ
IRQ
DRXD
DTXD
PCK0-PCK1
VDDBU
SHDN
WKUP
XIN
NRST
XOUT
XIN32
XOUT32
VDDCORE
TST
NTRST
PB PA
TC0 TC1 TC2 TC3 TC4 TC5
12M
RC
SPI1
NPCS2
NPCS1
SPCK
MOSI
MISO
NPCS0
NPCS3
HSMCI0
SD/SDIO
FIFO
MCI0_CK
MCI0_DA0-MCI0_DA3
MCI0_CDA
EMAC0
DMA
12-Channel
10-bit ADC
ADVREF
VDDANA
AD5-AD11
AD0
AD1
AD2
AD3
PIO
PWM
AD4
Peripheral
Bridge
SRAM
32KB
Peripheral
Bridge
TK
TF
TD
RD
RF
RK
PC
FS
Transc.
HFSDPC
HFSDMC
8-CH DMA
8-CH DMA
PWM0-PWM3
GNDANA
UTXD0-UTXD1
URDX0-URDX1
UART0 UART1
EBI
Static
Memory
Controller
D0-D15
A0/NBS0
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
SDCK, #SDCK, SDCKE
RAS, CAS
SDWE, SDA10
A1/NBS2/NWR2/DQM2
NANDOE, NANDWE
NWAIT NCS2, NCS3, NCS4, NCS5
NANDCS
DQM[0..1] DQS[0..1]
NANDALE, NANDCLE
PIO
D16-D31
NWR3/NBS3/DQM3
A20-A25
TWI0 TWI1 TWI2
TWCK0-TWCK2
TWD0-TWD2
Multi-Layer AHB Matrix
DDR2SDR
Controller
SMD
DIBN
DIBP
A2-A15, A19
A16/BA0
A18/BA2
A17/BA1
NAND Flash
Controller
PMECC
PMERRLOC
HSMCI1
SD/SDIO
FIFO
MCI1_CK
MCI1_CDA
MCI1_DA0-MCI1_DA3
TCLK0-TCLK5
TIOA0-TIOA5
TIOB0-TIOB5
ADTRG
HS
USB
EMAC1 (RMII)
DMA
ETXCK-ERXCK
ETXEN-ETXER
ECRS-ECOL
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
EMDC
EMDIO
REFCK
ETXEN
ERXER-CRSDV
ERX0-ERX1
ETX0-ETX1
EMDC
EMDIO
CAN0 CAN1
CANTX0-CANTX1
CANRX0-CANRX1
ROM
32 KB + 96 KB

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SAM9X25
3. Signal Description
Table 3-1 gives details on the signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type Active Level
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
VBG Bias Voltage Reference for USB Analog
PCK0-PCK1 Programmable Clock Output Output
Shutdown, Wakeup Logic
SHDN Shut-Down Control Output
WKUP Wake-Up Input Input
ICE and JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
JTAGSEL JTAG Selection Input
RTCK Return Test Clock Output
Reset/Test
NRST Microcontroller Reset I/O Low
TST Test Mode Select Input
NTRST Test Reset Signal Input
BMS Boot Mode Select Input
Debug Unit - DBGU
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
Advanced Interrupt Controller - AIC
IRQ External Interrupt Input Input
FIQ Fast Interrupt Input Input
PIO Controller - PIOA - PIOB - PIOC - PIOD
PA0-PA31 Parallel IO Controller A I/O
PB0-PB18 Parallel IO Controller B I/O
PC0-PC31 Parallel IO Controller C I/O
PD0-PD21 Parallel IO Controller D I/O

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SAM9X25
External Bus Interface - EBI
D0-D15 Data Bus I/O
D16-D31 Data Bus I/O
A0-A25 Address Bus Output
NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0-NCS5 Chip Select Lines Output Low
NWR0-NWR3 Write Signal Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0-NBS3 Byte Mask Signal Output Low
NAND Flash Support
NFD0-NFD16 NAND Flash I/O I/O
NANDCS NAND Flash Chip Select Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
DDR2/SDRAM/LPDDR Controller
SDCK,#SDCK DDR2/SDRAM Differential Clock Output
SDCKE DDR2/SDRAM Clock Enable Output High
SDCS DDR2/SDRAM Controller Chip Select Output Low
BA[0..2] Bank Select Output Low
SDWE DDR2/SDRAM Write Enable Output Low
RAS-CAS Row and Column Signal Output Low
SDA10 SDRAM Address 10 Line Output
DQS[0..1] Data Strobe I/O
DQM[0..3] Write Data Mask Output
High Speed MultiMedia Card Interface - HSMCI0-1
MCI0_CK, MCI1_CK Multimedia Card Clock I/O
MCI0_CDA, MCI1_CDA Multimedia Card Slot Command I/O
MCI0_DA0-MCI0_DA3 Multimedia Card 0 Slot A Data I/O
MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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SAM9X25
Universal Synchronous Asynchronous Receiver Transmitter - USARTx
SCKx USARTx Serial Clock I/O
TXDx USARTx Transmit Data Output
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
Universal Asynchronous Receiver Transmitter - UARTx
UTXDx UARTx Transmit Data Output
URXDx UARTx Receive Data Input
Synchronous Serial Controller - SSC
TD SSC Transmit Data Output
RD SSC Receive Data Input
TK SSC Transmit Clock I/O
RK SSC Receive Clock I/O
TF SSC Transmit Frame Sync I/O
RF SSC Receive Frame Sync I/O
Timer/Counter - TCx x=0..5
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Serial Peripheral Interface - SPIx
SPIx_MISO Master In Slave Out I/O
SPIx_MOSI Master Out Slave In I/O
SPIx_SPCK SPI Serial Clock I/O
SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select Output Low
Two-Wire Interface -TWIx
TWDx Two-wire Serial Data I/O
TWCKx Two-wire Serial Clock I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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11054A–ATARM–27-Jul-11
SAM9X25
Pulse Width Modulation Controller- PWMC
PWM0-PWM3 Pulse Width Modulation Output Output
USB Host High Speed Port - UHPHS
HFSDPA USB Host Port A Full Speed Data + Analog
HFSDMA USB Host Port A Full Speed Data - Analog
HHSDPA USB Host Port A High Speed Data + Analog
HHSDMA USB Host Port A High Speed Data - Analog
HFSDPB USB Host Port B Full Speed Data + Analog
HFSDMB USB Host Port B Full Speed Data - Analog
HHSDPB USB Host Port B High Speed Data + Analog
HHSDMB USB Host Port B High Speed Data - Analog
HFSDMC USB Host Port C Full Speed Data - Analog
HFSDPC USB Host Port C Full Speed Data + Analog
USB Device High Speed Port - UDPHS
DFSDM USB Device Full Speed Data - Analog
DFSDP USB Device Full Speed Data + Analog
DHSDM USB Device High Speed Data - Analog
DHSDP USB Device High Speed Data + Analog
Ethernet 10/100 - EMAC0
ETXCK Transmit Clock or Reference Clock Input
ERXCK Receive Clock Input
ETXEN Transmit Enable Output
ETX0-ETX3 Transmit Data Output
ETXER Transmit Coding Error Output
ERXDV Receive Data Valid Input
ERX0-ERX3 Receive Data Input
ERXER Receive Error Input
ECRS Carrier Sense and Data Valid Input
ECOL Collision Detect Input
EMDC Management Data Clock Output
EMDIO Management Data Input/Output I/O
RMII Ethernet 10/100 - EMAC1
REFCK Transmit Clock or Reference Clock Input
ETXEN Transmit Enable Output
ETX0-ETX1 Transmit Data Output
CRSDV Receive Data Valid Input
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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11054A–ATARM–27-Jul-11
SAM9X25
ERX0-ERX1 Receive Data Input
ERXER Receive Error Input
EMDC Management Data Clock Output
EMDIO Management Data Input/Output I/O
Analog-to-Digital Converter - ADC
AD0-AD11 12 Analog Inputs Analog
ADTRG ADC Trigger Input
ADVREF ADC Reference Analog
CAN Controller - CANx
CANRXx CAN input Input
CANTXx CAN output Output
Soft Modem - SMD
DIBN Soft Modem Signal I/O
DIBP Soft Modem Signal I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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11054A–ATARM–27-Jul-11
SAM9X25
4. Package and Pinout
The SAM9X25 is available in 217-ball BGA package.
4.1 Overview of the 217-ball BGA Package
Figure 4-1 shows the orientation of the 217-ball BGA Package.
Figure 4-1. Orientation of the 217-ball BGA Package
4.2 I/O Description
TOP VIEW
BALL A1
12
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
ABCDEF GHJ KL M NPRT U
Table 4-1. SAM9X25 I/O Type Description
I/O Type Voltage Range Analog Pull-up Pull-down Schmitt Trigger
GPIO 1.65-3.6V switchable switchable switchable
GPIO_CLK 1.65-3.6V switchable switchable switchable
GPIO_CLK2 1.65-3.6V switchable switchable switchable
GPIO_ANA 3.0-3.6V Iswitchable switchable
EBI 1.65-1.95V, 3.0-
3.6V switchable switchable
EBI_O 1.65-1.95V, 3.0-
3.6V Reset State Reset State
EBI_CLK 1.65-1.95V, 3.0-
3.6V
RSTJTAG 3.0-3.6V Reset State Reset State Reset State
SYSC 1.65-3.6V Reset State Reset State Reset State
VBG 0.9-1.1V I
USBFS 3.0-3.6V I/O
USBHS 3.0-3.6V I/O
CLOCK 1.65-3.6V I/O
DIB 3.0-3.6V I/O

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11054A–ATARM–27-Jul-11
SAM9X25
When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the
Pin Description table.
4.2.1 Reset State
In the tables that follow, the column “Reset State” indicates the reset state of the line with
mnemonics.
• “PIO” “/” signal
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned,
the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit
corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released.
• “I”/”O”
Indicates whether the signal is input or output state.
• “PU”/”PD”
Indicates whether Pull-Up, Pull-Down or nothing is enabled.
•“ST”
Table 4-2. SAM9X25 I/O Type Assignment and Frequency
I/O Type
I/O Frequency
(MHz)
Charge Load
(pF)
Output
Current Signal Name
GPIO 40 10 all PIO lines except the following
GPIO_CLK 54 10 MCI0CK, MCI1CK, SPI0SPCK, SPI1SPCK,
EMACx_ETXCK, ISI_MCK
GPIO_CLK2 75 10
GPIO_ANA 25 10 16mA,
40mA (peak) ADx, GPADx
EBI 133 50 (3.3V)
30 (1.8V) all Data lines (Input/output) except the following
EBI_O 66 50 (3.3V)
30 (1.8V)
all Address and control lines (output only) except the
following
EBI_CLK 133 10 CK, #CK
RSTJTAG 10 10 NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK
SYSC 0.25 10 WKUP, SHDN, JTAGSEL, TST, SHDN
VBG 0.25 10 VBG
USBFS 12 10 HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
HFSDMB/DFSDM, HFSDMC
USBHS 480 10 HHSDPA, HHSDPB/DHSDP, HHSDMA,
HHSDMB/DHSDM
CLOCK 50 50 XIN, XOUT, XIN32, XOUT32
DIB 25 25 DIBN, DIBP