Atmel SAM9X25 User manual

Features
•Core
– ARM926EJ-S™ ARM®Thumb®Processor running at up to 400 MHz @ 1.0V +/- 10%
– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
•Memories
– One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash,
SDCard, DataFlash®or serial DataFlash. Programmable order.
– One 32-Kbyte internal SRAM, single-cycle access at system speed
– High Bandwidth Multi-port DDR2 Controller
– 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static
Memories
– MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error
Correcting Code (PMECC)
•System running at up to 133 MHz
– Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval
Timer, Watchdog Timer and Real Time Clock
– Boot Mode Select Option, Remap Command
– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
– Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
– One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
– Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
– Dual Peripheral Bridge with dedicated programmable clock for best performance
– Two dual port 8-channel DMA Controllers
– Advanced Interrupt Controller and Debug Unit
– Two Programmable External Clock Signals
•Low Power Mode
– Shut Down Controller with four 32-bit Battery Backup Registers
– Clock Generator and Power Management Controller
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
•Peripherals
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with
dedicated On-Chip Transceiver
– Two 10/100 Mbps Ethernet MAC Controllers
– Two High Speed Memory Card Hosts
– Two CAN Controllers
– Two Master/Slave Serial Peripheral Interface
– Two Three-channel 32-bit Timer/Counters
– One Synchronous Serial Controller
– One Four-channel 16-bit PWM Controller
– Three Two-wire Interfaces
– Four USARTs, two UARTs
– One 12-channel 10-bit Analog-to-Digital Converter
– Soft Modem
•I/O
– Four 32-bit Parallel Input/Output Controllers
– 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
– Individually Programmable Open-drain, Pull-up and pull-down resistor,
Synchronous Output
•Package
– 217-ball BGA, pitch 0.8 mm
AT91SAM
ARM-based
Embedded MPU
SAM9X25
11054A–ATARM–27-Jul-11

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11054A–ATARM–27-Jul-11
SAM9X25
1. Description
The SAM9X25 is a high-performance ARM926-based embedded microprocessor unit, running
at 400 MHz and featuring multiple networking/connectivity peripherals, optimized for industrial
applications such as building automation, gateways and medical.
The SAM9X25 features two 2.0A/B compatible Controller Area Network (CAN) interfaces and
two IEEE Std 802.3-compatible 10/100Mbps Ethernet MACs. Additional communication inter-
faces include a soft modem supporting exclusively the Conexant SmartDAA line driver, HS USB
Device and Host, FS USB Host, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S,
TWIs and 10-bit ADC.
To ensure uninterrupted data transfer with minimum processor overhead, the SAM9X25 offers a
10-layer bus matrix coupled with 2 x 8 central DMA channels and dedicated DMAs for the high-
speed connectivity peripherals.
The External Bus Interface incorporates controllers for 8-bank DDR2/LPDDR, SDRAM/LPS-
DRAM, static memories, and specific circuitry for MLC/SLC NAND Flash with integrated ECC.
The SAM9X25 is available in a 217-ball BGA package with 0.8mm ball pitch.

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11054A–ATARM–27-Jul-11
SAM9X25
2. Block Diagram
Figure 2-1. SAM9X25 Block Diagram
AIC
APB
PLLA
System Controller
PMC
PLLUTMI
PIT
WDT
OSC 32K
SHDC
RSTC
POR
DBGU
4
GPBR
USART0 USART1 USART2 USART3
SPI0
OSC12M
PIOB
POR
PIOC
RTC
RC
PIOD
HS
Transc.
DMA
HS
Transceiver
DMA
SSC
PIO
PIO
HS EHCI /
FS OHCI
USB HOST
ARM926EJ-S
JTAG / Boundary Scan
In-Circuit Emulator
MMU
Bus Interface
ID
ICache
16 KB
DCache
16 KB
PIOA
NPCS2
NPCS1
SPCK
MOSI
MISO
NPCS0
NPCS3
RTS0-3
SCK0-3
TXD0-3
RDX0-3
CTS0-3
DFSDP/HFSDPA,
DFSDM/HFSDMA
DHSDP/HHSDPA,
DHSDM/HHSDMA
HFSDPB,HFSDMB
HHSDPB,HHSDMB
TDI
TDO
TMS
TCK
JTAGSEL
RTCK
BMS
VBG
FIQ
IRQ
DRXD
DTXD
PCK0-PCK1
VDDBU
SHDN
WKUP
XIN
NRST
XOUT
XIN32
XOUT32
VDDCORE
TST
NTRST
PB PA
TC0 TC1 TC2 TC3 TC4 TC5
12M
RC
SPI1
NPCS2
NPCS1
SPCK
MOSI
MISO
NPCS0
NPCS3
HSMCI0
SD/SDIO
FIFO
MCI0_CK
MCI0_DA0-MCI0_DA3
MCI0_CDA
EMAC0
DMA
12-Channel
10-bit ADC
ADVREF
VDDANA
AD5-AD11
AD0
AD1
AD2
AD3
PIO
PWM
AD4
Peripheral
Bridge
SRAM
32KB
Peripheral
Bridge
TK
TF
TD
RD
RF
RK
PC
FS
Transc.
HFSDPC
HFSDMC
8-CH DMA
8-CH DMA
PWM0-PWM3
GNDANA
UTXD0-UTXD1
URDX0-URDX1
UART0 UART1
EBI
Static
Memory
Controller
D0-D15
A0/NBS0
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
SDCK, #SDCK, SDCKE
RAS, CAS
SDWE, SDA10
A1/NBS2/NWR2/DQM2
NANDOE, NANDWE
NWAIT NCS2, NCS3, NCS4, NCS5
NANDCS
DQM[0..1] DQS[0..1]
NANDALE, NANDCLE
PIO
D16-D31
NWR3/NBS3/DQM3
A20-A25
TWI0 TWI1 TWI2
TWCK0-TWCK2
TWD0-TWD2
Multi-Layer AHB Matrix
DDR2SDR
Controller
SMD
DIBN
DIBP
A2-A15, A19
A16/BA0
A18/BA2
A17/BA1
NAND Flash
Controller
PMECC
PMERRLOC
HSMCI1
SD/SDIO
FIFO
MCI1_CK
MCI1_CDA
MCI1_DA0-MCI1_DA3
TCLK0-TCLK5
TIOA0-TIOA5
TIOB0-TIOB5
ADTRG
HS
USB
EMAC1 (RMII)
DMA
ETXCK-ERXCK
ETXEN-ETXER
ECRS-ECOL
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
EMDC
EMDIO
REFCK
ETXEN
ERXER-CRSDV
ERX0-ERX1
ETX0-ETX1
EMDC
EMDIO
CAN0 CAN1
CANTX0-CANTX1
CANRX0-CANRX1
ROM
32 KB + 96 KB

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SAM9X25
3. Signal Description
Table 3-1 gives details on the signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type Active Level
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
VBG Bias Voltage Reference for USB Analog
PCK0-PCK1 Programmable Clock Output Output
Shutdown, Wakeup Logic
SHDN Shut-Down Control Output
WKUP Wake-Up Input Input
ICE and JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
JTAGSEL JTAG Selection Input
RTCK Return Test Clock Output
Reset/Test
NRST Microcontroller Reset I/O Low
TST Test Mode Select Input
NTRST Test Reset Signal Input
BMS Boot Mode Select Input
Debug Unit - DBGU
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
Advanced Interrupt Controller - AIC
IRQ External Interrupt Input Input
FIQ Fast Interrupt Input Input
PIO Controller - PIOA - PIOB - PIOC - PIOD
PA0-PA31 Parallel IO Controller A I/O
PB0-PB18 Parallel IO Controller B I/O
PC0-PC31 Parallel IO Controller C I/O
PD0-PD21 Parallel IO Controller D I/O

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SAM9X25
External Bus Interface - EBI
D0-D15 Data Bus I/O
D16-D31 Data Bus I/O
A0-A25 Address Bus Output
NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0-NCS5 Chip Select Lines Output Low
NWR0-NWR3 Write Signal Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0-NBS3 Byte Mask Signal Output Low
NAND Flash Support
NFD0-NFD16 NAND Flash I/O I/O
NANDCS NAND Flash Chip Select Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
DDR2/SDRAM/LPDDR Controller
SDCK,#SDCK DDR2/SDRAM Differential Clock Output
SDCKE DDR2/SDRAM Clock Enable Output High
SDCS DDR2/SDRAM Controller Chip Select Output Low
BA[0..2] Bank Select Output Low
SDWE DDR2/SDRAM Write Enable Output Low
RAS-CAS Row and Column Signal Output Low
SDA10 SDRAM Address 10 Line Output
DQS[0..1] Data Strobe I/O
DQM[0..3] Write Data Mask Output
High Speed MultiMedia Card Interface - HSMCI0-1
MCI0_CK, MCI1_CK Multimedia Card Clock I/O
MCI0_CDA, MCI1_CDA Multimedia Card Slot Command I/O
MCI0_DA0-MCI0_DA3 Multimedia Card 0 Slot A Data I/O
MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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SAM9X25
Universal Synchronous Asynchronous Receiver Transmitter - USARTx
SCKx USARTx Serial Clock I/O
TXDx USARTx Transmit Data Output
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
Universal Asynchronous Receiver Transmitter - UARTx
UTXDx UARTx Transmit Data Output
URXDx UARTx Receive Data Input
Synchronous Serial Controller - SSC
TD SSC Transmit Data Output
RD SSC Receive Data Input
TK SSC Transmit Clock I/O
RK SSC Receive Clock I/O
TF SSC Transmit Frame Sync I/O
RF SSC Receive Frame Sync I/O
Timer/Counter - TCx x=0..5
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Serial Peripheral Interface - SPIx
SPIx_MISO Master In Slave Out I/O
SPIx_MOSI Master Out Slave In I/O
SPIx_SPCK SPI Serial Clock I/O
SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select Output Low
Two-Wire Interface -TWIx
TWDx Two-wire Serial Data I/O
TWCKx Two-wire Serial Clock I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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SAM9X25
Pulse Width Modulation Controller- PWMC
PWM0-PWM3 Pulse Width Modulation Output Output
USB Host High Speed Port - UHPHS
HFSDPA USB Host Port A Full Speed Data + Analog
HFSDMA USB Host Port A Full Speed Data - Analog
HHSDPA USB Host Port A High Speed Data + Analog
HHSDMA USB Host Port A High Speed Data - Analog
HFSDPB USB Host Port B Full Speed Data + Analog
HFSDMB USB Host Port B Full Speed Data - Analog
HHSDPB USB Host Port B High Speed Data + Analog
HHSDMB USB Host Port B High Speed Data - Analog
HFSDMC USB Host Port C Full Speed Data - Analog
HFSDPC USB Host Port C Full Speed Data + Analog
USB Device High Speed Port - UDPHS
DFSDM USB Device Full Speed Data - Analog
DFSDP USB Device Full Speed Data + Analog
DHSDM USB Device High Speed Data - Analog
DHSDP USB Device High Speed Data + Analog
Ethernet 10/100 - EMAC0
ETXCK Transmit Clock or Reference Clock Input
ERXCK Receive Clock Input
ETXEN Transmit Enable Output
ETX0-ETX3 Transmit Data Output
ETXER Transmit Coding Error Output
ERXDV Receive Data Valid Input
ERX0-ERX3 Receive Data Input
ERXER Receive Error Input
ECRS Carrier Sense and Data Valid Input
ECOL Collision Detect Input
EMDC Management Data Clock Output
EMDIO Management Data Input/Output I/O
RMII Ethernet 10/100 - EMAC1
REFCK Transmit Clock or Reference Clock Input
ETXEN Transmit Enable Output
ETX0-ETX1 Transmit Data Output
CRSDV Receive Data Valid Input
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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SAM9X25
ERX0-ERX1 Receive Data Input
ERXER Receive Error Input
EMDC Management Data Clock Output
EMDIO Management Data Input/Output I/O
Analog-to-Digital Converter - ADC
AD0-AD11 12 Analog Inputs Analog
ADTRG ADC Trigger Input
ADVREF ADC Reference Analog
CAN Controller - CANx
CANRXx CAN input Input
CANTXx CAN output Output
Soft Modem - SMD
DIBN Soft Modem Signal I/O
DIBP Soft Modem Signal I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active Level

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11054A–ATARM–27-Jul-11
SAM9X25
4. Package and Pinout
The SAM9X25 is available in 217-ball BGA package.
4.1 Overview of the 217-ball BGA Package
Figure 4-1 shows the orientation of the 217-ball BGA Package.
Figure 4-1. Orientation of the 217-ball BGA Package
4.2 I/O Description
TOP VIEW
BALL A1
12
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
ABCDEF GHJ KL M NPRT U
Table 4-1. SAM9X25 I/O Type Description
I/O Type Voltage Range Analog Pull-up Pull-down Schmitt Trigger
GPIO 1.65-3.6V switchable switchable switchable
GPIO_CLK 1.65-3.6V switchable switchable switchable
GPIO_CLK2 1.65-3.6V switchable switchable switchable
GPIO_ANA 3.0-3.6V Iswitchable switchable
EBI 1.65-1.95V, 3.0-
3.6V switchable switchable
EBI_O 1.65-1.95V, 3.0-
3.6V Reset State Reset State
EBI_CLK 1.65-1.95V, 3.0-
3.6V
RSTJTAG 3.0-3.6V Reset State Reset State Reset State
SYSC 1.65-3.6V Reset State Reset State Reset State
VBG 0.9-1.1V I
USBFS 3.0-3.6V I/O
USBHS 3.0-3.6V I/O
CLOCK 1.65-3.6V I/O
DIB 3.0-3.6V I/O

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SAM9X25
When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the
Pin Description table.
4.2.1 Reset State
In the tables that follow, the column “Reset State” indicates the reset state of the line with
mnemonics.
• “PIO” “/” signal
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned,
the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit
corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released.
• “I”/”O”
Indicates whether the signal is input or output state.
• “PU”/”PD”
Indicates whether Pull-Up, Pull-Down or nothing is enabled.
•“ST”
Table 4-2. SAM9X25 I/O Type Assignment and Frequency
I/O Type
I/O Frequency
(MHz)
Charge Load
(pF)
Output
Current Signal Name
GPIO 40 10 all PIO lines except the following
GPIO_CLK 54 10 MCI0CK, MCI1CK, SPI0SPCK, SPI1SPCK,
EMACx_ETXCK, ISI_MCK
GPIO_CLK2 75 10
GPIO_ANA 25 10 16mA,
40mA (peak) ADx, GPADx
EBI 133 50 (3.3V)
30 (1.8V) all Data lines (Input/output) except the following
EBI_O 66 50 (3.3V)
30 (1.8V)
all Address and control lines (output only) except the
following
EBI_CLK 133 10 CK, #CK
RSTJTAG 10 10 NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK
SYSC 0.25 10 WKUP, SHDN, JTAGSEL, TST, SHDN
VBG 0.25 10 VBG
USBFS 12 10 HFSDPA, HFSDPB/DFSDP, HFSDPC, HFSDMA,
HFSDMB/DFSDM, HFSDMC
USBHS 480 10 HHSDPA, HHSDPB/DHSDP, HHSDMA,
HHSDMB/DHSDM
CLOCK 50 50 XIN, XOUT, XIN32, XOUT32
DIB 25 25 DIBN, DIBP

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SAM9X25
Indicates if Schmitt Trigger is enabled.
Note: Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is
configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”.
That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address
line 20 with Pull-Down.

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SAM9X25
4.3 217-ball BGA Package Pinout
Table 4-3. Pin Description BGA217
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
Ball Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, ST
L3 VDDIOP0 GPIO PA0 I/O TXD0 O SPI1_NPCS1 O PIO, I, PU, ST
P1 VDDIOP0 GPIO PA1 I/O RXD0 I SPI0_NPCS2 O PIO, I, PU, ST
L4 VDDIOP0 GPIO PA2 I/O RTS0 O MCI1_DA1 I/O E0_TX0 O PIO, I, PU, ST
N4 VDDIOP0 GPIO PA3 I/O CTS0 I MCI1_DA2 I/O E0_TX1 O PIO, I, PU, ST
T3 VDDIOP0 GPIO PA4 I/O SCK0 I/O MCI1_DA3 I/O E0_TXER O PIO, I, PU, ST
R1 VDDIOP0 GPIO PA5 I/O TXD1 O CANTX1 O PIO, I, PU, ST
R4 VDDIOP0 GPIO PA6 I/O RXD1 I CANRX1 I PIO, I, PU, ST
R3 VDDIOP0 GPIO PA7 I/O TXD2 O SPI0_NPCS1 O PIO, I, PU, ST
P4 VDDIOP0 GPIO PA8 I/O RXD2 I SPI1_NPCS0 I/O PIO, I, PU, ST
U3 VDDIOP0 GPIO PA9 I/O DRXD I CANRX0 I PIO, I, PU, ST
T1 VDDIOP0 GPIO PA10 I/O DTXD O CANTX0 O PIO, I, PU, ST
U1 VDDIOP0 GPIO PA11 I/O SPI0_MISO I/O MCI1_DA0 I/O PIO, I, PU, ST
T2 VDDIOP0 GPIO PA12 I/O SPI0_MOSI I/O MCI1_CDA I/O PIO, I, PU, ST
T4 VDDIOP0 GPIO_CLK PA13 I/O SPI0_SPCK I/O MCI1_CK I/O PIO, I, PU, ST
U2 VDDIOP0 GPIO PA14 I/O SPI0_NPCS0 I/O PIO, I, PU, ST
U4 VDDIOP0 GPIO PA15 I/O MCI0_DA0 I/O PIO, I, PU, ST
P5 VDDIOP0 GPIO PA16 I/O MCI0_CDA I/O PIO, I, PU, ST
R5 VDDIOP0 GPIO_CLK PA17 I/O MCI0_CK I/O PIO, I, PU, ST
U5 VDDIOP0 GPIO PA18 I/O MCI0_DA1 I/O PIO, I, PU, ST
T5 VDDIOP0 GPIO PA19 I/O MCI0_DA2 I/O PIO, I, PU, ST
U6 VDDIOP0 GPIO PA20 I/O MCI0_DA3 I/O PIO, I, PU, ST
T6 VDDIOP0 GPIO PA21 I/O TIOA0 I/O SPI1_MISO I/O PIO, I, PU, ST
R6 VDDIOP0 GPIO PA22 I/O TIOA1 I/O SPI1_MOSI I/O PIO, I, PU, ST
U7 VDDIOP0 GPIO_CLK PA23 I/O TIOA2 I/O SPI1_SPCK I/O PIO, I, PU, ST
T7 VDDIOP0 GPIO PA24 I/O TCLK0 I TK I/O PIO, I, PU, ST
T8 VDDIOP0 GPIO PA25 I/O TCLK1 I TF I/O PIO, I, PU, ST
R7 VDDIOP0 GPIO PA26 I/O TCLK2 I TD O PIO, I, PU, ST
P8 VDDIOP0 GPIO PA27 I/O TIOB0 I/O RD I PIO, I, PU, ST
U8 VDDIOP0 GPIO PA28 I/O TIOB1 I/O RK I/O PIO, I, PU, ST
R9 VDDIOP0 GPIO PA29 I/O TIOB2 I/O RF I/O PIO, I, PU, ST
R8 VDDIOP0 GPIO PA30 I/O TWD0 I/O SPI1_NPCS3 O E0_MDC O PIO, I, PU, ST
U9 VDDIOP0 GPIO PA31 I/O TWCK0 O SPI1_NPCS2 O E0_TXEN O PIO, I, PU, ST
D3 VDDANA GPIO PB0 I/O E0_RX0 I RTS2 O PIO, I, PU, ST
D4 VDDANA GPIO PB1 I/O E0_RX1 I CTS2 I PIO, I, PU, ST
D2 VDDANA GPIO PB2 I/O E0_RXER I SCK2 I/O PIO, I, PU, ST
E4 VDDANA GPIO PB3 I/O E0_RXDV I SPI0_NPCS3 O PIO, I, PU, ST
D1 VDDANA GPIO_CLK PB4 I/O E0_TXCK I TWD2 I/O PIO, I, PU, ST
E3 VDDANA GPIO PB5 I/O E0_MDIO I/O TWCK2 O PIO, I, PU, ST
B3 VDDANA GPIO_ANA PB6 I/O AD7 I E0_MDC O PIO, I, PU, ST
C2 VDDANA GPIO_ANA PB7 I/O AD8 I E0_TXEN O PIO, I, PU, ST

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C5 VDDANA GPIO_ANA PB8 I/O AD9 I E0_TXER O PIO, I, PU, ST
C1 VDDANA GPIO_ANA PB9 I/O AD10 I E0_TX0 O PCK1 O PIO, I, PU, ST
B2 VDDANA GPIO_ANA PB10 I/O AD11 I E0_TX1 O PCK0 O PIO, I, PU, ST
A3 VDDANA GPIO_ANA PB11 I/O AD0 I E0_TX2 O PWM0 O PIO, I, PU, ST
B4 VDDANA GPIO_ANA PB12 I/O AD1 I E0_TX3 O PWM1 O PIO, I, PU, ST
A2 VDDANA GPIO_ANA PB13 I/O AD2 I E0_RX2 I PWM2 O PIO, I, PU, ST
C4 VDDANA GPIO_ANA PB14 I/O AD3 I E0_RX3 I PWM3 O PIO, I, PU, ST
C3 VDDANA GPIO_ANA PB15 I/O AD4 I E0_RXCK I PIO, I, PU, ST
A1 VDDANA GPIO_ANA PB16 I/O AD5 I E0_CRS I I PIO, I, PU, ST
B1 VDDANA GPIO_ANA PB17 I/O AD6 I E0_COL I I PIO, I, PU, ST
D5 VDDANA GPIO PB18 I/O IRQ I ADTRG I PIO, I, PU, ST
E2 VDDIOP1 GPIO PC0 I/O TWD1 I/O PIO, I, PU, ST
F4 VDDIOP1 GPIO PC1 I/O TWCK1 O PIO, I, PU, ST
F3 VDDIOP1 GPIO PC2 I/O TIOA3 I/O PIO, I, PU, ST
H2 VDDIOP1 GPIO PC3 I/O TIOB3 I/O PIO, I, PU, ST
E1 VDDIOP1 GPIO PC4 I/O TCLK3 I PIO, I, PU, ST
G4 VDDIOP1 GPIO PC5 I/O TIOA4 I/O PIO, I, PU, ST
F2 VDDIOP1 GPIO PC6 I/O TIOB4 I/O PIO, I, PU, ST
F1 VDDIOP1 GPIO PC7 I/O TCLK4 I PIO, I, PU, ST
G1 VDDIOP1 GPIO PC8 I/O UTXD0 O PIO, I, PU, ST
G3 VDDIOP1 GPIO PC9 I/O URXD0 I PIO, I, PU, ST
G2 VDDIOP1 GPIO PC10 I/O PWM0 O PIO, I, PU, ST
H3 VDDIOP1 GPIO PC11 I/O PWM1 O PIO, I, PU, ST
J3 VDDIOP1 GPIO PC12 I/O TIOA5 I/O PIO, I, PU, ST
L2 VDDIOP1 GPIO PC13 I/O TIOB5 I/O PIO, I, PU, ST
H1 VDDIOP1 GPIO PC14 I/O TCLK5 I PIO, I, PU, ST
J2 VDDIOP1 GPIO_CLK PC15 I/O PCK0 O PIO, I, PU, ST
J1 VDDIOP1 GPIO PC16 I/O E1_RXER I UTXD1 O PIO, I, PU, ST
L1 VDDIOP1 GPIO PC17 I/O URXD1 I PIO, I, PU, ST
K2 VDDIOP1 GPIO PC18 I/O E1_TX0 O PWM0 O PIO, I, PU, ST
N3 VDDIOP1 GPIO PC19 I/O E1_TX1 O PWM1 O PIO, I, PU, ST
K1 VDDIOP1 GPIO PC20 I/O E1_RX0 I PWM2 O PIO, I, PU, ST
M3 VDDIOP1 GPIO PC21 I/O E1_RX1 I PWM3 O PIO, I, PU, ST
P3 VDDIOP1 GPIO PC22 I/O TXD3 O PIO, I, PU, ST
J4 VDDIOP1 GPIO PC23 I/O RXD3 I PIO, I, PU, ST
K3 VDDIOP1 GPIO PC24 I/O RTS3 O PIO, I, PU, ST
M2 VDDIOP1 GPIO PC25 I/O CTS3 I PIO, I, PU, ST
P2 VDDIOP1 GPIO PC26 I/O SCK3 I/O PIO, I, PU, ST
M1 VDDIOP1 GPIO PC27 I/O E1_TXEN O RTS1 O PIO, I, PU, ST
K4 VDDIOP1 GPIO PC28 I/O E1_CRSDV I CTS1 I PIO, I, PU, ST
N1 VDDIOP1 GPIO_CLK PC29 I/O E1_TXCK I SCK1 I/O PIO, I, PU, ST
R2 VDDIOP1 GPIO_CLK2 PC30 I/O E1_MDC O PIO, I, PU, ST
N2 VDDIOP1 GPIO PC31 I/O FIQ I E1_MDIO I/O PCK1 O PIO, I, PU, ST
Table 4-3. Pin Description BGA217 (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
Ball Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, ST

14
11054A–ATARM–27-Jul-11
SAM9X25
P13 VDDNF EBI PD0 I/O NANDOE O PIO, I, PU
R14 VDDNF EBI PD1 I/O NANDWE O PIO, I, PU
R13 VDDNF EBI PD2 I/O A21/NANDALE O A21,O, PD
P15 VDDNF EBI PD3 I/O A22/NANDCLE O A22,O, PD
P12 VDDNF EBI PD4 I/O NCS3 O PIO, I, PU
P14 VDDNF EBI PD5 I/O NWAIT I PIO, I, PU
N14 VDDNF EBI PD6 I/O D16 O PIO, I, PU
R15 VDDNF EBI PD7 I/O D17 O PIO, I, PU
M14 VDDNF EBI PD8 I/O D18 O PIO, I, PU
N16 VDDNF EBI PD9 I/O D19 O PIO, I, PU
N17 VDDNF EBI PD10 I/O D20 O PIO, I, PU
N15 VDDNF EBI PD11 I/O D21 O PIO, I, PU
K15 VDDNF EBI PD12 I/O D22 O PIO, I, PU
M15 VDDNF EBI PD13 I/O D23 O PIO, I, PU
L14 VDDNF EBI PD14 I/O D24 O PIO, I, PU
M16 VDDNF EBI PD15 I/O D25 O A20 O A20, O, PD
L16 VDDNF EBI PD16 I/O D26 O A23 O A23, O, PD
L15 VDDNF EBI PD17 I/O D27 O A24 O A24, O, PD
K17 VDDNF EBI PD18 I/O D28 O A25 O A25, O, PD
J17 VDDNF EBI PD19 I/O D29 O NCS2 O PIO, I, PU
K16 VDDNF EBI PD20 I/O D30 O NCS4 O PIO, I, PU
J16 VDDNF EBI PD21 I/O D31 O NCS5 O PIO, I, PU
D10,
D13,
F14
VDDIOM POWER VDDIOM I I
J14,
K14 VDDNF POWER VDDNF I I
H9,
H10,
J9,
J10
GNDIOM GND GNDIOM I I
P7 VDDIOP0 POWER VDDIOP0 I I
H4 VDDIOP1 POWER VDDIOP1 I I
M4,
P6 GNDIOP GND GNDIOP I I
B5 VDDBU POWER VDDBU I I
B6 GNDBU GND GNDBU I I
C6 VDDANA POWER VDDANA I I
D6 GNDANA GND GNDANA I I
R12 VDDPLLA POWER VDDPLLA I I
T13 VDDOSC POWER VDDOSC I I
U13 GNDOSC GND GNDOSC I I
H14,
K8,
K9
VDDCORE POWER VDDCORE I I
H8,
J8,
K10
GNDCORE GND GNDCORE I I
U16 VDDUTMII POWER VDDUTMII I I
Table 4-3. Pin Description BGA217 (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
Ball Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, ST

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11054A–ATARM–27-Jul-11
SAM9X25
T17 VDDUTMIC POWER VDDUTMIC I I
T16 GNDUTMI GND GNDUTMI I I
D14 VDDIOM EBI D0 I/O O, PD
D15 VDDIOM EBI D1 I/O O, PD
A16 VDDIOM EBI D2 I/O O, PD
B16 VDDIOM EBI D3 I/O O, PD
A17 VDDIOM EBI D4 I/O O, PD
B15 VDDIOM EBI D5 I/O O, PD
C14 VDDIOM EBI D6 I/O O, PD
B14 VDDIOM EBI D7 I/O O, PD
A15 VDDIOM EBI D8 I/O O, PD
C15 VDDIOM EBI D9 I/O O, PD
D12 VDDIOM EBI D10 I/O O, PD
C13 VDDIOM EBI D11 I/O O, PD
A14 VDDIOM EBI D12 I/O O, PD
B13 VDDIOM EBI D13 I/O O, PD
A13 VDDIOM EBI D14 I/O O, PD
C12 VDDIOM EBI D15 I/O O, PD
J15 VDDIOM EBI_O A0 O NBS0 O O, PD
H16 VDDIOM EBI_O A1 O
NBS2/DQM/
NWR2
OO, PD
H15 VDDIOM EBI_O A2 O O, PD
H17 VDDIOM EBI_O A3 O O, PD
G17 VDDIOM EBI_O A4 O O, PD
G16 VDDIOM EBI_O A5 O O, PD
F17 VDDIOM EBI_O A6 O O, PD
E17 VDDIOM EBI_O A7 O O, PD
F16 VDDIOM EBI_O A8 O O, PD
G15 VDDIOM EBI_O A9 O O, PD
G14 VDDIOM EBI_O A10 O O, PD
F15 VDDIOM EBI_O A11 O O, PD
D17 VDDIOM EBI_O A12 O O, PD
C17 VDDIOM EBI_O A13 O O, PD
E16 VDDIOM EBI_O A14 O O, PD
D16 VDDIOM EBI_O A15 O O, PD
C16 VDDIOM EBI_O A16 O BA0 O O, PD
B17 VDDIOM EBI_O A17 O BA1 O O, PD
E15 VDDIOM EBI_O A18 O BA2 O O, PD
E14 VDDIOM EBI_O A19 O O, PD
B9 VDDIOM EBI_O NCS0 O O, PU
B8 VDDIOM EBI_O NCS1 O SDCS O O, PU
D9 VDDIOM EBI_O NRD O O, PU
C9 VDDIOM EBI_O NWR0 O NWRE O O, PU
C7 VDDIOM EBI_O NWR1 O NBS1 O O, PU
Table 4-3. Pin Description BGA217 (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
Ball Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, ST

16
11054A–ATARM–27-Jul-11
SAM9X25
A8 VDDIOM EBI_O NWR3 O NBS3/DQM3 O O, PU
D11 VDDIOM EBI_CLK SDCK O O
C11 VDDIOM EBI_CLK #SDCK O O
B12 VDDIOM EBI_O SDCKE O O, PU
B11 VDDIOM EBI_O RAS O O, PU
C10 VDDIOM EBI_O CAS O O, PU
A12 VDDIOM EBI_O SDWE O O, PU
C8 VDDIOM EBI_O SDA10 O O, PU
A10 VDDIOM EBI_O DQM0 O O, PU
B10 VDDIOM EBI_O DQM1 O O, PU
A11 VDDIOM EBI DQS0 I/O O, PD
A9 VDDIOM EBI DQS1 I/O O, PD
A4 VDDANA POWER ADVREF I I
U17 VDDUTMIC VBG VBG I I
T14 VDDUTMII USBFS HFSDPA I/O DFSDP I/O O, PD
T15 VDDUTMII USBFS HFSDMA I/O DFSDM I/O O, PD
U14 VDDUTMII USBHS HHSDPA I/O DHSDP I/O O, PD
U15 VDDUTMII USBHS HHSDMA I/O DHSDM I/O O, PD
R16 VDDUTMII USBFS HFSDPB I/O O, PD
P16 VDDUTMII USBFS HFSDMB I/O O, PD
R17 VDDUTMII USBHS HHSDPB I/O O, PD
P17 VDDUTMII USBHS HHSDMB I/O O, PD
L17 VDDUTMII USBFS HFSDPC I/O O, PD
M17 VDDUTMII USBFS HFSDMC I/O O, PD
R11 VDDIOP0 DIB DIBN I/O O, PU
P11 VDDIOP0 DIB DIBP I/O O, PU
A7 VDDBU SYSC WKUP I I, ST
D8 VDDBU SYSC SHDN O O, PU
P9 VDDIOP0 RSTJTAG BMS I I, PD, ST
D7 VDDBU SYSC JTAGSEL I I, PD
B7 VDDBU SYSC TST I I, PD, ST
U10 VDDIOP0 RSTJTAG TCK I I, ST
T9 VDDIOP0 RSTJTAG TDI I I, ST
T10 VDDIOP0 RSTJTAG TDO O O
U11 VDDIOP0 RSTJTAG TMS I I, ST
R10 VDDIOP0 RSTJTAG RTCK O O
P10 VDDIOP0 RSTJTAG NRST I/O I, PU, ST
T11 VDDIOP0 RSTJTAG NTRST I I, PU, ST
A6 VDDBU CLOCK XIN32 I I
A5 VDDBU CLOCK XOUT32 O O
T12 VDDOSC CLOCK XIN I I
U12 VDDOSC CLOCK XOUT O O
Table 4-3. Pin Description BGA217 (Continued)
Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
Ball Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir
Signal, Dir, PU,
PD, ST

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11054A–ATARM–27-Jul-11
SAM9X25
5. Power Considerations
5.1 Power Supplies
The SAM9X25 has several types of power supply pins.
Note: 1. Refer to Table 4-2 for more details.
Table 5-1. SAM9X25 Power Supplies
Name Voltage Range, nominal Powers
Associated
Ground
VDDCORE 0.9-1.1V, 1.0V ARM core, internal memories, internal peripherals and
part of the system controller. GNDCORE
VDDIOM 1.65-1.95V, 1.8V
3.0-3.6V, 3.3V External Memory Interface I/O lines GNDIOM
VDDNF 1.65-1.95V, 1.8V
3.0-3.6V, 3.3V
NAND Flash I/O and control, D16-D32 and multiplexed
SMC lines GNDIOM
VDDIOP0 1.65-3.6V a part of Peripheral I/O lines(1) GNDIOP
VDDIOP1 1.65-3.6V a part of Peripheral I/O lines (1) GNDIOP
VDDBU 1.65-3.6V the Slow Clock oscillator, the internal 32 kHz RC
oscillator and backup part of the System Controller GNDBU
VDDUTMIC 0.9-1.1V, 1.0V the USB transceiver core logic GNDUTMI
VDDUTMII 3.0-3.6V, 3.3V the USB transceiver interface GNDUTMI
VDDPLLA 0.9-1.1V, 1.0V the PLLA cell GNDOSC
VDDOSC 1.65-3.6V the Main Oscillator cells GNDOSC
VDDANA 3.0-3.6V, 3.3V the Analog to Digital Converter GNDANA

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11054A–ATARM–27-Jul-11
SAM9X25
6. Memories
Figure 6-1. SAM9X25 Memory Mapping
Internal Memories
0xF800 4000
0xF800 8000
0xF801 0000
SPI0
SPI1
0xF800 C000
TC0, TC1, TC2
HSMCI0
0xF000 8000
0xF001 0000
USART0
0xF800 0000
TWI0
0xF001 4000
SYSC
PWMC
0xF801 8000
SSC
0xF801 C000
0xF802 0000
UDPHS
0xF802 4000
0xF801 4000
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
1 MByte
UDPHSRAM
SRAM
Internal Memory Mapping
Peripheral Mapping
Address Memory Space
EBI
Chip Select 0
EBI
Chip Select 2
EBI
Chip Select 4
EBI
Chip Select 5
EBI
Chip Select 1
DDR2/LPDDR
SDR/LPSDR
EBI
Chip Select 3
NAND Flash
Boot Memory (1)
ROM
0xF8030000
0xF8038000
UHP OHCI
0xF000 C000
0xF802 8000
0xF802 C000
UHP EHCI
0xF8034000
0xF803C000
CAN0
CAN1
HSMCI1
0xF804 0000
0xF804 8000
0xF804 4000
0xF804 C000
0xFFFF C000
0xFFFF FFFF
0xFFFF FFFF
0xF000 0000
0xEFFF FFFF
0x7000 0000
0x6FFF FFFF
0x6000 0000
0x5FFF FFFF
0x5000 0000
0x4FFF FFFF
0x4000 0000
0x3FFF FFFF
0x3000 0000
0x2FFF FFFF
0x2000 0000
0x1FFF FFFF
0x1000 0000
0x0000 0000
0x0FFF FFFF 0x0020 0000
0xF000 4000
SMD
0xF805 0000
ADC
0xFFFF FE00
0xFFFF FC00
0xFFFF EC00
0xFFFF EA00
0xFFFF E800
0xFFFF E600
0xFFFF E000
16 Bytes
512 Bytes
512 Bytes
512 Bytes
512 Bytes
512 Bytes
PMC
PIOC
PIOB
PIOA
DBGU
RSTC
512 Bytes
AIC 512 Bytes512 Bytes
512 Bytes
MATRIX 512 Bytes
SMC
0xFFFF FE10
16 Bytes
SHDC
512 Bytes
512 Bytes
512 Bytes
DDR2/LPDDR
SDR/LPSDR
0xFFFF FE20
16 Bytes
0xFFFF FE30
16 Bytes
PIT
0xFFFF FE40
16 Bytes
WDT
0xFFFF FE54 4 Bytes
GPBR
0xFFFF FE70
PMECC 1536 Bytes
0xFFFF C000
Reserved
0xFFFF FFFF
PIOD
RTC
0xFFFF FE60
DMAC1
Reserved
0xFFFF FE50 SCKCR
16 Bytes
System Controller Mapping
16 Bytes
0xFFFF FEB0
Reserved
0xFFFF EE00
BSCR 12 Bytes
DMAC0
0xFFFF DE00
PMERRLOC 512 Bytes
0xFFFF FEC0
Reserved
0xFFFF F000
0xFFFF F200
0xFFFF F400
0xFFFF F600
0xFFFF F800
0xFFFF FA00
Notes:
(1) Can be ROM, EBI1_NCS0 or SRAM
depending on BMSand REMAP
Reserved
Reserved
Reserved
Undefined
(Abort)
Undefined
(Abort)
Undefined
(Abort)
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
256 MBytes
1,792 MBytes
Internal Peripherals
EMAC0
0xF000 0000
TC3, TC4, TC5
TWI1
TWI2
USART1
USART2
USART3
EMAC1
UART0
UART1
0x0010 0000
0x0040 0000
0x0030 0000
0x0060 0000
0x0050 0000
0x0080 0000
0x0070 0000
0x0FFF FFFF
0x0000 0000

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11054A–ATARM–27-Jul-11
SAM9X25
6.1 Memory Mapping
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of
the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 6
are directed to the EBI that associates these banks to the external chip selects, EBI_NCS0 to
EBI_NCS5. Bank 0 is reserved for the addressing of the internal memories, and a second level
of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals
and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
6.2 Embedded Memories
6.2.1 Internal SRAM
The SAM9X25 embeds a total of 32 Kbytes of high-speed SRAM.
After reset and until the Remap Command is performed, the SRAM is only accessible at address
0x0030 0000.
After Remap, the SRAM also becomes available at address 0x0.
6.2.2 Internal ROM
The SAM9X25 embeds an Internal ROM, which contains the SAM-BA program.
At any time, the ROM is mapped at address 0x0010 0000. It is also accessible at address 0x0
(BMS = 1) after the reset and before the Remap Command.
6.3 External Memories
6.3.1 External Bus Interface
• Integrates three External Memory Controllers:
– Static Memory Controller
– DDR2/SDRAM Controller
– MLC NAND Flash ECC Controller
• Additional logic for NAND Flash and CompactFlash®
• Up to 26-bit Address Bus (up to 64 MBytes linear per chip select)
• Up to 6 chips selects, Configurable Assignment:
– Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5
– DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1
– Optional NAND Flash support on NCS3
6.3.2 Static Memory Controller
• 8- or 16-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 16-byte page size)

20
11054A–ATARM–27-Jul-11
SAM9X25
• Multiple device adaptability
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
6.3.3 DDR2SDR Controller
• Supports 8-bank DDR2, LPDDR2, SDR and LPSDR
• Numerous Configurations Supported
– 2K, 4K, 8K, 16K Row Address Memory Parts
– SDRAM with 8 Internal Banks
– SDR-SDRAM with 32-bit Data Path
– DDR2/LPDDR with 16-bit Data Path
– One Chip Select for SDRAM Device (256 Mbyte Address Space)
• Programming Facilities
– Multibank Ping-pong Access (Up to 8 Banks Opened at Same Time = Reduces
Average Latency of Transactions)
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Automatic Update of DS, TCR and PASR Parameters (LPSDR)
• Energy-saving Capabilities
– Self-refresh, Power-down and Deep Power Modes Supported
• SDRAM Power-up Initialization by Software
• CAS Latency of 2, 3 Supported
• Auto Precharge Command Not Used
• SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
– Clock Frequency Change in Precharge Power-down Mode Not Supported