Atmel AT91SAM7L-STK User manual

6409A–ATARM–30-Jun-08
AT91SAM7L-STK Rev. A Starter Kit
....................................................................................................................
User Guide

1-2 AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08

AT91SAM7L-STK Rev. A Starter Kit User Guide i
6409A–ATARM–30-Jun-08
Table of Contents
Section 1
Overview ....................................................................................................................1-1
1.1 Scope................................................................................................................................. 1-1
1.2 Deliverables ...................................................................................................................... 1-1
1.3 The AT91SAM7L-STK Rev. A Starter Board..................................................................... 1-1
Section 2
Setting Up the AT91SAM7L-STK Rev. A Board.........................................................2-1
2.1 Electrostatic Warning......................................................................................................... 2-1
2.2 Requirements..................................................................................................................... 2-1
2.3 Layout ................................................................................................................................ 2-2
2.4 Powering Up the Board...................................................................................................... 2-2
2.5 Getting Started................................................................................................................... 2-2
2.6 AT91SAM7L-STK Rev. A Block Diagram .......................................................................... 2-3
Section 3
Board Description.......................................................................................................3-1
3.1 AT91SAM7L64/128 Microcontroller................................................................................... 3-1
3.2 AT91SAM7L64/128 Block Diagram ................................................................................... 3-3
3.3 Memory.............................................................................................................................. 3-4
3.4 Clock Circuitry.................................................................................................................... 3-4
3.5 Reset Circuitry ................................................................................................................... 3-4
3.6 Shut Down controller.......................................................................................................... 3-4
3.7 Power Supply Circuitry.......................................................................................................3-4
3.8 User Interface .................................................................................................................... 3-4
3.9 Debug Interface ................................................................................................................. 3-4
3.10 Expansion Slot................................................................................................................... 3-4
3.11 PIO Usage ......................................................................................................................... 3-5
Section 4
Configuration..............................................................................................................4-1
4.1 Configuration Straps .......................................................................................................... 4-1
Section 5
Schematics.................................................................................................................5-1
Section 6
Errata..........................................................................................................................6-1

Table of Contents (Continued)
ii AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
6.1 Q1 Footprint Incorrect........................................................................................................ 6-1
6.2 MAX3318 Control Pull-ups................................................................................................. 6-2
Section 7
Revision History .........................................................................................................7-1

AT91SAM7L-STK Rev. A Starter Kit User Guide 1-1
6409A–ATARM–30-Jun-08
Section 1
Overview
1.1 Scope
The AT91SAM7L-STK rev.A starter kit enables evaluation capabilities and code development of applica-
tions running on an AT91SAM7L64/128.
This guide focuses on the AT91SAM7L-STK rev.A board as an evaluation platform.
1.2 Deliverables
The AT91SAM7L-STK rev.A package contains the following items:
An AT91SAM7L-STK rev.A board
Two AAA batteries
1.3 The AT91SAM7L-STK Rev. A Starter Board
The board is equipped with an AT91SAM7L128 (128-lead LQFP package) together with the following:
One DBGU serial communication port
One ZIGBEE extension connector
One JTAG/ICE debug interface
Five user- input push buttons
One WakeUP input push button
One Reset Push Button
One Battery Socket for two AAA batteries
One 400 segments dot matrix LCD

AT91SAM7L-STK Rev. A Starter Kit User Guide 2-1
6409A–ATARM–30-Jun-08
Section 2
Setting Up the AT91SAM7L-STK Rev. A Board
2.1 Electrostatic Warning
The AT91SAM7L-STK rev.A starter board is shipped in a protective anti-static package. The board must
not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be
worn when handling the board. Avoid touching the component pins or any other metallic element.
2.2 Requirements
In order to set up the AT91SAM7L-STK rev.A starter board, the following items are needed:
The AT91SAM7L-STK rev.A starter board
Two AAA batteries

Setting Up the AT91SAM7L-STK Rev. A Board
2-2 AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
2.3 Layout
Figure 2-1. AT91SAM7L-STK Rev. A Board Layout
2.4 Powering Up the Board
The AT91SAM7L-STK rev.A requires 3.0V (2.2V-3.6V) DC input. The power is supplied to the board via
2 AAA batteries or 3.0V VCC pads.
2.5 Getting Started
Please refer to the AT91SAM product pages on the Atmel web site, for the most up-to-date information
on getting started with the AT91SAM7L-STK rev.A.

Setting Up the AT91SAM7L-STK Rev. A Board
AT91SAM7L-STK Rev. A Starter Kit User Guide 2-3
6409A–ATARM–30-Jun-08
2.6 AT91SAM7L-STK Rev. A Block Diagram
Figure 2-2. AT91SAM7L-STK Block Diagram
PC[0..29]
PB[0..23]
PA[0..25]
PC[0..29]
AD[0..3]
PC[0..29]
AD[0..3]
PA[0..25]
PB[0..23]
SHEET 2
SHEET 4
SHEET 3
'%*8
56=,*%((
Processor
Processor
PB[0..23]
PA[0..25]
PC[0..29]
AD[0..3]
ERASE
LCD, KBD
LCD, KBD
PC[0..29]
PB[0..23]
PA[0..25]
AD[0..3]
ERASE
Interfaces
Interfaces
PC[0..29]

AT91SAM7L-STK Rev. A Starter Kit User Guide 3-1
6409A–ATARM–30-Jun-08
Section 3
Board Description
3.1 AT91SAM7L64/128 Microcontroller
•Incorporates the ARM7TDMI®ARM®Thumb®Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™In-circuit Emulation, Debug Communication Channel Support
•Internal High-speed Flash
– 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane
– 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane
– Single Cycle Access at Up to 15 MHz in Worst Case Conditions
– 128-bit Read Access
– Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time: 10 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
•Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
•Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 6 kbytes
• 2 Kbytes Directly on Main Supply that Can Be Used as Backup SRAM
• 4 Kbytes in the Core
•Memory Controller (MC)
– Enhanced Embedded Flash Controller, Abort Status and Misalignment Detection
•Reset Controller (RSTC)
– Based on Brownout Reset and Low-power Factory-calibrated Brownout Detector
– Provides External Reset Signal Shaping and Reset Source Status
•Clock Generator (CKGR)
– Low-power 32 kHz RC Oscillator, 32 kHz On-chip Oscillator, 2 MHz Fast RC Oscillator and one PLL
•Supply Controller (SUPC)
– Minimizes Device Power Consumption
– Manages the Different Supplies On Chip
– Supports Multiple Wake-up Sources
•Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode
– Three Programmable External Clock Signals
– Handles Fast Start Up
•Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected

Board Description
3-2 AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
•Debug Unit (DBGU)
– Two-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access
Prevention
•Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
•Windowed Watchdog (WDT)
– 12-bit Key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter may be Stopped While the Processor is in Debug State or in Idle Mode
•Real-time Clock (RTC)
– Two Hundred Year Calendar with Alarm
– Runs Off the Internal RC or Crystal Oscillator
•Three Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– Eighty Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
•Eleven Peripheral DMA Controller (PDC) Channels
•One Segmented LCD Controller
– Display Capacity of Forty Segments and Ten Common Terminals
– Software Selectable LCD Output Voltage (Contrast)
•Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA®Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Manchester Encoder/Decoder
– Full Modem Line Support on USART1
•One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
•One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
•One Four-channel 16-bit PWM Controller (PWMC)
•One Two-wire Interface (TWI)
– Master, Multi-Master and Slave Mode Support, All Atmel®Two-wire EEPROMs and I2C compatible
Devices Supported
– General Call Supported in Slave Mode
•One 4-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
•SAM-BA®Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
– In Application Programming Function (IAP)
•IEEE®1149.1 JTAG Boundary Scan on All Digital Pins
•I/Os, including Four High-current Drive I/O lines, Up to 4 mA Each
•Power Supplies
– Embedded 1.8V Regulator, Drawing up to 60 mA for the Core with Programmable Output Voltage
– Single Supply 1.8V - 3.6V
– Zero-power Power-on Reset and Brownout Detector, Fully Programmable
•Fully Static Operation: Up to 36 MHz at 85°C
•Available in a 128-lead LQFP Green and a 144-ball LFBGA Green Package

Board Description
AT91SAM7L-STK Rev. A Starter Kit User Guide 3-3
6409A–ATARM–30-Jun-08
3.2 AT91SAM7L64/128 Block Diagram
Figure 3-1. AT91SAM7L64/128 Block Diagram
TDI
TDO
TMS
TCK
NRST
FIQ
IRQ0-IRQ1
PCK0-PCK2
PMC
Peripheral Bridge
Peripheral Data
Controller
AIC
PLL
SRAM
2 Kbytes( Back-up)
4 Kbytes (Core)
ARM7TDMI
Processor
ICE
JTAG
SCAN
JTAGSEL
PIOA (26 IOs)
Timer Counter
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
Flash
64/128 Kbytes
DRXD
DTXD TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Memory Controller
Abort
Status
Address
Decoder
Misalignment
Detection
PIO
PIO
APB
Embedded
Flash
Controller
AD0
AD1
AD2
AD3
ADTRG
11 Channels
PDC
PDC
SPI
PDC
ADC
ADVREF
TC0
TC1
TC2
TWD
TWCK
TWI
XIN
XOUT
VDDIO1
PWMC
PWM0
PWM1
PWM2
PWM3
1.8 V
Voltage
Regulator
GND
VDDOUT
VDDCORE
VDDIO1
VDDCORE
Fast Flash
Programming
Interface
ERASE
PGMD0-PGMD15
PGMNCMD
PGMEN0-PGMEN2
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
VDDIO2
TST
DBGU PDC
PDC
PIO
PIT
WDT
System Controller
VDDIO1
SAM-BA
ROM (12 Kbytes)
RSTB
FWUP
PIOB (24 IOs)
LCD Controller
SEG00-SEG39
COM0-COM9
PIOC (30 IOs)
32k RCOSC
Supply
Controller
POR
OSC
BOD
2 MHz RCOSC
VDDIO1
RTC
USART0
RXD0
TXD0
SCK0
RTS0
CTS0
PDC
PDC
USART1
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
PDC
PDC
PIO
PDC
PDC
VDDLCD
CAPP1
CAPM1
CAPP2
CAPM2
CLKIN
PLLRC
VDD3V6
LCD
Voltage
Regulator VDDIO2
Charge
Pump
VDDINLCD

Board Description
3-4 AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
3.3 Memory
6 Kbytes of Internal single-cycle access High-speed SRAM
64/128 Kbytes of Internal single-cycle access High-speed Flash
3.4 Clock Circuitry
32.768 KHz standard crystal for the oscillator
3.5 Reset Circuitry
Internal reset controller with a bi-directional reset pin
External reset push button
3.6 Shut Down controller
Programmable shutdown and Wake-Up
Wake-up push button.
3.7 Power Supply Circuitry
For dynamic power consumption, the AT91SAM7L64/128 consumes a maximum of 30 mA on VCC at
full speed 36MHz
On board 2 AAA batteries or 3V DC input power pad directly supplied to VCC
3.8 User Interface
Five user- input push buttons, four direction buttons and one ok button
3.9 Debug Interface
20-pin JTAG/ICE interface connector
One Serial interface (DBGU COM Port) via RS-232 DB9 male socket
3.10 Expansion Slot
One ZIGBEE expansion connector for Atmel AT86RF230 adaptor
All PIOC signals of the AT91SAM7L64/128 are routed to peripheral extension connector (J6). This
allows the developer to add external hardware components or boards.

Board Description
AT91SAM7L-STK Rev. A Starter Kit User Guide 3-5
6409A–ATARM–30-Jun-08
3.11 PIO Usage
Table 3-1. PIO Controller A
I/O Line Peripheral A Peripheral B Peripheral Usage Powered by
PA0 Segment LCD PANEL COM0 VDDIO2
PA1 Segment LCD PANEL COM1 VDDIO2
PA2 Segment LCD PANEL COM2 VDDIO2
PA3 Segment LCD PANEL COM3 VDDIO2
PA4 Segment LCD PANEL COM4 VDDIO2
PA5 Segment LCD PANEL COM5 VDDIO2
PA6 Segment LCD PANEL SEG0 VDDIO2
PA7 Segment LCD PANEL SEG1 VDDIO2
PA8 Segment LCD PANEL SEG2 VDDIO2
PA9 Segment LCD PANEL SEG3 VDDIO2
PA10 Segment LCD PANEL SEG4 VDDIO2
PA11 Segment LCD PANEL SEG5 VDDIO2
PA12 Segment LCD PANEL SEG6 VDDIO2
PA13 Segment LCD PANEL SEG7 VDDIO2
PA14 Segment LCD PANEL SEG8 VDDIO2
PA15 Segment LCD PANEL SEG9 VDDIO2
PA16 Segment LCD PANEL SEG10 VDDIO2
PA17 Segment LCD PANEL SEG11 VDDIO2
PA18 Segment LCD PANEL SEG12 VDDIO2
PA19 Segment LCD PANEL SEG13 VDDIO2
PA20 Segment LCD PANEL SEG14 VDDIO2
PA21 Segment LCD PANEL SEG15 VDDIO2
PA22 Segment LCD PANEL SEG16 VDDIO2
PA23 Segment LCD PANEL SEG17 VDDIO2
PA24 Segment LCD PANEL SEG18 VDDIO2
PA25 Segment LCD PANEL SEG19 VDDIO2

Board Description
3-6 AT91SAM7L-STK Rev. A Starter Kit User Guide
6409A–ATARM–30-Jun-08
Table 3-2. PIO Controller B
I/O Line Peripheral A Peripheral B Peripheral Usage Powered by
PB0 Segment LCD PANEL SEG20 VDDIO2
PB1 Segment LCD PANEL SEG21 VDDIO2
PB2 Segment LCD PANEL SEG22 VDDIO2
PB3 Segment LCD PANEL SEG23 VDDIO2
PB4 Segment LCD PANEL SEG24 VDDIO2
PB5 Segment LCD PANEL SEG25 VDDIO2
PB6 Segment LCD PANEL SEG26 VDDIO2
PB7 Segment LCD PANEL SEG27 VDDIO2
PB8 Segment LCD PANEL SEG28 VDDIO2
PB9 Segment LCD PANEL SEG29 VDDIO2
PB10 Segment LCD PANEL SEG30 VDDIO2
PB11 Segment LCD PANEL SEG31 VDDIO2
PB12 NPCS3 Segment LCD PANEL SEG32 VDDIO2
PB13 NPCS2 Segment LCD PANEL SEG33 VDDIO2
PB14 NPCS1 Segment LCD PANEL SEG34 VDDIO2
PB15 RTS1 Segment LCD PANEL SEG35 VDDIO2
PB16 RTS0 Segment LCD PANEL SEG36 VDDIO2
PB17 DTR1 Segment LCD PANEL SEG37 VDDIO2
PB18 PWM0 Segment LCD PANEL SEG38 VDDIO2
PB19 PWM1 Segment LCD PANEL SEG39 VDDIO2
PB20 PWM2 Segment LCD PANEL COM6 VDDIO2
PB21 PWM3 Segment LCD PANEL COM7 VDDIO2
PB22 NPCS1 PCK1 Segment LCD PANEL COM8 VDDIO2
PB23 PCK0 NPCS3 Segment LCD PANEL COM9 VDDIO2

Board Description
AT91SAM7L-STK Rev. A Starter Kit User Guide 3-7
6409A–ATARM–30-Jun-08
Table 3-3. PIO Controller C
I/O Line Peripheral A Peripheral B Peripheral Usage Powered by
PC0 CTS1 PWM2 User’s Input Buttons OK VDDIO1
PC1 DCD1 TIOA2 User’s Input Buttons UP VDDIO1
PC2 DTR1 TIOB2 User’s Input Buttons RIGHT VDDIO1
PC3 DSR1 TCLK1 User’s Input Buttons DOWN VDDIO1
PC4 RI1 TCLK2 User’s Input Buttons LEFT VDDIO1
PC5 IRQ1 NPCS2 ZIGBEE IRQ1 VDDIO1
PC6 NPCS1 PCK2 ZIGBEE NPCS1 VDDIO1
PC7 PWM0 TIOA0 MAX3318E FORCEOFF VDDIO1
PC8 PWM1 TIOB0 ZIGBEE RSIN VDDIO1
PC9 PWM2 SCK0 ZIGBEE SLP_IR VDDIO1
PC10 TWD NPCS3 VDDIO1
PC11 TWCK TCLK0 VDDIO1
PC12 RXD0 NPCS3 MAX3318E FORCEON VDDIO1
PC13 TXD0 PCK0 MAX3318E INVALID VDDIO1
PC14 RTS0 ADTRG MAX3318E READY VDDIO1
PC15 CTS0 PWM3 VCC/VBAT MONITOR ENABLE VDDIO1
PC16 DRXD NPCS1 MAX3318E DRXD VDDIO1
PC17 DTXD NPCS2 MAX3318E DTXD VDDIO1
PC18 NPCS0 PWM0 VDDIO1
PC19 MISO PWM1 ZIGBEE MISO VDDIO1
PC20 MOSI PWM2 ZIGBEE MOSI VDDIO1
PC21 SPCK PWM3 ZIGBEE SPCK VDDIO1
PC22 NPCS3 TIOA1 VDDIO1
PC23 PCK0 TIOB1 VDDIO1
PC24 RXD1 PCK1 VDDIO1
PC25 TXD1 PCK2 VDDIO1
PC26 RTS0 FIQ VDDIO1
PC27 NPCS2 IRQ0 VDDIO1
PC28 SCK1 PWM0 VDDIO1
PC29 RTS1 PWM1 VDDIO1

AT91SAM7L-STK Rev. A Starter Kit User Guide 4-1
6409A–ATARM–30-Jun-08
Section 4
Configuration
4.1 Configuration Straps
Table 4-1 gives details of configuration straps on the AT91SAM7L-STK rev. A starter board and their
default settings.
Notes: 1. This jumper is used to erase and reinitialize the internal flash content and some of the NVM bits.
2. This jumper is provided for power consumption measurement. By default, it is closed. To use this fea-
ture, the user has to open the strap and insert an ammeter.
Table 4-1.
Designation Default Setting Feature
J6 pins 39-40 Opened Closed for internal flash erase(1)
J8 Closed VCC jumper(2)
SD1 Opened Disables VDDIO2 to VDDLCD connection
SD2 2-3 Selects VCC or VDD3V6 to VDDLCD
SD3 Closed Enables VDDOUT applying to VDDCORE
SD4 2-3 Selects VDDINLCD input
R20 IN Enables the ICE NRST input
TP1 N.A RX
TP2 N.A TX
TP3 N.A CLKIN
TP4 N.A FWUP
TP5 N.A ADREF
TP6 N.A XOUT
TP7 N.A NRSTB
TP8 N.A VDDIO2
TP9 N.A VDD3V6
TP10 N.A VDDOUT

AT91SAM7L-STK Rev. A Starter Kit User Guide 5-1
6409A–ATARM–30-Jun-08
Section 5
Schematics
This section contains the following schematics:
Top Level
Interfaces
LCD, KBD
Processor

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PC[0..29]
PB[0..23]
PA[0..25]
PC[0..29]
AD[0..3]
PC[0..29]
AD[0..3]
PA[0..25]
PB[0..23]
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A
AT91SAM7L-STK
14
A
XX-XXX-XXPP XXX
Top level
17MAR08
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A
AT91SAM7L-STK
14
A
XX-XXX-XXPP XXX
Top level
17MAR08
REV DATEMODIF. DES. DATE VER.
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A
AT91SAM7L-STK
14
A
XX-XXX-XXPP XXX
Top level
17MAR08
SHEET 2
SHEET 4
SHEET 3


Processor
Processor
PB[0..23]
PA[0..25]
PC[0..29]
AD[0..3]
ERASE
LCD, KBD
LCD, KBD
PC[0..29]
PB[0..23]
PA[0..25]
AD[0..3]
ERASE
Interfaces
Interfaces
PC[0..29]

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PC19
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC8
PC21
PC5
PC6
PC20
PC9
PC17
PC16
PC13
PC14 PC12
PC7
PC[0..29]
VCC VCC
VCC
VCC
VCC
VCC VCC
VCC
GND
GND
GND GND
GND
GND
GND
VCC
GND
GND
VCC VCC
GND
GND
GND
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A
AT91SAM7L-STK
24
A
XX-XXX-XXPP XXX
Interfaces
17MAR08
REV DATEMODIF. DES. DATE VER.
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A
AT91SAM7L-STK
24
A
XX-XXX-XXPP XXX
Interfaces
17MAR08
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A
AT91SAM7L-STK
24
A
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Interfaces
17MAR08
ZIGBEE INTERFACE
Note: Pin 1 on Zigbee board RZ502 matches pin 2 on this connector
MISO
SPCKNPSC1
RSTN
IRQ1
MOSI
SLP_TR
SERIAL DEBUG PORT
Only for AT86RF230Rev.A connexion
not required for Rev.B on
DTXD
DRXD
TX
RX
TP2
TESTPOINT
TP2
TESTPOINT
TP1
TESTPOINT
TP1
TESTPOINT
C1
100NF
C1
100NF
C6
NOT POPULATED
C6
NOT POPULATED
C3
100NF
C3
100NF
U2
NC7SZ175P6X
U2
NC7SZ175P6X
CP
1
GND 2
D
3
Q4
VCC 5
C
6
J4
D09P24A4GX00
J4
D09P24A4GX00
5
4
3
2
1
9
8
7
6
10 11
R3
100K
R3
100K
C2
100NF
C2
100NF
AAA
AAA
J1
AAA
AAA
J1
J5J5
1 2
3 4
5 6
7 8
9 10
11 12
13
15
17
19
14
16
18
20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
R5 0RR5 0R
J3
Pad
J3
Pad
1
1
R2
100K
R2
100K
R4
NOT POPULATED
R4
NOT POPULATED
R7
10K
R7
10K
C5
100NF
C5
100NF
C7
NOT POPULATED
C7
NOT POPULATED
J2
Pad
J2
Pad
1
1
U1
MAX3318E
U1
MAX3318E
READY 1
C1+ 2
C1- 4
C2+ 5
C2- 6
VCC
19
GND
18
V+
3
V-
7
R1IN
16
R2IN
9
R1OUT 15
R2OUT 10
INVALID 11
FORCEOFF 20
FORCEON 14
D1OUT
17
D2OUT
8
D1IN 13
D2IN 12
C4
100NF
C4
100NF
R6 0RR6 0R
U3
NC7SZ125P5X
U3
NC7SZ125P5X
2 4
3 5 1
R1
100K
R1
100K

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PA5 COM5
PA10 SEG4
PA7 SEG1
PA3 COM3
PA19 SEG13
PA16 SEG10
PA21 SEG15
PA17 SEG11
PA15 SEG9
PA0 COM0
PA18 SEG12
PA24 SEG18
PA20 SEG14
PA23 SEG17
PA22 SEG16
PA9 SEG3
PA12 SEG6
PA6 SEG0
PA1 COM1
PA8 SEG2
PA14 SEG8
PA4 COM4
PA13 SEG7
PA11 SEG5
PA25 SEG19
PA2 COM2 PB2 SEG22
PB1 SEG21
PB5 SEG25
PB4 SEG24
PB3 SEG23
PB0 SEG20
PB7 SEG27
PB13 SEG33
PB8 SEG28
PB12 SEG32
PB9 SEG29
PB17 SEG37
PB16 SEG36
PB10 SEG30
PB6 SEG26
PB15 SEG35
PB14 SEG34
PB11 SEG31
PB21 COM7
PB23 COM9
PB19 SEG39
PB22 COM8
PB20 COM6
PB18 SEG38
PC2
PC3
PC0
PC4
PC1
PC10
PC11
PC25
PC26
PC27
PC28
PC29
PC5
PC6
PC7
PC8
PC9
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC1
PC4
PC3
PC28PC29
PC23
PC21
PC17
PC25
PC27
PC3
PC1
PC13
PC11
PC7
PC15
PC5
PC9
PC19
PC24
PC26
PC18
PC16
PC22
PC20
PC4
PC2
PC0
PC14
PC12
PC10
PC8
PC6
AD3
AD2
AD1
AD0
AD1
AD3 AD0 AD2
ERASE
COM4 COM3 COM2 COM1 COM0 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG22 SEG24 SEG26 SEG28 SEG30 SEG32 SEG34 SEG36 SEG14 SEG16 SEG18 SEG20
COM9 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 COM5 COM6 COM7 COM8 SEG23 SEG25 SEG27 SEG29 SEG31 SEG33 SEG35 SEG37 SEG15 SEG17 SEG19 SEG21
SEG38SEG39
PC15
AD3
PC0
PC2
PC[0..29]
PB[0..23]
PA[0..25]
AD[0..3]
ERASE
AD[0..3]
VCC
GND
GND
VCC
GND
VCC
GND
VCC VCC
GND GND GND
REV DATEMODIF. DES. DATE VER.
SCALE
1/1
REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDIT
A
AT91SAM7L-STK
34
A
XX-XXX-XXPP XXX
LCD, KBD
17MAR08
REV DATEMODIF. DES. DATE VER.
SCALE
1/1
REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDIT
A
AT91SAM7L-STK
34
A
XX-XXX-XXPP XXX
LCD, KBD
17MAR08
REV DATEMODIF. DES. DATE VER.
SCALE
1/1
REV. SHEET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
INIT EDIT
A
AT91SAM7L-STK
34
A
XX-XXX-XXPP XXX
LCD, KBD
17MAR08
VCC/VBAT MONITOR
UP
OK
RIGHT
LEFT
DOWNOK
UP
RIGHT
LEFT
DOWN
CTS1/PWM2_WKUP0DCD1/TIOA2_WKUP1 DTR1/TIOB2_WKUP2DSR1/TCLK1_WKUP3 RI1/TCLK2_WKUP4IRQ1/NPCS2_WKUP5 NPCS1/PCK2_WKUP6PWM0/TIOA0 PWM1/TIOB0PWM2/SCK0 TWD/NPCS3TWCK/TCLK0_WKUP7 RXD0/NPCS3_WKUP8TXD0/PCK0_WKUP9 RTS0/ADTRG_WKUP10CTS0/PWM3_WKUP11 DRXD/NPCS1/DTXD/MPCS2 NPCS0/PWM0MISO/PWM1 MOSI/PWM2SPCK/PWM3 MPCS3/TIOA1PCK0/TIOB1 RXD1/PCK1TXD1/PCK2 RTS0/FIQ_WKUP12NPCS2/IRQ0_WKUP13 SCK1/PWM0_WKUP14RTS1/PWM1_WKUP15
PCK0/NPCS3
NPCS3
NPCS2
NPCS1
RTS1
RTS0
DTR1
PWM0
PWM1
PWM2
PWM3
NPSC1/PCK1
R11
NOT POPULATED
R11
NOT POPULATED
BP4
3-1437565-0
BP4
3-1437565-0
LCD1
LCD_GS08001AA
LCD1
LCD_GS08001AA
COM5 50 COM4 49 COM3 48 COM2 47 COM1 46
SEG1 45 SEG3 44 SEG5 43 SEG7 42 SEG9 41
SEG11 40 SEG13 39 SEG15 38 SEG17 37 SEG19 36 SEG21 35 SEG23 34 SEG25 33 SEG27 32 SEG29 31 SEG31 30 SEG33 29 SEG35 28 SEG37 27 SEG39 26
SEG40
25
SEG38
24
COM6
1
COM7
2
COM8
3
COM9
4
COM10
5
SEG2
6
SEG4
7
SEG6
8
SEG8
9
SEG10
10
SEG12
11
SEG14
12
SEG16
13
SEG18
14
SEG20
15
SEG22
16
SEG24
17
SEG26
18
SEG28
19
SEG30
20
SEG32
21
SEG34
22
SEG36
23
BP1
3-1437565-0
BP1
3-1437565-0
BP5
3-1437565-0
BP5
3-1437565-0
JS1JS1
BP2
3-1437565-0
BP2
3-1437565-0
Q1
FDV304P
Q1
FDV304P
1
3 2
R9
10K
R9
10K
J6J6
1 2
3 4
5 6
7 8
9 10
11 12
13
15
17
19
14
16
18
20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
BP3
3-1437565-0
BP3
3-1437565-0
R10
NOT POPULATED
R10
NOT POPULATED
R8
10K
R8
10K