Atmel AT90S4433-8AC User manual

1
Features
•Utilizes the AVR®RISC Architecture
•AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32x8GeneralPurposeWorkingRegisters
– Up to 10 MIPS Throughput at 10 MHz
•Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9-, or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
–FullDuplexUART
•• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
•• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.8 mA
– Idle Mode: 0.8 mA
– Power-down Mode: <1 µA
•I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP and SOIC
•Operating Voltages
– 2.7 - 6.0V (AT90S2313-4)
– 4.0 - 6.0V (AT90S2313-10)
•Speed Grades
– 0 - 4 MHz (AT90S2313-4)
– 0 - 10 MHz (AT90S2313-10)
Pin Configuration
PDIP/SOIC
8-bit
Microcontroller
with 2K Bytes
of In-System
Programmable
Flash
AT90S2313
Rev. 0839I–AVR–06/02

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Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S2313
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
Figure 1. The AT90S2313 Block Diagram
The AT90S2313 provides the following features: 2K bytes of In-System Programmable
Flash, 128 bytes EEPROM, 128 bytes SRAM, 15 general purpose I/O lines, 32 general
purpose working registers, flexible Timer/Counters with compare modes, internal and
external interrupts, a programmable serial UART, programmable Watchdog Timer with
internal Oscillator, an SPI serial port for Flash memory downloading and two software

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selectable power-saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next external interrupt or Hardware Reset.
The device is manufactured using Atmel’s high-density non-volatile memory technology.
The On-chip In-System Programmable Flash allows the Program memory to be repro-
grammed in-system through an SPI serial interface or by a conventional non-volatile
memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-
grammable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful
microcontroller that provides a highly flexible and cost-effective solution to many embed-
ded control applications.
The AT90S2313 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-
cuit Emulators and evaluation kits.
Pin Descriptions
VCC Supply voltage pin.
GND Ground pin.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the
negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out-
put buffers can sink 20 mA and can drive LED displays directly. When pins PB0 to PB7
are used as inputs and are externally pulled low, they will source current if the internal
pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S2313 as listed
on page 51.
Port D (PD6..PD0) Port D has seven bi-directional I/O ports with internal pull-up resistors, PD6..PD0. The
Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port D pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S2313 as listed
on page 56.
RESET Reset input. A low level on this pin for more than 50 ns will generate a Reset, even if the
clock is not running. Shorter pulses are not guaranteed to generate a Reset.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.

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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can
be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3.
Figure 2. Oscillator Connections
Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be
connected as indicated in the figure.
Figure 3. External Clock Drive Configuration
XTAL2
XTAL1
GND
C2
C1
MAX 1 HC BUFFER
HC

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Architectural
Overview
The fast-access Register File concept contains 32 x 8-bit general purpose working reg-
isters with a single clock cycle access time. This means that during one single clock
cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output
from the Register File, the operation is executed, and the result is stored back in the
Register File –in one clock cycle.
Figure 4. The AT90S2313 AVR RISC Architecture
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing –enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up func-
tion. These added function registers are the 16-bit X-register, Y-register, and Z-register.
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S2313 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be
used on the Register File as well. This is enabled by the fact that the Register File is
assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be
accessed as though they were ordinary memory locations.

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The I/O memory space contains 64 addresses for CPU peripheral functions such as
control registers, Timer/Counters, A/D converters and other I/O functions. The I/O mem-
ory can be accessed directly or as the Data Space locations following those of the
Register File, $20 - $5F.
The AVR has Harvard architecture –with separate memories and buses for program
and data. The program memory is accessed with a 2-stage pipeline. While one instruc-
tion is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Programmable Flash memory.
With the relative jump and call instructions, the whole 1K address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 8-bit Stack Pointer (SP) is read/write accessible in the
I/O space.
The 128 bytes data SRAM + Register File and I/O Registers can be easily accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 5. Memory Maps
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-
arate Interrupt Vector in the Interrupt Vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.

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General Purpose
Register File
Figure 6 shows the structure of the 32 general purpose registers in the CPU.
Figure 6. AVR CPU General Purpose Working Registers
All the register operating instructions in the instruction set have direct and single-cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI
instruction for load immediate constant data. These instructions apply to the second half
of the registers in the Register File (R16..R31). The general SBC, SUB, CP, AND, OR,
and all other operations between two registers or on a single register apply to the entire
Register File.
As shown in Figure 6, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although the Register
File is not physically implemented as SRAM locations, this memory organization pro-
vides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set
to index any register in the file.
X-register, Y-register, and Z-
register
The registers R26..R31 have some added functions to their general purpose usage.
These registers are the address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y and Z are defined in Figure 7.
Figure 7. X-, Y-, and Z-Registers
70Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register Low Byte
R27 $1B X-register High Byte
R28 $1C Y-register Low Byte
R29 $1D Y-register High Byte
R30 $1E Z-register Low Byte
R31 $1F Z-register High Byte
15 0
X-register 7 0 7 0
R27 ($1B) R26 ($1A)
15 0
Y-register 7 0 7 0
R29 ($1D) R28 ($1C)
15 0
Z-register 7 0 7 0
R31 ($1F) R30 ($1E)

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In the different addressing modes these address registers have functions as fixed dis-
placement, automatic increment and decrement (see the descriptions for the different
instructions).
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, ALU operations between regis-
ters in the Register File are executed. The ALU operations are divided into three main
categories –arithmetic, logical, and bit functions.
In-System Programmable
Flash Program Memory
The AT90S2313 contains 2K bytes On-chip In-System Programmable Flash memory for
program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as
1K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles.
The AT90S2313 Program Counter (PC) is 10 bits wide, thus addressing the 1,024 pro-
gram memory addresses.
See page 60 for a detailed description on Flash data downloading. See page 10 for the
different addressing modes.
EEPROM Data Memory The AT90S2313 contains 128 bytes of EEPROM data memory. It is organized as a sep-
arate data space in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 39, specifying the EEPROM Address Register, the
EEPROM Data Register and the EEPROM Control Register.
For the SPI data downloading, see page 68 for a detailed description.

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SRAM Data Memory Figure 8 shows how the AT90S2313 data memory is organized.
Figure 8. SRAM Organization
The 224 data memory locations address the Register File, I/O memory and the data
SRAM. The first 96 locations address the Register File + I/O memory, and the next 128
locations address the data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Dis-
placement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the
Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The Direct addressing reaches the entire data address space.
The Indirect with Displacement mode features 63 address locations reached from the
base address given by the Y- and Z-registers.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are used and decremented and
incremented.
The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of data
SRAM in the AT90S2313 are all directly accessible through all these addressing modes.
Register File Data Address Space
R0 $00
R1 $01
R2 $02
……
R29 $1D
R30 $1E
R31 $1F
I/O Registers
$00 $20
$01 $21
$02 $22
……
$3D $5D
$3E $5E
$3F $5F
Internal SRAM
$60
$61
$62
…
$DD
$DE
$DF

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Program and Data
Addressing Modes
The AT90S2313 AVR RISC microcontroller supports powerful and efficient addressing
modes for access to the Program memory (Flash) and Data memory. This section
describes the different addressing modes supported by the AVR architecture. In the fig-
ures, OP means the operation code part of the instruction word. To simplify, not all
figures show the exact location of the addressing bits.
Register Direct, Single
Register Rd
Figure 9. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Direct, Two Registers
Rd and Rr
Figure 10. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
(Rd).
I/O Direct Figure 11. I/O Direct Addressing

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Operand address is contained in 6 bits of the instruction word. n is the destination or
source register address.
Data Direct Figure 12. Direct Data Addressing
A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify
the destination or source register.
Data Indirect with
Displacement
Figure 13. Data Indirect with Displacement
Operand address is the result of the Y- or Z-register contents added to the address con-
tained in 6 bits of the instruction word.
Data Indirect Figure 14. Data Indirect Addressing
Operand address is the contents of the X-, Y-, or Z-register.

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Data Indirect with Pre-
decrement
Figure 15. Data Indirect Addressing with Pre-decrement
The X-, Y-, or Z-register is decremented before the operation. Operand address is the
decremented contents of the X-, Y-, or Z-register.
Data Indirect with Post-
increment
Figure 16. Data Indirect Addressing with Post-increment
The X-, Y-, or Z-register is incremented after the operation. Operand address is the con-
tents of the X-, Y-, or Z-register prior to incrementing.
Constant Addressing Using
the LPM Instruction
Figure 17. Code Memory Constant Addressing
Constant byte address is specified by the Z-register contents. The 15 MSBs select word
address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =
1).

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Indirect Program Addressing,
IJMP and ICALL
Figure 18. Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Relative Program Addressing,
RJMP and RCALL
Figure 19. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to
2047.

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Memory Access and
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
TheAVRCPUisdrivenbytheSystemClockØ, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results
for functions per cost, functions per clocks and functions per power-unit.
Figure 20. The Parallel Instruction Fetches and Instruction Executions
Figure 21 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 21. Single-cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described
in Figure 22.
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4

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Figure 22. On-chip Data SRAM Access Cycles
I/O Memory The I/O space definition of the AT90S2313 is shown in Table 1.
System Clock Ø
WR
RD
Data
Data
Address Address
T1 T2 T3 T4
Prev. Address
Read Write
Table 1. AT90S2313 I/O Space(1)
Address Hex Name Function
$3F ($5F) SREG Status Register
$3D ($5D) SPL Stack Pointer Low
$3B ($5B) GIMSK General Interrupt MaSK Register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt MaSK Register
$38 ($58) TIFR Timer/Counter Interrupt Flag Register
$35 ($55) MCUCR MCU general Control Register
$33 ($53) TCCR0 Timer/Counter 0 Control Register
$32 ($52) TCNT0 Timer/Counter 0 (8-bit)
$2F ($4F) TCCR1A Timer/Counter 1 Control Register A
$2E ($4E) TCCR1B Timer/Counter 1 Control Register B
$2D ($4D) TCNT1H Timer/Counter 1 High Byte
$2C ($4C) TCNT1L Timer/Counter 1 Low Byte
$2B ($4B) OCR1AH Output Compare Register 1 High Byte
$2A ($4A) OCR1AL Output Compare Register 1 Low Byte
$25 ($45) ICR1H T/C 1 Input Capture Register High Byte
$24 ($44) ICR1L T/C 1 Input Capture Register Low Byte
$21 ($41) WDTCR Watchdog Timer Control Register
$1E ($3E) EEAR EEPROM Address Register
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$18 ($38) PORTB Data Register, Port B
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B

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Note: 1. Reserved and unused locations are not shown in the table.
All AT90S2313 I/O and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions transferring data between the 32 general pur-
pose working registers and the I/O space. I/O Registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as
SRAM, $20 must be added to this address. All I/O Register addresses throughout this
document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical “1”to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a “1”back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The I/O and peripherals control registers are explained in the following sections.
Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
Global Interrupt Enable bit is cleared (zero), none of the interrupts are enabled indepen-
dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
•Bit6–T:BitCopyStorage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
$12 ($32) PORTD Data Register, Port D
$11 ($31) DDRD Data Direction Register, Port D
$10 ($30) PIND Input Pins, Port D
$0C ($2C) UDR UART I/O Data Register
$0B ($2B) USR UART Status Register
$0A ($2A) UCR UART Control Register
$09 ($29) UBRR UART Baud Rate Register
$08 ($28) ACSR Analog Comparator Control and Status Register
Table 1. AT90S2313 I/O Space(1) (Continued)
Address Hex Name Function
Bit 76543210
$3F ($5F) I THSVNZCSREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initialvalue00000000

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• Bit 5 – H: Half-carry Flag
The Half-carry Flag H indicates a Half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result after the different arithmetic and logic
operations. See the Instruction Set description for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result after the different arithmetic and logic opera-
tions. See the Instruction Set description for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the Instruc-
tion Set description for detailed information.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Stack Pointer – SP An 8-bit register at I/O address $3D ($5D) forms the Stack Pointer of the AT90S2313. 8
bits are used to address the 128 bytes of SRAM in locations $60 - $DF.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-
rupt Stacks are located. This stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when
data is pushed onto the stack with the PUSH instruction, and it is decremented by 2
when an address is pushed onto the stack with subroutine calls and interrupts. The
Stack Pointer is incremented by 1 when data is popped from the stack with the POP
instruction, and it is incremented by 2 when an address is popped from the stack with
return from subroutine RET or return from interrupt RETI.
Bit 76543210
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initialvalue00000000

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Reset and Interrupt
Handling
The AT90S2313 provides 10 different interrupt sources. These interrupts and the sepa-
rate Reset Vector each have a separate Program Vector in the program memory space.
All the interrupts are assigned individual enable bits that must be set (one) together with
the I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are automatically defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in Table 2. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 (the External
Interrupt Request 0), etc.
The most typical and general program setup for the Reset and Interrupt Vector
addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
$003 rjmp TIM_CAPT1 ; Timer1 Capture Handler
$004 rjmp TIM_COMP1 ; Timer1 Compare Handler
$005 rjmp TIM_OVF1 ; Timer1 Overflow Handler
$006 rjmp TIM_OVF0 ; Timer0 Overflow Handler
$007 rjmp UART_RXC ; UART RX Complete Handler
$008 rjmp UART_DRE ; UDR Empty Handler
$009 rjmp UART_TXC ; UART TX Complete Handler
$00a rjmp ANA_COMP ; Analog Comparator Handler
;
$00b MAIN: ldi r16,low(RAMEND); Main program start
$00c out SPL,r16
$00d <instr> xxx
…………
Table 2. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
1 $000 RESET Hardware Pin, Power-on Reset and
Watchdog Reset
2 $001 INT0 External Interrupt Request 0
3 $002 INT1 External Interrupt Request 1
4 $003 TIMER1 CAPT1 Timer/Counter1 Capture Event
5 $004 TIMER1 COMP1 Timer/Counter1 Compare Match
6 $005 TIMER1 OVF1 Timer/Counter1 Overflow
7 $006 TIMER0 OVF0 Timer/Counter0 Overflow
8 $007 UART, RX UART, RX Complete
9 $008 UART, UDRE UART Data Register Empty
10 $009 UART, TX UART, TX Complete
11 $00A ANA_COMP Analog Comparator

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Reset Sources The AT90S2313 has three sources of reset:
•Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (VPOT).
•External Reset. The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
•Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
During Reset, all I/O Registers are then set to their initial values, and the program starts
execution from address $000. The instruction placed in address $000 must be an RJMP
(Relative Jump) instruction to the reset handling routine. If the program never enables
an interrupt source, the Interrupt Vectors are not used, and regular program code can
be placed at these locations. The circuit diagram in Figure 23 shows the reset logic.
Table 3 defines the timing and electrical parameters of the reset circuitry.
Figure 23. Reset Logic
Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT
(falling).
The user can select the start-up time according to typical Oscillator start-up. The num-
ber of WDT Oscillator cycles used for each time-out is shown in Table 4. The frequency
of the Watchdog Oscillator is voltage-dependent, as shown in “Typical Characteristics”
on page 74.
Table 3. Reset Characteristics (VCC =5.0V)
Symbol Parameter Min Typ Max Units
VPOT(1) Power-on Reset Threshold Voltage (rising) 1.0 1.4 1.8 V
Power-on Reset Threshold Voltage (falling) 0.4 0.6 0.8 V
VRST RESET Pin Threshold Voltage –0.85 VCC V
tTOUT
Reset Delay Time-out Period
FSTRT Unprogrammed 11.0 16.0 21.0 ms
tTOUT
Reset Delay Time-out Period
FSTRT Programmed 0.25 0.28 0.31 ms

20 AT90S2313
0839I–AVR–06/02
Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. As
shown in Figure 23, an internal timer is clocked from the Watchdog Timer. This timer
prevents the MCU from starting until after a certain period after VCC has reached the
Power-on Threshold voltage (VPOT)(seeFigure24).TheFSTRTFusebitintheFlash
can be programmed to give a shorter start-up time if a ceramic resonator or any other
fast-start Oscillator is used to clock the MCU.
If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via
an external pull-up resistor. By holding the RESET pin low for a period after VCC has
been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a tim-
ing example of this.
Figure 24. MCU Start-up, RESET Tied to VCC.
Figure 25. MCU Start-up, RESET Controlled Externally
Table 4. Number of Watchdog Oscillator Cycles
FSTRT Time-out at VCC = 5V Number of WDT Cycles
Programmed 0.28 ms 256
Unprogrammed 16.0 ms 16K
VCC
RESET
TIME-OUT
INTERNAL
RESET
tTOUT
VPOT
VRST
VCC
RESET
TIME-OUT
INTERNAL
RESET
tTOUT
VPOT
VRST