Avago MC68HC11 Reference guide

1
Interfacing the MC68HC11 to the HCTL-2020
Application Brief M-023
Introduction
This application brief describes two interfaces for the
HCTL-2020 to the MC68HC11. One is a port interface and
the other is a bus interface.
;******************************************************************************
;THIS SUBROUTINE IS USED TO READ DATA FROM THE HCTL-2020 ;FOR THE PORT
INTERFACE.
;THE SUBROUTINE RETURNS THE 16 BIT DATA FROM THE HCTL-;2020 IN REGISTER IX.
;* DENOTES ACTIVE LOW SIGNALS.
;******************************************************************************
RD2020: PSHA ;SAVE REG A ON STACK.
PSHB
LDAA#00
STAA$1007 ;PUT PORT C IN INPUT MODE.
LDAA#0FA
STAA$1004 ;SEL LO AND OE* LO.
LDAA$1003 ;HIGH BYTE OF DATA IN REG. A.
LDAB#0FB
STAB$1004 ;SEL HI AND OE* LO.
LDAB$1003 ;LO BYTE IN REG. B.
XGDX ;REGISTER IX HAS THE 16 BIT VALUE FROM
;THE HCTL-2020
LDAA#0FF
STAA$1004 ;SEL HI AND OE* HI.
PULB ;RESTORE REG B FROM STACK.
PULA ;RESTORE REG A FROM STACK.
RTS
;******************************************************************************
;THIS SUBROUTINE IS USED TO RESET THE HCTL-2020 IN THE ;PORT INTERFACE.
;******************************************************************************
RST2020: PSHA
LDAA#0EF
STAA$1004 ;RST*LO.
LDAA#0FF
STAA$1004 ;RST*HI.
PULA
RTS
Port Interface
The connections are shown in Figure 1, the schematic
titled “Port Interface”. Port C is used to read the data in
and 3 pins on port B are used for the control signals to
the HCTL-2020. The E clock from the 68HC11E9 is used to
clock the HCTL-2020. In this interface it is assumed that
the 68HC11E9 is in the single chip mode.
The subroutines to read from the HCTL-2020 and to reset
the HCTL-2020 follow.

2
Figure 1. Port Interface Schematic.
PA3 31
XT
8
EX
7
RESET
17
IRQ
19
XIRQ
18
MODB
2
PA0
34
PA1
33
PA2
32
PE0
43
PE1
44
PE2
45
PE3
46
PE4
47
PE5
48
PE6
49
PE7
50
VRH
52
VRL
51
PA4 30
PA5 29
PA6 28
PA7 27
PB0 42
PB1 41
PB2 40
PB3 39
PB4 38
PB5 37
PB6 36
PB7 35
PC0 9
PC1 10
PC2 11
PC3 12
PC4 13
PC5 14
PC6 15
PC7 16
PD0 20
PD1 21
PD2 22
PD3 23
PD4 24
PD5 25
MODA 3
E5
AS 4
R/W 6
DO
1
2
SEL
3
OE
4
U/D
5
NC
6
RST
7
CHB
8
CHA
9
VSS
10
VDD 20
D1 19
D2 18
D3 17
CNTDCDR 16
CNTCAS 15
D4 14
D5 13
D6 12
D7 11
68HC11E9
U1
HCTL-2020
U2
Vcc
NOTE: 68HC11E9 IS IN THE SINGLE CHIP MODE.
REFER TO THE 68HC11E9 REFERENCE MANUAL FOR DETAILS.
5563-1
CLK

3
Bus Interface
In applications where the expanded-mode is already be-
ing used, it is convenient to use the bus interface to the
HCTL-2020. Figure 2,“Bus Interface Control Signals”, is the
schematic diagram to generate the control signals in the
expanded mode.
The subroutines to read and reset follow.
;******************************************************************************
;THIS SUBROUTINE READS A VALUE FROM THE HCTL-2020. THE HIGH ;BYTE OF DATA IS RE-
TURNED IN REG IY IN THE CORRECT ORDER OF ;HIGH AND LOW BYTES.
;THE TWO BYTES ARE MAPPED AT THE MEMORY LOCATIONS AT 0CFFOh ;AND 0CFF1h RE-
SPECTIVELY.
;******************************************************************************
H2020 EQU $0C000
RD2020: LDY H2020
RTS
;******************************************************************************
;THIS SUBROUTINE IS USED TO RESET THE HCTL-2020. THE RESET ;SIGNAL IS MAPPED TO
MEMORY LOCATION 0CFF2h.
;******************************************************************************
REST2020 EQU $0CFF2
RST2020: PSHA
LDAA REST2020;READ LOCATION $CFF2 TO CAUSE RESET
PULA
RTS

4
Figure 2. Bus Interface Control Signals.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007 AvagoTechnologies Limited. All rights reserved.
5964-3770E - February 7, 2007
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
OC
1
G
11
Q0 2
Q1 5
Q2 6
Q3 9
Q4 12
Q5 15
Q6 16
Q7 19
1
2
4
5
1
26
Y0 15
Y1 14
Y2 13
Y3 12
Y4 11
Y5 10
Y6 9
Y7 7
A
1
B
2
C
3
G1
6
G2A
4
G2B
5
U2
74HC138
E
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AS
74HC373
U1
U4A U6A
74HC20 74HC32
U3C
74HC00
U5
74HC30
U3D
74HC00
A15
A14
A13
A12
A11
A10
A9
A8 98
11 12
10
12
13
11
6
5
4
3
8
2
1
U3A
74HC00
U3B
74HC00
13
SEL
6
2
4
5
R/W
*
OE
*
RST
*
3
MC68HC11 BUS
NOTE: ALL
*
SIGNALS ARE ACTIVE LOW.
5563-2