IDT 89EBPES12N3 User manual

November 2006
6024 Silver Creek Valley Road, San Jose,California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2006 Integrated Device Technology,Inc.
IDT™89EBPES12N3
Evaluation Board Manual
(Eval Board: 18-597-001)

DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patentrights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analysis be performed.
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when properly used in accordance with instructions for use providedin the labeling, can be reasonably expected toresult in a significant injury to the user.
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Notes
EB12N3 Eval Board Manual (18-597-001) i November 2, 2006
Table of Contents
1 Description of the EB12N3 Eval Board
Introduction..................................................................................................................................1-1
Board Features............................................................................................................................1-2
Hardware............................................................................................................................1-2
Software.............................................................................................................................1-2
Other..................................................................................................................................1-2
Revision History...........................................................................................................................1-3
2 Installation of the EB12N3 Eval Board
EB12N3 Installation.....................................................................................................................2-1
Hardware Description..................................................................................................................2-1
Host System.......................................................................................................................2-1
Reference Clocks ........................................................................................................................2-3
Power Sources ............................................................................................................................2-4
External Power Source.......................................................................................................2-4
PCI Express Serial Data Transmit Termination Voltage Regulator.....................................2-4
PCI Express Digital Power Voltage Regulator....................................................................2-4
PCI Express Analog Power Voltage Regulator..................................................................2-4
Core Logic Voltage Regulator............................................................................................2-4
Required Jumpers..............................................................................................................2-4
Power Selection for Downstream Ports.......................................................................................2-5
Reset ...........................................................................................................................................2-6
Fundamental Reset............................................................................................................2-6
Downstream Reset.............................................................................................................2-6
Boot Configuration Vector............................................................................................................2-7
SMBus Interfaces ........................................................................................................................2-9
SMBus Slave Interface.......................................................................................................2-9
SMBus Master Interface...................................................................................................2-10
JTAG Header.............................................................................................................................2-12
Attention Buttons .......................................................................................................................2-12
LEDs..........................................................................................................................................2-12
PCI Express Connector.............................................................................................................2-13
Locations of Connectors, Jumpers, and Switches.....................................................................2-15
3 Software for the EB12N3 Eval Board
Introduction..................................................................................................................................3-1
Device Management Software.....................................................................................................3-1
4 Schematics
Schematics..................................................................................................................................4-1

IDT Table of Contents
EB12N3 Eval Board Manual (18-597-001) ii November 2, 2006
Notes

Notes
EB12N3 Eval Board Manual (18-597-001) iii November 2, 2006
List of Tables
Table 2.1 Clock Source Selection.....................................................................................................2-3
Table 2.2 Clock Frequency Selection...............................................................................................2-3
Table 2.3 Clock Spread Spectrum Selection....................................................................................2-3
Table 2.4 SMA Connectors - Onboard Reference Clock..................................................................2-3
Table 2.5 Power Connector Pin-Out.................................................................................................2-4
Table 2.6 Power Selection for Downstream Ports Jumpers, Headers..............................................2-5
Table 2.7 W13 Shunt Selection for Cold Reset................................................................................2-6
Table 2.8 W13 Shunt Selection for Warm Reset..............................................................................2-6
Table 2.9 Downstream Reset Selection ...........................................................................................2-7
Table 2.10 Boot Configuration Vector Signals....................................................................................2-7
Table 2.11 Boot Configuration Vector Switches.................................................................................2-8
Table 2.12 Slave SMBus Interface Connector....................................................................................2-9
Table 2.13 SMBus Slave Interface Address Configuration.................................................................2-9
Table 2.14 PES12N3 SMBus Slave Interface Address Setting........................................................2-10
Table 2.15 I/O Expander Address Setting........................................................................................2-11
Table 2.16 EEPROM SMBus Address Setting.................................................................................2-11
Table 2.17 Required EEPROM Headers..........................................................................................2-11
Table 2.18 JTAG Connector Pin Out................................................................................................2-12
Table 2.19 Attention Buttons ...........................................................................................................2-12
Table 2.20 LED Status Indicators.....................................................................................................2-12
Table 2.21 PCI Express Connector Pin-Out.....................................................................................2-13

IDT List of Tables
EB12N3 Eval Board Manual (18-597-001) iv November 2, 2006
Notes

Notes
EB12N3 Eval Board Manual (18-597-001) iii November 2, 2006
List of Figures
Figure 1.1 Functional Block Diagram of the EB12N3 Eval Board......................................................1-1
Figure 2.1 SuperMicro X6DH8-G2 Motherboard...............................................................................2-2

IDT List of Figures
EB12N3 Eval Board Manual (18-597-001) iv November 2, 2006
Notes

Notes
EB12N3 Eval Board Manual (18-597-001) 1 - 1 November 2, 2006
Chapter 1
Description of the EB12N3
Eval Board
Introduction
The 89HPES12N3 switch (also referred to as PES12N3 in this manual) is a member of IDT’s PCI
Express standard (PCIe) based line of products. It is a 3 port switch, with 4 serial lanes per port (x4). One
upstream port is provided for connecting to the root complex (RC), and two downstream ports areavailable
for connecting to PCIe endpoints or to another switch. More information on this device can be found in the
89HPES12N3 User Manual.
The 89EBPES12N3 Evaluation Board (also referred to as EB12N3 in this manual) provides an evalua-
tion platform for the PES12N3 switch. It is also a cost effective way to add a PCIe downstream port (x4) to
an existing system with a limited number of PCIe downstream ports. The EB12N3 eval board is designed to
function as an add-on card to beplugged into a x4 PCIe slot available on a motherboard hosting an appro-
priate root complex andmicroprocessor(s). The EB12N3 is a vehicle to test and evaluatethe functionality of
the PES12N3 chip, and it can also play an important role for customers to get a headstart on software
development while they await the arrival of their own hardware. It is also used inside IDT to reproduce
system level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block
diagram representing the main parts of the EB12N3 board.
Figure 1.1 Functional Block Diagram of the EB12N3 Eval Board
Voltages on board
+12 V
5 V
External Power
Connector
(optional)
+3.3 V
+1.5 V
+1.0 V
+
JTAG
Header
Main
Reset
I/O Expander
PCA9555
PCIe x4 Upstream Edge
24LC512
EPROM
SMBUS
HEADER
PES12N3
PCI Express
Switch
MIC2951B
Controller
Dual Power
PCIe x4 Downstream Slot
PCIe x4 Downstream Slot
x4
x4
x4
25 MHz
SSC Clock
Buffer
Clock
Fanout HCSL CLK
SMBus

IDT Description of the EB12N3 Eval Board Board Features
EB12N3 Eval Board Manual (18-597-001) 1 - 2 November 2, 2006
Notes Board Features
Hardware
PES12N3 PCIe 3 port switch
–Three x4 ports, 12 PCIe lanes
–PCIe Base Specification Revision 1.0a compliant
–48 Gbps aggregate switching capacity
–128 to 2048 byte maximum payload size
–Static lane reversal and polarity inversion supported on all lanes
–Automatic per port link width negotiation to x4, x2, x1
–Can load configuration from serial EEPROM via SMBUS
x4 PCIe Connectors
–One edge connector on the upstream port, to be plugged into a x4 slot on a host motherboard
–Two slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in
Numerous user selectable configurations set using onboard jumpers and DIP-switches
–Source of clock - host clock or onboard clock generator
–multiple clock rates and spread spectrum settings
–Boot mode selection
SMBUS Slave Interface (4 pin header)
SMBUS Master Interface connected to two optional Serial EEPROMs through I/O expander
–Facilitates testing with two different settings of initialization data witha simple changeof a jumper
–Only one EEPROM can be selectively connected to the SMBUS at a time
“Attention” button for each port to initiate a hot swap event on each port
4 pin connector for optional external power supply Push button for Warm Reset
Several LEDs to display status, reset, power, “Attention”, etc.
One 10 pin JTAG connector (pitch 2.54 mm x 2.54 mm)
Software
There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES12N3 within host systems
running popular operating systems.
Installation programs
–Operating Systems Supported: Windows2000, WindowsXP, Linux
GUI based application for Windows and Linux
–Allows users to view and modify registers in thePES12N3
–Binary file generator for programming the serial EEPROMs attached to the SMBUS
Other
A metal bracket is required to hold firmly in place the two endpoints plugged into the EB12N3 board.
An external power supply may be required under some conditions.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB12N3 board for specific test points.

IDT Description of the EB12N3 Eval Board Revision History
EB12N3 Eval Board Manual (18-597-001) 1 - 3 November 2, 2006
Notes Revision History
September 26, 2006: Initial publication of board manual.
November 2, 2006: Added footnote to Table 2.10 regarding default setting for switch mode pins.

IDT Description of the EB12N3 Eval Board Revision History
EB12N3 Eval Board Manual (18-597-001) 1 - 4 November 2, 2006
Notes

Notes
EB12N3 Eval Board Manual (18-597-001) 2 - 1 November 2, 2006
Chapter 2
Installation of the EB12N3
Eval Board
EB12N3 Installation
This chapter discusses the steps required to configure and install the EB12N3 evaluation board. All
available DIP switches and jumper configurations are explained in details.
The primary installation steps are:
1. Configure jumper/switch options suitable to the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on evaluation board.
3. Insert Evaluation Board into the host system (motherboard with root complex chipset).
4. Apply power to the host system.
The EB12N3 board is shipped with all jumpers and switches configured to their default settings, and in
general, they do not require further modification or setup.
Hardware Description
The PES12N3 is a 12lane, 3-port PCI Express switch. It is a peripheral chip that performs PCI Express
based switching with a feature set optimized for high performance x4 applications such as servers and
storage. It provides fan-out and switching functions between a PCI Express upstream port and two down-
stream ports or peer-to-peer switching between downstream ports.
The PES12N3 has two PCI Express x4 downstream ports accessible through two x4 connectors. Each
port is capable of negotiating a x1, x2, or x4 link width. All endpoint cards connected to the 89EBPES12N3
must support at least one of these link widths.
Basic requirements for the board to run are:
Host system with a PCI Express root complex supportingx4 configuration thougha PCI Express x4
slot.
x1, x2, or x4 PCI Express Endpoint Cards.
Host System
The evaluation board cannot be operated as a standalone unit. A host system implementing a PCI
Express root complex supporting x4 configuration through a PCI Express x4 slot is required to take full
advantage of the PES12N3’s capabilities. One such system is the SuperMicro X6DH8-G2 motherboard
equipped with an Intel E7520 chipset which was introduced in 2004 to deploy dual-processor server chipset
technology. The board has three PCI Express slots. All slots have x8 connectors. However, only two have a
x8 link width (J15 and J16). The remaining slot has a x4 link width. Refer to Figure 2.1 to identify the proper
connectors.

IDT Installation of the EB12N3 Eval Board Hardware Description
EB12N3 Eval Board Manual (18-597-001) 2 - 2 November 2, 2006
Notes
Figure 2.1 SuperMicro X6DH8-G2 Motherboard

IDT Installation of the EB12N3 Eval Board Reference Clocks
EB12N3 Eval Board Manual (18-597-001) 2 - 3 November 2, 2006
Notes Reference Clocks
The EB12N3 requires two differential reference clocks. The EB12N3 drives both of these clocks from a
common source. The source for the reference clock is user-selectable between the host system’s reference
clock and the onboard clock generator. Selection is made by stuffing resistors described in Table 2.1.
The source for the onboard clock is the ICS557-03 clock generator device (U9) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB12N3 allows selection between multiple
clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively.
Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak
energy over a wider bandwidth.
The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.4. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.
Clock Configuration Stuffing Option
Install Clock Source
R79, R81 Onboard Reference Clock – Use onboard clock generator
R75, R78 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection
Clock Frequency Switch - J8[2:1]
J8[2] J8[1] Clock Frequency
OFF OFF <Reserved>
OFF ON 125 MHz
ON OFF 100 MHz (Default)
ON ON <Reserved>
Table 2.2 Clock Frequency Selection
Clock Spread Spectrum Switch - J8[4:3]
J8[4] J8[3] Spread%
OFF OFF No Spread (Default)
OFF ON Down -0.75
ON OFF Down -0.50
ON ON Center ±0.25
Table 2.3 Clock Spread Spectrum Selection
Onboard Reference Clock Output (Differential) – J3, J7
J3 Positive Reference Clock
J7 Negative Reference Clock
Table 2.4 SMA Connectors - Onboard Reference Clock

IDT Installation of the EB12N3 Eval Board Power Sources
EB12N3 Eval Board Manual (18-597-001) 2 - 4 November 2, 2006
Notes Power Sources
The EB12N3 and all attached endpoint cards are powered entirely by the host system through the
upstream PCI Express edge connector. In general, this is sufficient and there is no need for an external
power-source. If the combined power requirements of the EB12N3 Evaluation Board and the devices
attached to the two downstream ports exceed PCI Express specifications, an external source may be
required to supply the necessary power.
External Power Source
If necessary, external power is supplied to the EB12N3 board through a 4-pin auxiliary power connector
attached to J5. The external power supply provides +12V and +5.0V to the EB12N3 as described in Table
2.5. The +5V is unused.
.
PCI Express Serial Data Transmit Termination Voltage Regulator
A low-voltage, low-dropout regulator (Micrel MIC49300BR) provides a 1.5V PCI Express serial data
transmit termination voltage to the PES12N3.
PCI Express Digital Power Voltage Regulator
A low-voltage, low-dropout regulator (Micrel MIC49300BR) provides a 1.0V PCI Express digital power
voltage to the PES12N3.
PCI Express Analog Power Voltage Regulator
A low-voltage, low-dropout regulator (Micrel MIC49300BR) provides a 1.0V PCI Express analog power
voltage to the PES12N3.
Core Logic Voltage Regulator
The EB12N3 employs three low-voltage, low-dropoutvoltage regulators (Micrel MIC49300BR) to supply
the 1.0V core voltage to the PES12N3 switch.
Required Jumpers
To deliver power to thePES12N3 switch, the following jumpers must be shunted: W10, W22-W25.
4-Pin Power Connector – J5
Pin Signal
1+12V
2GND
3GND
4+5V
Table 2.5 Power Connector Pin-Out

IDT Installation of the EB12N3 Eval Board Power Selection for Downstream Ports
EB12N3 Eval Board Manual (18-597-001) 2 - 5 November 2, 2006
Notes Power Selection for Downstream Ports
The following table illustrates the power selection features and hot plug capabilities for downstream
ports B and C.
Power Selection for Downstream Ports Jumpers, Headers
Ref. Designator Type Default Description
J2[6] Switch On On - Downstream clock for port B is always enabled
Off - Setting for hot plugging - Downstream clock for port B is
controlled byMIC2591B, which is controlled by the 12N3
J2[7] Switch On On - Downstream clock for port C is always enabled
Off - Setting for hot plugging - Downstream clock for port C is
controlled byMIC2591B, which is controlled by the 12N3
W6 Header Shunted Shunted - Hot Plug disabled, enables direct power to down-
stream port C
Open - Downstream port C power will be controlled by power
enable signal (Refer to schematic page 5 C7)
W11 Header Shunted Shunted - Hot Plug disabled, enables direct power to down-
stream port B
Open - Downstream port B power willbe controlled by power
enable signal (Refer to schematic page 5 C7)
W7 3 pin
Header [1-2] shunted [1-2]Select onboard (+12V) to Port B
[2-3]Select external power (+12V) to Port B
Note: External Power Connector has to be attached at J5.
W8 3 pin
Header [1-2] shunted [1-2]Select onboard (+3.3V) to Port B
[2-3]Select external power (+3.3V) to Port B
Note: External Power Connector has to be attached at J5.
W9 3 pin
Header [1-2] shunted [1-2]Select onboard (+12V) to Port C
[2-3]Select external power (+12V) to Port C
Note: External Power Connector has to be attached at J5.
W12 3 pin
Header [1-2] shunted [1-2]Select onboard (+3.3V) to Port C
[2-3]Select external power (+3.3V) to Port C
Note: External Power Connector has to be attached at J5.
Table 2.6 Power Selection for Downstream Ports Jumpers, Headers

IDT Installation of the EB12N3 Eval Board Reset
EB12N3 Eval Board Manual (18-597-001) 2 - 6 November 2, 2006
Notes Reset
The PES12N3 supports two types of reset mechanisms as described in the PCI Express specifications:
Fundamental Reset: This is a system generatedreset that propagates along the PCI Express tree
through a single side-band signal PERST#, connected to the Root Complex, the PES12N3 and the
endpoints.
Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Resetmaybeinitiated bysoftware.Thisis further discussedin the89HPES12N3User
Manual. The EB12N3 evaluation board does not need to doanything specific to support Hot Reset.
Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB12N3 evaluation board. Both
types of resets depend on the location of the shunt on header W13. Refer to the tables below:
Cold Reset:
Warm Reset: This is triggered by hardware while the device is powered on.
Downstream Reset
The PES12N3 provides three different downstream reset schemes. By default the reset scheme used is
the fundamental reset. There is also a software controlled reset for each downstream port through the
GPIO pins. Finally, there is a pgood controlled reset for each downstream port. When hot plugging is
enabled, this reset scheme creates a downstream port reset if pgood_ _N is not asserted. Selection of the
downstream reset is made by shunting different header pins as described in Table 2.9.
W13 Shunt Selection for Cold Reset
Shunt Description
Pins [1-2] During initial power-on, the onboard voltage monitor (TLC7733D) will assert
the PCI Express Reset (PERSTN) input pin of the PES12N3.
Pins [2-3] During initial power-on, the reset signal (PERSTN) will come from the
upstream edge connector.
Table 2.7 W13 Shunt Selection for Cold Reset
W13 Shunt Selection for Warm Reset
Shunt Description
Pins [1-2] A warm reset can be initiated in two ways. Both events cause the onboard
voltage monitor (TLC7733D) to assert the PCI Express Reset (PERSTN)
input of the PES12N3 while the power is on. The two ways are:
–by pressing a push-button switch (X4) located on EB12N3 board
–if the system board IO Controller Hub asserts PERST# signal, which
propagates through the PCIe upstream edge connector of the EB12N3
Pins [2-3] This will directly tie the upstream reset to the onboard fundamental reset.
Table 2.8 W13 Shunt Selection for Warm Reset

IDT Installation of the EB12N3 Eval Board Boot Configuration Vector
EB12N3 Eval Board Manual (18-597-001) 2 - 7 November 2, 2006
Notes
Boot Configuration Vector
A Boot Configuration Vector consisting of the signals listed in Table 2.10 is sampled by the PES12N3
during a fundamental reset (while PERSTN is active). The Boot Configuration Vector defines the essential
parameters for switch operation and is set using DIP Switches J1 and J2 as defined in Table 2.11
Port# Header Selection
B J11 [1-2] PGOOD_B_N controlled reset (used when hot-plugging is enabled)
[3-4] Software controlled reset through GPIO0
[5-6] Fundamental reset PERST# (default)
C J12 [1-2] PGOOD_C_N controlled reset (used when hot-plugging is enabled)
[3-4] Software controlled reset through GPIO1
[5-6] Fundamental reset PERST# (default)
Table 2.9 Downstream Reset Selection
Boot Configuration Vector Signals
Signal Description
CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream
ports are using the same clock source as that provided to downstream devices. This
pinisused astheinitial valueoftheSlotClock Configuration bitinallofthe LinkStatus
Registers for downstream ports. The value may be overridden by modifying the SCLK
bit in the PB_PCIELSTS or PC_PCIELSTS register. Default: 0x1
CCLKUS Common Clock Upstream. The assertion of this pin indicates that the upstream port
is using the same clock source as the upstream device. This pin is used as the initial
value of the Slot Clock Configuration bit in the Link Status Register for the upstream
port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS
register. Default: 0x1
MSMBSMODE Master SMBus Slow Mode. Theassertionof thispinindicatesthat the masterSMBus
should operate at 100 KHz instead of 400 kHz. Default: 0x0
PEALREV PCI Express Port A Lane Reverse. When this pin is asserted, the lanes of PCI
Express Port A are reversed. This value may be overridden by modifying the value of
the PALREV bit in the PA_SWCTL register. Default: 0x0
PEBLREV PCI Express Port B Lane Reverse. When this pin is asserted, the lanes of PCI
Express Port B are reversed. This value may be overridden by modifying the value of
the PBLREV bit in the PA_SWCTL register. Default: 0x0
PECLREV PCI Express Port C Lane Reverse.When this pin is asserted, the lanes of PCI
Express Port C are reversed. This value may be overridden by modifying the value of
the PCLREV bit in the PA_SWCTL register.Default: 0x0
REFCLKM PCI Express Reference Clock Mode Select. These signals select the frequency of
the reference clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
Table 2.10 Boot Configuration Vector Signals (Part 1 of 2)

IDT Installation of the EB12N3 Eval Board Boot Configuration Vector
EB12N3 Eval Board Manual (18-597-001) 2 - 8 November 2, 2006
Notes
RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the
PES12N3 executes the reset procedure and remains in a reset state with the Master
and Slave SMBusesactive. This allows software to read and write registers internal to
the device before normal device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the PA_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the PA_SWCTL regis-
ter.Default: 0x0
SWMODE[3:0] Switch Mode. These configuration pins determine the PES12N3 switch operating
mode. Default1: 0x0
0x0 - Initialization without serial EEPROM
0x1 - Serial EEPROM-based initialization
0x2 through 0x5 - Reserved
0x6 - Scan test mode (factory use only)
0x7 - PLL Bypass test mode
0x8 - 10-bit loop-back test mode
0x9 - Reserved
0xA - Internal pseudo random bit stream self-test mode
0xB - External pseudo random bit stream self-test mode
0xC -Reserved
0xD - SerDes broadcast test mode
0xE - Reserved
0xF - Reserved
1. The default setting is 0x1 if the PES12N3A device is on the board.
Boot Configuration Vector Switches J1 & J2 (ON=0, Off=1)
Switch BCV Bit Default
J1[1] CCLKDS OFF
J1[2] CCLKUS OFF
J1[3] MSMBSMODE ON
J1[4] PEALREV ON
J1[5] PEBLREV ON
J1[6] PECLREV ON
J1[7] REFCLKM ON
J1[8] RSTHALT ON
J2[1] <RESERVED> ON
J2[2] SWMODE[0] ON
J2[3] SWMODE[1] ON
Table 2.11 Boot Configuration Vector Switches (Part 1 of 2)
Boot Configuration Vector Signals
Signal Description
Table 2.10 Boot Configuration Vector Signals (Part 2 of 2)