AWINIC AW21009 User manual

AW21009
Jul. 2021 V1.1
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9 MULTI-FUNCTION LED DRIVER WITH I2C INTERFACE
FEATURES
9-channel RGB LED Driver
Global 256-levels DC current configuration
Individual 4096-levels PWM for dimming
Individual 256-levels current for color-mixing
Dither function
High-precision current sinks
Device-to-device error: ±5%
Channel-to-channel error: ±5%
EMI and audible noise reduction
Phase delay and phase inverting scheme
Slew rate control function
Flexible LED lighting pattern control
LED open/short detection per channel
Auto power save mode when all LEDs off > 32ms
Under voltage lock out and over temperature
protection
1MHz I2C interface, 4 selectable addresses: 20h,
21h, 24h, 25h
Power supply: 2.7V~5.5V
QFN 3mmX3mmX0.75mm-20L package
APPLICATIONS
Cell Phone
Keyboard
PDA/MP3/MP4/CD/Mini display
Smart home appliance
GENERAL DESCRIPTION
AW21009 is a 9-channel multi-function LED driver.
Each channel has individual 8-bit DC current setting
for color-mixing and maximum 12-bit PWM
resolution for brightness control. The global current
of each channel is recommended to be 40mA
configured via register and external Resistor REXT.
Group control mode, autonomous breathing pattern
and rapid RGB control mode are provided for
flexible, high efficiency lighting effect programming
and fast display updating.
Programmable phase-shifting and spread spectrum
technology are utilized to reduce EMI and audible
noise caused by MLCC when LEDs turn on or off
simultaneously.
AW21009 can be turned off with minimum current
consumption by either pulling the EN pin low or
using the software shutdown feature.
AW21009 is available in QFN 3mmX3mmX
0.75mm-20L package. It operates from 2.7V to 5.5V
over the temperature range of -40°C to +85°C.
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TYPICAL APPLICATION CIRCUIT
RB
RG
RR
RB
RG
RR
Note1: The resistorRR/RG/RBare only thermal reduction. And they aredetermined by VLED, VF ofLED, VDROPOUT of LEDx and
ILED. RX=(VLED-VFX-VDROPOUT)/ILED.
Note2: The resistorR1 and R2are equal to 4.7kΩat 400kHz I2C, at 1MHz I2C R1 and R2are equal to 1kΩ.
C3
1μF
VLED
EN
VIO
SCL
SDA
R2
4.7kΩ
MCU
AW21009
LED9
LED8
LED7
C1
1μF
LED3
LED2
LED1
GND
ISET
C2
0.1μF
R1
4.7kΩ
AD0
REXT
4kΩ
AD1
VCC
VCC 10
9
8
4
3
2
16
15
14
19
18
17
20
21
Figure 1 AW21009 Application Circuit
PIN CONFIGURATION AND TOP MARK
SL5G
XXXX
AW21009QNR Marking
(Top View)
SL5G –AW21009QNR
XXXX - Production TracingCode
21
GND
NC
LED1
LED2
LED3
LED4
AD1
AD0
NC
NC
NC
ISET EN SCL SDA VCC
LED5 LED6 LED7 LED8 LED9
1
2
3
4
5
6 7 8 9
10
15
14
13
12
11
20 19 18 17 16
AW21009QNR
(Top View)
Figure 2 Pin Configuration and Top Mark
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PIN DEFINITION
No.
NAME
DESCRIPTION
1
NC
Not connected.
2~10
LED1~LED9
Constant current sink, connect to LED’s cathode.
11~13
NC
Not connected.
14
AD0
I2C interface device address, connects to GND, VCC for different device
address of I2C.
15
AD1
I2C interface device address, connects to GND, VCC for different device
address of I2C.
16
VCC
Power supply: 2.7V~5.5V.
17
SDA
Serial data I/O for I2C interface.
18
SCL
Serial clock input for I2C interface.
19
EN
Shutdown the chip when pulled low.
20
ISET
When REXT=4.0kΩ, global current of LED is 40mA.
21
GND
Ground.
FUNCTIONAL BLOCK DIAGRAM
SDA
I2C
POR
SCL LED2
LED9
AD0
OTP
UVLO
VCC
BRx
SLx
OSC
LED1
AD1
GND
Open/Short
Detect
GCC
LED
DRIVER
Digital
Control
PWM
Modulation
BG
Phase
Control
EN
ISET
Global Current
Setting
Figure 3 Functional Block Diagram
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TYPICAL APPLICATION CIRCUITS
EN
VIO
SCL
SDA
R2
4.7kΩ
MCU
AW21009
LED9
LED8
LED7
C1
1μF
LED3
LED2
LED1
GND
ISET
C2
0.1μF
R1
4.7kΩ
RLED
RLED
RLED
RLED
RLED
RLED
Note1: The resistorRLED is only thermal reduction, and it is determined by VLED, VF ofLED, VDROPOUT of LEDx
and ILED. RLED=(VLED-VF-VDROPOUT)/ILED.
Note2: The resistorR1 and R2are equal to 4.7kΩat 400kHz I2C, at 1MHz I2C R1 and R2are equal to 1kΩ.
AD0
REXT
4kΩ
AD1
VCC
VCC
C3
1μF
VLED
10
9
8
4
3
2
16
15
14
19
18
17
20
21
Figure 4 Typical Application Circuit
RB
RG
RR
RB
RG
RR
Note1: The resistorRR/RG/RBare only thermal reduction. And they are determined by VLED, VF ofLED, VDROPOUT of LEDx and
ILED. RX=(VLED-VFX-VDROPOUT)/ILED.
Note2: The resistorR1 and R2are equal to 4.7kΩat 400kHz I2C, at 1MHz I2C R1 and R2are equal to 1kΩ.
C3
1μF
VLED
EN
VIO
SCL
SDA
R2
4.7kΩ
MCU
AW21009
LED9
LED8
LED7
C1
1μF
LED3
LED2
LED1
GND
ISET
C2
0.1μF
R1
4.7kΩ
AD0
REXT
4kΩ
AD1
VCC
VCC 10
9
8
4
3
2
16
15
14
19
18
17
20
21
Figure 5 Typical Application Circuit (RGB)
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ORDERING INFORMATION
Part Number
Temperature
Package
Marking
Moisture
Sensitivity Level
Environmental
Information
Delivery
Form
AW21009QNR
-40°C ~85°C
QFN 3X3-20L
SL5G
MSL1
ROHS+HF
6000 units/
Tape and Reel
ABSOLUTE MAXIMUM RATINGS(NOTE1)
PARAMETERS
RANGE
Supply voltage range VCC
-0.3V to 6V
Input voltage range
SCL, SDA, EN, AD0, AD1
-0.3V to VCC
Output voltage range
LED1~LED9
-0.3V to VCC
Junction-to-ambient thermal resistance θJA
47°C/W
Operating free-air temperature range
-40°C to 85°C
Maximum operating junction temperature TJMAX
150°C
Storage temperature TSTG
-65°C to 150°C
Lead temperature (soldering 10 seconds)
260°C
ESD (NOTE 2)
HBM
±2000V
CDM
±1500V
Latch-Up
Test condition: JESD78D
+IT：200mA
-IT：-200mA
NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the ranges
listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for prolonged
periods may affect device reliability.
NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: MIL-STD-883J Method 3015.9 EIA/JESD22-C101F(CDM)
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ELECTRICAL CHARACTERISTICS
TA=25°C, VCC=3.6V (unless otherwise noted), REXT=4KΩ, PWMRES=8bit..
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Power supply voltage and current
VCC
Power supply voltage
2.7
5.5
V
ISD_VCC
Shutdown current of VCC
VEN=GND
0.1
1
μA
ISTB_VCC
Standby current of VCC
VEN=3.6V,CHIPEN=0
3
10
μA
Power-save mode current
consumption
VEN=3.6V, GCR.APSE=1,
All LEDs off >32ms
3
10
μA
IACT_VCC
Quiescent current in active
mode
VEN=VCC,
GCR.CHIPEN=1
2
4
mA
VEN=VCC,
Iout=20mA per LEDx
8
10
mA
ILEAKAGE
Output leakage current
VEN=0V,
VLEDX=5.5V
0.1
1
μA
IMAX
Maximum global current of
LEDX
GCCR.GCC=0xFF,
BRX=COLX=0xFF
38
40
42
mA
IMATCH
Output current match
accuracy
GCCR.GCC=0xFF,
SLX= BRx =0XFF
-5
5
%
VDROPOUT
Dropout voltage when the
LED current has dropped
5%
ILEDX=20mA
70
100
150
mV
ILEDX=40mA
100
120
200
mV
ILEDX=60mA
150
180
300
mV
FOSC
OSC clock frequency
14.88
16
17.12
MHz
TSD
Thermal shutdown
threshold
165
°C
Thermal shutdown
hysteresis
25
°C
AD0,AD1, EN
VIL
Input low level
EN
0.4
V
VIH
Input high level
EN
1.4
V
VIL
Input low level
AD0,AD1
0.3*VCC
V
VIH
Input high level
AD0,AD1
0.7*VCC
V
RENPD
Internal pull down
resistance
EN
1M
Ω
I2C Interface
VOL
Output low level
SDA,IOL = 10 mA
0.1
V
VIH
Input high level
SCL, SDA
1.2
V
VIL
Input low level
SCL, SDA
0.4
V
I2C INTERFACE TIMING
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PARAMETER
FAST MODE
FAST MODE PLUS
UNIT
MIN
MAX
MIN
MAX
FSCL
Interface clock frequency
-
400
-
1000
kHz
THD:STA
(Repeat-start) START condition hold
time
0.6
-
0.26
-
μs
TLOW
Low level width of SCL
1.3
-
0.5
-
μs
THIGH
High level width of SCL
0.6
-
0.26
-
μs
TSU:STA
(Repeat-start) START condition setup
time
0.6
-
0.26
-
μs
THD:DAT
Data hold time
0
-
0
-
μs
TSU:DAT
Data setup time
0.1
-
0.05
-
μs
TR
Rising time of SDA and SCL
-
0.3
-
0.12
μs
TF
Falling time of SDA and SCL
-
0.3
-
0.12
μs
TSU:STO
STOP condition setup time
0.6
-
0.26
-
μs
TBUF
Time between start and stop
condition
1.3
-
0.5
-
μs
SDA
SCL
tBUF tLOW
tHD:STA tHD:DAT
tRtHIGH tF
tSU:DAT
Stop Start Start
tSU:STA
VIL
VIH
VIL
VIH
tSU:STOStop
Figure 6 I2C Interface Timing
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DETAILED FUNCTIONAL DESCRIPTION
OVERVIEW
AW21009 is a 9 channel multi-function LED driver. Each channel has individual 8-bit DC current setting for
color-mixing and maximum 12-bit PWM resolution for brightness control. The global current of each channel
is recommended to be 40mA configured via register and external Resistor REXT.
Phase-control, spread spectrum technology and slew rate control are utilized to reduce EMI and audible noise
caused by MLCC. Output current of each LED can be controlled by one pattern or be configured independently.
The integrated pattern controller provides breathing or group dimming control. The breathing mode includes
auto breathing and manual control mode. All breathing parameters are configurable including rising/falling
slope, on/off time, repeat times and brightness.
AW21009 can be turned off with minimum current consumption by either pulling the EN pin low or using the
software shutdown feature.
OPERATION MODE AND RESET
RESET
Power On Reset
Upon initial power-up, the AW21009 is reset by internal power-on-reset, and all registers are reset to default
value, and the chip is shut down.
Once the supply voltage VCC drops below the threshold voltage VPOR(2.0V), the power-on-reset will reset the
chip again. By reading the bit PUST of the register UVCR (address 60h), whether the chip has been reset can
be detected.
When the VCC ramps up above the threshold voltage VPOR (2.0V) and EN is ‘1’, POR is pulled high, meanwhile
the chip enters into initialization mode. The chip needs about 2ms to load the OTP information in initialization
mode. After initialization, it works in lower-power mode. About 200μs delay is required after CHIPEN is pulled
up, otherwise, internal OSCCLK may work incorrectly. Only in low-power and active mode, registers could be
configured. The recommended operation timing is shown as bellow.
VCC
POR
CHIPEN
OSC
Initialization
initial
Standby Active
200μs
EN
..
2ms
Shutdown
INITIAL
MODE
Note: Thechip needs about 2ms for
initalization after power on
(bit CHIPEN of GCR register)
Note: Recommend CHIPEN=1 after Initial
Note: OSC operates stable,which needs
200μs after CHIPEN=1
Internal registers are configurable
Configuring
Time
Figure 7 Power On Timing
Software Reset
By writing 00h to register RESET (address 70h), the software reset is triggered. Then all registers will be reset
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to the default value and the chip enters into initialization mode.
After the software reset command is input by I2C, it needs to wait at least 2ms before any other I2C commands
are accepted.
VCC
POR
CHIPEN
OSC
Initialization
initial
Standby Active
200μs
EN
..
2ms
Shutdown
INITIAL
MODE
Note: Thechip needs about 2ms for
initalization after power on
(bit CHIPEN of GCR register)
Note: Recommend CHIPEN=1 after Initial
Note: OSC operates stable,which needs
200μs after CHIPEN=1
Internal registers are configurable
Configuring
Time
Figure 8 Software Reset Timing
OPERATING MODE
Shutdown mode
The AW21009 enters into shutdown mode automatically when EN is pulled to low. In this situation, I2C interface
is not accessible, all registers will be reset and can not be configured.
Initialization mode
If EN is high, the AW21009 enters into initialization mode. During this period, all registers will be reset and chip
starts loading efuse information automatically.
Standby mode
After initialization, the AW21009 enters into standby mode when the bit CHIPEN of the register GCR (address
20h) is ‘0’, or UVLO is triggered in active mode. In this mode, only POR and I2C circuits work. I2C interface is
accessible, and all registers can be configured now.
Active mode
The AW21009 enters into active mode when EN is high and the bit CHIPEN of the register GCR (address 20h)
is ‘1’.
Power save mode
In active mode, when the bit APSE of the register GCR (address 20h) is set to “1”, the auto power-save function
is enabled. When all LEDs are switched off and the value of all registers BR00L~BR08H are 00h and write
00h to register UPDATE(address 45h) for more than 32ms, AW21009 automatically enters into power saving
mode. In power save mode, most analog blocks are disabled to minimize power consumption, but the registers
retain the data and keep it available via I2C. Once writing a non-zero value into any register among
BR00L~BR08H, the chip exits power-save mode immediately.
Thermal shutdown
The AW21009 enters the thermal shutdown mode when the junction temperature exceeds 165°C (typical)
automatically. In this mode, all the LEDx outputs are shut down. If the junction temperature decreases below
140°C (typical) and write ‘1’ to bit CHIPEN of the register GCR (address 20h), the AW21009 returns to active
mode.
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Initialization
Standby
Active
Software reset
CHIPEN=1
EN = H
Active mode
CHIPEN=0
Shutdown EN = LFrom all modes
VCC power on
Thermal Shutdown
OTST=1
OTST=0 &
CHIPEN=1
Power Save APSE=0 or
Write a non-zero value
to register BRx
APSE=1 &&
All LEDs off > 32ms
Figure 9 AW21009 operating mode transition
FEATURE DESCRIPTION
CURRENT SETTING
The average output current of LEDx (x=1~9) can be expressed by the following formula,
𝑰𝑶𝑼𝑻(𝒙) = 𝑰𝑴𝑨𝑿 ×𝑮𝑪𝑪
𝟐𝟓𝟓 ×𝑺𝑳𝒙 𝟐𝟓𝟓 ×𝑩𝑹𝒙 𝟐𝑷𝑾𝑴𝑹𝑬𝑺 𝒙 = 𝟏~𝟗
Where IMAX=40mA, GCC is the 8bit global current configured by the register GCCR (address 58h), SL is 8bit
individual constant current parameter configured by the register SLx (address 46h~4Eh) , PWMRES is
8bit/9bit/12bit PWM resolution configured by the register GCR (address 20h), and BR is 8bit/9bit/12bit
individual PWM modulated current parameter configured by the register BRxL/BRxH (address 21h~32h).
PWM MODULATION
Dither Function
When PWMRES[1:0] of GCR(address 20h) is 2’b11, dither function is enabled. Then the final output PWM has
the frequency equal to 9 bits and resolution equal to 12 bits. It achieved by 9 bits PWM modulation and 3bits
digital dither control. For 3-bit dither, every PWM in the 8 PWM group can be added one LSB or not according
to the 8-bit digital dither timing.
PWM Frequency
The output PWM frequency is decided by bits CLKFRQ [2:0] and PWMRES[1:0] in register GCR (address
20h). Following table shows the relationship of PWM frequency, the CLKFRQ [2:0] and PWMRES[1:0]. To
avoid the MLCC audible noise, it’s recommended to use the PWM frequency lower than 500 Hz or higher than
20kHz.
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BR Resolution
CLKFRQ[2:0]
000
001
010
011
100
101
110
111
8bit
62k
32k
4k
2k
1k
500
244
122
9bit
32k
16k
2k
1k
488
244
122
-
12bit
4k
2k
244
122
-
-
-
-
9bit+3bit dither
32k
16k
2k
1k
488
244
122
-
PWM Phase Control
To reduce the peak load current and ceramic-capacitor audible ringing, AW21009 supports 3 PWM phase
shifting (Phase1~Phase3) and phase-inverting scheme. When setting PDE in register PHCR (address 59h) to
‘1’, the phase shifting scheme is enabled, and each adjacent phase differs by 60 degrees, which meaning only
3 of 9 LEDs could switch on in the same time.
Phase1
LED1~LED3
Phase2
LED4~LED6
Phase3
LED7~LED9
π/3
2π/3
0
Figure 10 Phase shift scheme
When setting PINVTEn in register PHCR (address 59h, n=0~2) to ‘1’, the PWM phase of the even-numbered
channels is inverted. As shown below, if setting PINVTEn to ‘1’, the even-numbered channels are rotated 180
degrees counterclockwise when the odd-numbered channels are not, which is good for reducing the input-
current ripple. For an example, when setting PINVTE0 to ‘1’, the channel of LED2 are rotated 180 degrees
counterclockwise while the channels of LED1, LED3 are not.
PINVTEn=”1”
LED[1,3,5,7,9 ]
LED[2,4,6,8 ]
PINVTEn=”0”
LED[1,3,5,7,9]
LED[2,4,6,8 ]
Figure 11 Phase invert scheme
PWM Disable
If the bits DCPWM[1:0] in register SSCR (address 5Fh) is set to “11”, the PWM output is disabled, and the duty
of each PWM is forced to 100%. In this mode, the BRx parameter is not valid, but the SLx parameter is still
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effective.
It should be noted that when performing open-short detection, the bits DCPWM [1:0] need to be set to “11”.
GROUP CONTROL MODE
AW21009 supports group control mode, in this mode, all selected LEDs are controlled by the group control
registers (GSLR, GSLG, GSLB). The register GCFG select which LEDs are controlled by group control register.
There are total 3 control bit (GEx), each bit set adjacent 3 LED are included in or not. User can configure group
control register to setting common brightness and color for all selected LED, so as to simplify lighting effect
programming and speed up display refreshing via I2C interface.
If bit GSLDIS in register GCFG (address 8Bh) is ‘1’, the color parameters of the grouped LED are no longer
configured by register GSLR/G/B but by individual register (SL0~SL08).
The detailed configurations are as follows.
LED
GE
Brightness
Color
GE=0
GE=1
GE=0 or
GSLDIS=1
GE=1 and
GSLDIS=0
1
GCFG[0]
BR00
GBR
SL00
GSLR
2
BR01
GBR
SL01
GSLG
3
BR02
GBR
SL02
GSLB
4
GCFG[1]
BR03
GBR
SL03
GSLR
5
BR04
GBR
SL04
GSLG
6
BR05
GBR
SL05
GSLB
7
GCFG[2]
BR06
GBR
SL06
GSLR
8
BR007
GBR
SL07
GSLG
9
BR08
GBR
SL08
GSLB
Note: GBR={GBRH,GBRL}.
SPREAD SPECTRUM
PWM is a troublesome for some application which is concerned about EMI. AW21009 has spread spectrum
function to optimize the EMI performance. If bit SSE in register SSCR (address 5Fh) is set to ‘1’, spread
spectrum function is enabled. By setting the bit SSR in register SSCR, four spread spectrum range
±5%/±15%/±25%/±35% can be selected. The total electromagnetic emitting energy can spread into a wider
range of frequency band that significantly degrades the peak energy of EMI.
RGB CONFIGURE MODE
In RGB applications, every 3 LEDs in RGB share a same BR parameter. To achieve fast register configuration
for RGB applications, AW21009 provides an RGB configuration mode by setting the bit RGBMD in register
GCR2 (address 61h).
If RGBMD=1, register BR00~BR02 configure brightness parameters for corresponding 3 RGB groups . In other
words, in RGB mode, only registers BR00~BR02 need to be configured, and the registers BR03~BR08 are
not valid any more.
If RGBMD=0, register BR00~BR08 configure brightness parameters for corresponding 9 LEDs independently,
more details as follows.
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LED
BR parameter source
RGBMD=0
RGBMD=1
1
BR00
BR00
2
BR01
3
BR02
4
BR03
BR01
5
BR04
6
BR05
7
BR06
BR02
8
BR07
9
BR08
Note: BRxx = {BRxxH,BRxxL}
SINGLE BYTE CONFIGURATION MODE
By default, every LED has a 12bit BR parameter with BRxxL and BRxxH. The effective bit of BRxxH is 4bit.
However, AW21009 provides an single byte configuration mode by setting the bit SBMD in register GCR2
(address 61h). In single byte applications, every LED has a 8bit BR parameter configured by BR00L~BR04L.
It is worth noting that the effective bit of BRxxH(xx is 00~04) is 8 bit in single byte mode compared with default
mode. More details are as follows.
LED
BR parameter source
SBMD=0
SBMD=1
1
{BR00H,BR00L}
BR00L
2
{BR01H,BR01L}
BR00H
3
{BR02H,BR02L}
BR01L
4
{BR03H,BR03L}
BR01H
5
{BR04H,BR04L}
BR02L
6
{BR05H,BR05L}
BR02H
7
{BR06H,BR06L}
BR03L
8
{BR07H,BR07L}
BR03H
9
{BR08H,BR08L}
BR04L
PATTERN CONTROLLERS
There is a breathing pattern controller in the chip. When bit PATE in register PATCFG (address 80h) is set to
‘1’, breathing pattern controller is enabled. Pattern controller can be configured as autonomous breathing mode
or manual-controlled mode. When corresponding GE is configured as ‘1’, if in pattern controlled mode, each
led group (consisting of three adjacent LEDs) can enter into breathing mode. When GE is ‘0’, the three adjacent
LEDs exit breathing mode directly. For example, when setting GCFG = 0x01 and in pattern controlled mode,
LED1~LED3 will work in breathing mode and other LEDs will work in default mode.
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Autonomous Breathing Mode
When bit PATE and PATMD in register PATCFG are set to ‘1’, the pattern controller works in autonomous
breathing mode. In this mode, the pattern controller will generate a breathing lighting effect, which is configured
by the user-defined timing parameter. The waveform of the breathing lighting effect is shown in the following
figure. The parameter T0~T3 define 4 key periods in a complete breathing cycle. T0~T3 composite a breathing
loop, denoting the rise-time, on-time, fall-time and off-time respectively. Register GBRH (address 86h) and
GBRL (address 87h) control the max and min brightness of the breathing respectively.
T0 T1 T2 T3
GBRH
GBRL
Figure 12 LED breath timing in pattern mode
The start point and end point of autonomous breathing loop are configurable. The loop starting point could be
selected among T0~T3, which is set by bits LB [1:0] in register PATT2 (address 84h). The end point of the loop
can only be selected between the end of T3 and the end of T1, which is determined by bits LE [1:0] in register
PATT2. If bits LE [1:0] is not “00”, the end point of breathing loop is the end of T1, and the loop counter
increment by 1 at the end of T1. If bit LE [1:0] is “00”, the loop end point is the end of T3, and the loop counter
increment by 1 at the end of T3.
The repeat times is decided by bit RPT [11:8] of register PATT2 (address 84h) and RPT [7:0] of register PATT3
(address 85h). When setting RPT [11:0] to ‘0’, the breathing pattern will run unlimited times.
After the breathing pattern is over, the status bit PATIS in register PATGO (address 81h) will be set to ‘1’, and
PATIS will be cleared to ‘0’ after reading out through I2C bus. Once breathing loop start again or pattern
controller switches to manual mode by setting PATE bit to ‘0’, the PATIS will also be cleared.
When bit RUN in register PATGO is set to ‘1’, breathing pattern is started. The full process of the autonomous
breathing is as follows:
1. Set GSLR/G/B, GBRH/L parameter.
2. Set GCFG to select the LED in breathing pattern mode or not.
3. Configure PATT0, PATT1, PATT2, and PATT3 for parameters T0~T3, start/stop point, and repeat
times.
4. Set PATE=1 to enable breathing pattern mode.
5. Set PATMD=1 to select auto breathing mode.
6. Set RUN=1 to start the breath pattern.
Manual Control Mode
If bit PATMD is set to ‘0’, manual control mode is selected. In manual control mode, user could program the bit
SWITCH of register PATCFG to control the output of pattern controller. When bit SWITCH is ‘1’, the output of
pattern controller is decided by register GBRH. When bit SWITCH is set as “0”, the output is the decided by
register GBRL.
If bit RAM0PE in register PATCFG is set to ‘1’, the smooth ramp up/down will be enabled. At the same time, if
SWITCH changes from “0” to ‘1’, the output will be ramp up to GBRH smoothly. Similarly, if SWITCH changes
from “1” to ‘0’, the output of the pattern controller will ramp down to GBRL smoothly.
However, if the RAMP is set to ‘0’, the output of the pattern controller will change to GBRH or GBR directly
with no ramp as the SWITCH changes.
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Set PATCFG.SWITCH =1
fade-in fade-out
PATCFG.RAMPE =0
PATCFG.RAMPE =1
Set PATCFG.SWITCH =0
GBRH
GBRL
GBRH
GBRL
Figure 13 Manual Control Mode
PROTECTION FEATURES
Under Voltage Lock Out (UVLO)
When bit UVDIS of the register UVCR (address 60h) is set to ‘0’, the chip monitors the voltage of VCC. If the
supply voltage drops below threshold (2.5V typically), the bit UVST of the register UVCR (address 60h) will be
set to ‘1’. After read-out, the register UVCR will be clear.
If both bit UVDIS and bit UVPD of the register UVCR (address 60h) is set to ‘0’, UVLO protection function is
enabled. Once the event of under voltage occurs, the bit CHIPEN of the register GCR (address 20h) will be
cleared to ‘0’, and then the chip will enter into standby mode. If the voltage of VCC rises above the UVLO
threshold and then write “1” to bit CHIPEN, the chip will enter into active mode again.
By default, control bits UVDIS, UVPD are all “0”. Both UVLO monitor and protection are enabled.
Over Temperature Protection (OTP)
When bit OTDIS of the register OTCR (address 5Eh) is set to ‘0’, the over-temperature detection is enabled.
Once the temperature of this chip reaches 165°C, the over-temperature condition is detected, and the bit OTST
of the register OTCR (address 5Eh) will be set to ‘1’. The OTST will be cleared to ‘0’ after reading the register
OTCR.
If both bit OTDIS and bit OTPD of the register OTCR (address 5Eh) are set to ‘0’, the Over-Temperature
Protection (OTP) function is enabled. Once the temperature is over 165°C, the bit CHIPEN of the register GCR
(address 20h) will be cleared to ‘0’, and then the chip will enter into thermal shutdown mode. When the
temperature returns below 140°C, the chip will enter into active mode again after writing “1” to bit CHIPEN.
By default, control bits OTDIS and OTPD are all “0”, both OT monitor and OT protection are enable.
LED Open/Short Detection
AW21009 supports LED open/short detection. When bit OSDE[1:0] of the register OSDCR(address 5Ah) is
set to “10” , short detection is enabled, and the detection results can be read out via the registers
OSST0~1(5Bh~5Ch). Similarly, when set bit OSDE [1:0] of the register OSDCR (address 5Ah) to “11”, open
detection is enabled, and the results also can be read out via the registers OSST0~1.
The valid detect result is determined by:
Short Detection: VLED > VCC- VTHSHORT
Open Detection: VLED < VTHOPEN
Note: VTHOPEN: Threshold of open detection (When OTH=0, VTHOPEN = 0.1V, else VTHOPEN = 0.2V;).
VTHSHORT: Threshold of short detection (When STH=0, VTHSHORT = 0.5V, else VTHSHORT = 1V).
We recommend the bit DCPWM[1:0] of the register SSCR (address 5Fh) being set to “11” and maintain about
1mA current of each LED when the open/short function is enabled.
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I2C INTERFACE
The AW21009 supports the I2C protocol. The maximum frequency supported by the I2C is 1MHz.
The pull-up resistor for the SDA and SCL can be selected from 1kΩ to 10kΩ. Usually, 4.7kΩ is recommended
for 400 kHz I2C, 1kΩ is recommended for 1 MHz I2C. The voltage from 1.8V to 3.3V is allowed for the I2C
interface. Additionally, the I2C chip supports continuous read and write operations.
CHIP ADDRESS
The I2C chip address is 7-bit (A7~A1), followed by the bit R/W (A0). Set A0 to “0” for writing and “1” for reading.
The values of bit A1 and A2 are depended on the pin AD0. A3 and A4 are depended on the pin AD1. There are
2 options: VCC and GND. The A7 to A5 is “010” constantly. The chip also supports using a broadcast slave
address of 1Ch. All slave addresses as followed.
AD PIN
A7:A5
A4:A3
A2:A1
A0
Chip Address
Broadcast Address
GND/GND
010
00
00
0/1
20h
1Ch
GND/VCC
00
01
21h
VCC/GND
01
00
24h
VCC/VCC
01
01
25h
I2C START/STOP
All transactions begin with a START and are terminated by a STOP sent by master to slave. A high-to-low
transition on the SDA input/output while the SCL input is high defines a START condition. A low-to-high
transition on the SDA input/output while the SCL input is high defines a STOP condition.
In particular, the bus stays busy when a repeated START (Sr) is generated instead of a STOP signal
corresponding to the lastest START (S). Sr and S are usually regarded as equivalent.
SCL
SDA
S/Sr
S: START condition
Sr: START Repeated condition P: STOP condition
P
Figure 14 I2C START/STOP Condition Timing
DATA VALIDATION
When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level.Each
SCL pulse corresponds to one bit data transaction.
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SCL
SDA
Data Line
Stable
Data Valid
Change
of Data
Allowed
Figure 15 Data Validation Diagram
ACK (ACKNOWLEDGEMENT)
ACK means the successful transaction of I2C bus data. During writing cycle, after master sends 8-bit data,
SDA must be released by master and SDA is pulled down to GND by slave chip when slave sends ACK.
During reading cycle, after slave chip sends 8-bit data, slave releases the SDA and waits for ACK from master.
If master sends ACK with STOP condition, slave chip sends the next data. If master sends NACK, slave chip
stops sending data and waits for I2C stop.
12 8 9
Data Output
by Transmiter
Data Output
by Receiver
SCL From
Master START
condition
Not Acknowledge（NACK）
Acknowledge（ACK）
Clock Pulse for
Acknowledgement
Figure 16 I2C ACK Timing
WRITE CYCLE
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line aborts the current transaction during the high state of the SCL. New data should be sent to SDA bus
during the low SCL state. This protocol allows a single data line to transfer both command/control information
and data using the synchronous serial clock.
Each data transaction is composed of a start condition, a number of byte transfers and a stop condition to
terminate the transaction. Every byte written to the SDA bus must be 8 bits and is transferred with the most
significant bit first. After each byte, an ACK signal must follow.
1. In a write process, the following steps should be followed:
2. Master chip generates START condition. The “START” signal is generated by pulling down the SDA
signal while the SCL signal is high.
3. Master chip sends slave address (7-bit) and the data direction bit R/𝑊
= 0.
4. Slave chip sends acknowledge signal if the slave address is correct.
5. Master sends control register address (8-bit).
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6. Slave sends acknowledge signal.
7. Master sends data byte to write to the addressed register.
8. Slave sends acknowledge signal.
9. If master send more data bytes, the control register address will be incremented by one after
acknowledge signal (repeat step f and g).
10. Master generates STOP condition to indicate write cycle ends.
0
A2 A1 A0A6 A5 A3A4 A4 A3 A1A2A7 A5A6
123456780123456
D5 D4 D2D3A0 D6D7 D1 D0
78012345678SCL
SDA Ack
Ack
Start
R/W
Stop
Device Address Register Address Write Data
Ack
Figure 17 I2C Write Byte Cycle
READ CYCLE
In a read cycle, the following steps should be followed:
1. Master chip generates START condition
2. Master chip sends slave address (7-bit) and the data direction bit (R/W = 0).
3. Slave chip sends acknowledge signal if the slave address is correct.
4. Master sends control register address (8-bit)
5. Slave sends acknowledge signal
6. Master generates STOP condition followed with START condition or REPEAT START condition
7. Master chip sends slave address (7-bit) and the data direction bit (R/W = 1).
8. Slave chip sends acknowledge signal if the slave address is correct.
9. Slave sends data byte from addressed register.
10. If the master chip sends acknowledge signal, the slave chip will increase the control register address by
one, then send the next data from the new addressed register. In particular, if register address is 00h or
01h, the slave chip will poll register address between 00h and 01h.
11. If the master chip generates STOP condition, the read cycle ends.
0
A2 A1 A0A6 A5 A3A4 A4 A3 A1A2A7 A5A6
123456780123456
A4 A3 A1A2
A0
A5A6 D6 D0D1A0 D7
7
01234567801... 6
SCL
SDA Ack
Ack
Ack
7 8
Ack
start
R/W
……
stop
Device Address Register Address
Device Address Read Data
8
RS
Using
Repeat start
A4 A3 A1A2A5A6 D6 D0D1A0 D7
0 1 2 3 4 5 6 7 8 0 1... 6
Ack
7 8
Ack
……
stopReadData
S
Separated
Read/write
transaction
……
……
Device Address
P
……
…… R/W
R/W
Figure 18 I2C Read Byte Cycle
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REGISTER CONFIGURATION
REGISTER LIST
ADDR
R/W
NAME
D7
D6
D5
D4
D3
D2
D1
D0
DEF
20h
RW
GCR
APSE
CLKFRQ
-
PWMRES
CHIPEN
00h
21h
RW
BR00L
BR00L
00h
22h
RW
BR00H
-
BR00H
00h
…
…
…
…
…
31h
RW
BR08L
BR08L
00h
32h
RW
BR08H
-
BR08H
00h
45h
W
UPDATE
UPDATE
00h
46h
RW
SL00
SL00
00h
…
…
…
…
…
4Eh
RW
SL08
SL08
00h
58h
RW
GCCR
GCC
00h
59h
RW
PHCR
PDE
-
PINVTE
00h
5Ah
RW
OSDCR
-
OTH
STH
OSDE
00h
5Bh
R
OSST0
OP/ST [7:0]
00h
5Ch
R
OSST1
-
OP/ST [8]
00h
5Eh
RW
OTCR
TROF
TRST
OTST
OTPD
OTDIS
TRTH
00h
5Fh
RW
SSCR
-
DCPWM
SSE
SSR
CLT
00h
60h
RW
UVCR
REXT_ST
UVST
PUST
OCPTH
UVPD
UVDIS
00h
61h
RW
GCR2
-
BSDIS
UDMD
SBMD
RGBMD
00h
62h
RW
GCR3
-
APS2E
SRR
SRF[1:0]
00h
70h
RW
RESET
RESET/ID
12h
80h
RW
PATCFG
-
SWITCH
RAMPE
PATMD
PATE
00h
81h
RW
PATGO
-
PATIS
PATST
RUN
00h
82h
RW
PATT0
T0
T1
00h
83h
RW
PATT1
T2
T3
00h
84h
RW
PATT2
LE
LB
RPT[11:8]
00h
85h
RW
PATT3
RPT[7:0]
00h
86h
RW
GBRH
GBRH
00h
87h
RW
GBRL
GBRL
00h
88h
RW
GSLR
GSLR
00h
89h
RW
GSLG
GSLG
00h
8Ah
RW
GSLB
GSLB
00h
8Bh
RW
GCFG
-
GSLDIS
-
GE2
GE1
GE0
00h
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REGISTER DETAILED DESCRIPTION
GCR: Global Control Register (Address 20h)
Bit
Symbol
R/W
Description
Default
7
APSE
RW
Auto power save enable
0: disable
1: enable
0
6:4
CLKFRQ
RW
OSC frequency selection
000
000: 16MHz
001: 8MHz
010: 1MHz
011: 512kHz
100: 256kHz
101: 125kHz
110: 62.5kHz
111: 31.25kHz
3
reserved
-
-
0
2:1
PWMRES
RW
Brightness resolution selection
00: 8bit
01: 9bit
10: 12bit
11: 12bit with dither enabled
00
0
CHIPEN
RW
Chip enable
0: disable
1: enable
0
BRxxL/BRxxH: Brightness Control Register (Addredd 21h~32h)
Bit
Symbol
R/W
Description
Default
7:0
BRxxL
RW
Brightness control LSB8 for LED
00h
3:0
BRxxH
RW
Brightness control MSB4 for LED
0000
UPDATE: Update Register (Address 45h)
Bit
Symbol
R/W
Description
Default
7:0
UPDATE
W
Write 00h to update BR and SL registers
00h
SLxx: Scaling Register (Address 46h~4Eh)
Bit
Symbol
R/W
Description
Default
7:0
SLxx
RW
Scaling parameter for LED
00h
GCCR: Global Current Control Register (Address 58h)
Bit
Symbol
R/W
Description
Default
7:0
GCC
RW
Global current control register
00h
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