Caen V2718 Technical document

Technical
Information
Manual
MOD. V2718 •VX2718
July 03rd, 2018
Revision n. 11
VME –PCI
OPTICAL LINK BRIDGE
MANUAL REV. 11
NPO:
00106/03:V2718.MUTx/11

CAEN S.p.A.
Via Vetraia, 11 55049 Viareggio (LU) - ITALY
Tel. [phone] Fax [phone]
[email protected]
www.caen.it
© CAEN SpA –2018
Disclaimer
No part of this manual may be reproduced in any form or by any means, electronic, mechanical,
recording, or otherwise, without the prior written permission of CAEN SpA.
The information contained herein has been carefully checked and is believed to be accurate; however,
no responsibility is assumed for inaccuracies. CAEN SpA reserves the right to modify its products
specifications without giving any notice; for up to date information please visit www.caen.it.
MADE IN ITALY: We remark that all our boards have been designed and assembled in Italy. In a
challenging environment where a competitive edge is often obtained at the cost of lower wages and
declining working conditions, we proudly acknowledge that all those who participated in the production
and distribution process of our devices were reasonably paid and worked in a safe environment (this
is true for the boards marked "MADE IN ITALY", while we cannot guarantee for third-party
manufactures).

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User's Manual (MUT)
Mod. V2718 VME PCI Optical Link Bridge
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3
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ...........................................................................................................................8
1.1. OVERVIEW ...............................................................................................................................................8
1.2. BLOCK DIAGRAM....................................................................................................................................10
1.3. CONET LAYOUT ...................................................................................................................................11
2. VME INTERFACE .......................................................................................................................................12
2.1. VME BUS REQUESTER ...........................................................................................................................12
2.1.1. Fair and Demand Request modes ..................................................................................................13
2.1.2. VME bus Release ..........................................................................................................................13
2.2. ADDRESSING CAPABILITIES ....................................................................................................................13
2.3. DATA TRANSFER CAPABILITIES ..............................................................................................................14
2.4. INTERRUPT CAPABILITIES.......................................................................................................................14
2.5. CYCLE TERMINATIONS ...........................................................................................................................15
2.6. SLAVE ....................................................................................................................................................16
2.7. LOCATION MONITOR..............................................................................................................................17
2.8. VME BUS FIRST SLOT DETECTOR ..........................................................................................................17
2.9. SYSTEM CONTROLLER FUNCTIONS.........................................................................................................18
2.9.1. System Clock Driver .....................................................................................................................18
2.9.2. Arbitration Module........................................................................................................................18
2.9.2.1. Fixed Priority Arbitration Mode (PRI)................................................................................18
2.9.2.2. Round Robin Arbitration Mode (RRS) .................................................................................18
2.10. BUS TIMER.............................................................................................................................................18
2.11. IACK DAISY CHAIN DRIVER..................................................................................................................19
2.12. VME64X CYCLES NOT YET IMPLEMENTED............................................................................................19
2.13. INTERNAL REGISTERS.............................................................................................................................20
2.13.1. Status register ................................................................................................................................21
2.13.2. Control register..............................................................................................................................22
2.13.3. Firmware Revision register............................................................................................................22
2.13.4. Firmware Download register.........................................................................................................23
2.13.5. Flash Enable register .....................................................................................................................23
2.13.6. IRQ Status register.........................................................................................................................23
2.13.7. IRQ Mask register .........................................................................................................................23
2.13.8. Input register..................................................................................................................................24
2.13.9. Output set register..........................................................................................................................24
2.13.10. Output clear register ......................................................................................................................25
2.13.11. Input Multiplexer Set register........................................................................................................26
2.13.12. Input Multiplexer Clear register ....................................................................................................27
2.13.13. Output Multiplexer Set register .....................................................................................................28
2.13.14. Output Multiplexer Clear register..................................................................................................29
2.13.15. LED Polarity set register ...............................................................................................................29
2.13.16. LED polarity clear register ............................................................................................................30
2.13.17. Pulser A 0 register .........................................................................................................................30
2.13.18. Pulser A 1 register .........................................................................................................................30
2.13.19. Pulser B 0 register..........................................................................................................................31
2.13.20. Pulser B 1 register..........................................................................................................................31
2.13.21. Scaler 0 register.............................................................................................................................31
2.13.22. Scaler 1 register.............................................................................................................................32
2.13.23. Display Address Low register .......................................................................................................32
2.13.24. Display Address High register.......................................................................................................32
2.13.25. Display Data Low register.............................................................................................................32

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4
2.13.26. Display Data High register ............................................................................................................33
2.13.27. Display Control Left register.........................................................................................................33
2.13.28. Display Control Right register.......................................................................................................33
2.13.29. Location Monitor Address Low register........................................................................................34
2.13.30. Location Monitor Address High register.......................................................................................34
2.13.31. Location Monitor Control register.................................................................................................34
2.13.32. BA Rotary Switches Status register...............................................................................................34
3. TECHNICAL SPECIFICATIONS................................................................................................................35
3.1. PACKAGING............................................................................................................................................35
3.2. POWER REQUIREMENTS..........................................................................................................................35
3.3. FRONT PANEL.........................................................................................................................................36
3.4. V2718 AND A2818/A3818 EXTERNAL COMPONENTS.............................................................................37
3.4.1. V2718 connectors..........................................................................................................................37
3.4.2. V2718 buttons ...............................................................................................................................37
3.4.3. A2818 connectors..........................................................................................................................37
3.4.4. A3818 connectors..........................................................................................................................37
3.5. V2718 INTERNAL HARDWARE COMPONENTS..........................................................................................38
3.5.1. Switches.........................................................................................................................................38
3.5.2. Internal jumpers.............................................................................................................................40
3.6. PROGRAMMABLE INPUT/OUTPUT...........................................................................................................41
3.6.1. Timer & Pulse Generator...............................................................................................................41
3.6.2. Scaler.............................................................................................................................................42
3.6.3. Coincidence...................................................................................................................................42
3.6.4. Input/Output Register ....................................................................................................................42
3.7. I/O INTERNAL CONNECTIONS..................................................................................................................43
3.8. VME DATAWAY DISPLAY......................................................................................................................44
3.9. FIRMWARE UPGRADE..............................................................................................................................46
3.10. V2718 TECHNICAL SPECIFICATIONS TABLE ............................................................................................49
4. SOFTWARE OVERVIEW ...........................................................................................................................50
4.1. SOFTWARE USER INTERFACE .................................................................................................................50
4.1.1. Software User Interface: Installation .............................................................................................50
4.1.2. Hardware Installation ....................................................................................................................51
4.1.3. CAENVME Demo: The Main Menu.............................................................................................52
4.1.4. Software User Interface: I/O Setting Menu –VME Settings.........................................................53
4.1.5. Software User Interface: I/O Setting Menu –Pulser .....................................................................53
4.1.6. Software User Interface: I/O Setting Menu –Scaler .....................................................................54
4.1.7. Software User Interface: I/O Setting Menu –Location Monitor...................................................54
4.1.8. Software User Interface: I/O Setting Menu –Input.......................................................................55
4.1.9. Software User Interface: I/O Setting Menu –Output ....................................................................55
4.1.10. Software User Interface: I/O Setting Menu –Display...................................................................55
4.1.11. Software User Interface: I/O Setting Menu –About .....................................................................56
4.2. CAENVMELIB INTRODUCTION.............................................................................................................56
4.3. CAENVMELIB 1.X DESCRIPTION ..........................................................................................................56
4.3.1. CAENVME_SWRelease...............................................................................................................56
4.3.2. CAENVME_Init............................................................................................................................57
4.3.3. CAENVME_BoardFWRelease .....................................................................................................57
4.3.4. CAENVME_End...........................................................................................................................57
4.3.5. CAENVME_ReadCycle................................................................................................................58
4.3.6. CAENVME_MultiRead ................................................................................................................58
4.3.7. CAENVME_RMWCycle ..............................................................................................................59
4.3.8. CAENVME_WriteCycle...............................................................................................................59
4.3.9. CAENVME_MultiWrite ...............................................................................................................60

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4.3.10. CAENVME_BLTReadCycle ........................................................................................................60
4.3.11. CAENVME_MBLTReadCycle.....................................................................................................61
4.3.12. CAENVME_BLTWriteCycle........................................................................................................61
4.3.13. CAENVME_MBLTWriteCycle....................................................................................................62
4.3.14. CAENVME_ADOCycle ...............................................................................................................62
4.3.15. CAENVME_ADOHCycle.............................................................................................................62
4.3.16. CAENVME_SetPulserConf ..........................................................................................................63
4.3.17. CAENVME_SetScalerConf ..........................................................................................................64
4.3.18. CAENVME_SetOutputConf .........................................................................................................65
4.3.19. CAENVME_SetInputConf............................................................................................................65
4.3.20. CAENVME_GetPulserConf..........................................................................................................66
4.3.21. CAENVME_GetScalerConf..........................................................................................................66
4.3.22. CAENVME_SetOutputConf .........................................................................................................67
4.3.23. CAENVME_ReadRegister............................................................................................................67
4.3.24. CAENVME_SetOutputRegister....................................................................................................67
4.3.25. CAENVME_ClearOutputRegister.................................................................................................68
4.3.26. CAENVME_PulseOutputRegister.................................................................................................68
4.3.27. CAENVME_ReadDisplay.............................................................................................................68
4.3.28. CAENVME_SetArbiterType.........................................................................................................69
4.3.29. CAENVME_SetRequesterType ....................................................................................................69
4.3.30. CAENVME_SetReleaseType........................................................................................................69
4.3.31. CAENVME_SetBusReqLevel.......................................................................................................70
4.3.32. CAENVME_SetTimeout...............................................................................................................70
4.3.33. CAENVME_SetFIFOMode ..........................................................................................................70
4.3.34. CAENVME_GetArbiterType........................................................................................................71
4.3.35. CAENVME_GetRequesterType....................................................................................................71
4.3.36. CAENVME_GetReleaseType.......................................................................................................71
4.3.37. CAENVME_GetBusReqLevel......................................................................................................72
4.3.38. CAENVME_GetTimeout ..............................................................................................................72
4.3.39. CAENVME_GetFIFOMode..........................................................................................................72
4.3.40. CAENVME_SystemReset.............................................................................................................73
4.3.41. CAENVME_ResetScalerCount.....................................................................................................73
4.3.42. CAENVME_EnableScalerGate.....................................................................................................73
4.3.43. CAENVME_DisableScalerGate....................................................................................................74
4.3.44. CAENVME_StartPulser................................................................................................................74
4.3.45. CAENVME_StopPulser ................................................................................................................74
4.3.46. CAENVME_IACKCycle ..............................................................................................................75
4.3.47. CAENVME_IRQCheck ................................................................................................................75
4.3.48. CAENVME_IRQEnable ...............................................................................................................75
4.3.49. CAENVME_IRQDisable ..............................................................................................................76
4.3.50. CAENVME_IRQWait...................................................................................................................76
4.3.51. CAENVME_ReadFlashPage.........................................................................................................76
4.3.52. CAENVME_WriteFlashPage........................................................................................................77
4.3.53. CAENVME_SetInputConf............................................................................................................77
4.3.54. CAENVME_SetLocationMonitor.................................................................................................77
4.3.55. CAENVME_WriteRegister...........................................................................................................78
5. TECHNICAL SUPPORT..............................................................................................................................79
LIST OF FIGURES
FIG.1: MOD.V2718 BLOCK DIAGRAM ...............................................................................................................10
FIG.2: CONET CABLES LAYOUT........................................................................................................................11
FIG.3: INTERNAL ARBITRATION FOR VMEBUS REQUESTS................................................................................12

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FIG.4: V2718 SLAVE OPERATION.......................................................................................................................16
FIG.5: THE LOCATION MONITOR .......................................................................................................................17
FIG.6: STATUS REGISTER...................................................................................................................................21
FIG.7: CONTROL REGISTER................................................................................................................................22
FIG.8: FIRMWARE REVISION REGISTER .............................................................................................................22
FIG.9: IRQ STATUS REGISTER............................................................................................................................23
FIG.10: IRQ MASK REGISTER ............................................................................................................................23
FIG.11: INPUT REGISTER....................................................................................................................................24
FIG.12: OUTPUT SET REGISTER..........................................................................................................................24
FIG.13: OUTPUT SET REGISTER..........................................................................................................................25
FIG.14: INPUT MULTIPLEXER REGISTER ............................................................................................................26
FIG.15: INPUT MULTIPLEXER REGISTER ............................................................................................................27
FIG.16:OUTPUT MULTIPLEXER SET REGISTER ..................................................................................................28
FIG.17: OUTPUT MULTIPLEXER SET REGISTER ..................................................................................................29
FIG.18: LED POLARITY SET REGISTER...............................................................................................................29
FIG.19: LED POLARITY CLEAR REGISTER ..........................................................................................................30
FIG.20: PULSER A0REGISTER...........................................................................................................................30
FIG.21: PULSER A1REGISTER...........................................................................................................................30
FIG.22: PULSER B0REGISTER ...........................................................................................................................31
FIG.23: PULSER B1REGISTER ...........................................................................................................................31
FIG.24: SCALER 0REGISTER ..............................................................................................................................31
FIG.25: SCALER 1REGISTER ..............................................................................................................................32
FIG.26: DISPLAY ADDRESS LOW REGISTER .......................................................................................................32
FIG.27: DISPLAY ADDRESS HIGH REGISTER.......................................................................................................32
FIG.28: DISPLAY ADDRESS LOW REGISTER .......................................................................................................32
FIG.29: DISPLAY DATA HIGH REGISTER ............................................................................................................33
FIG.30: DISPLAY CONTROL LEFT REGISTER ......................................................................................................33
FIG.31: DISPLAY CONTROL LEFT REGISTER ......................................................................................................33
FIG.32: LOCATION MONITOR ADDRESS LOW REGISTER ....................................................................................34
FIG.33: LOCATION MONITOR ADDRESS LOW REGISTER ....................................................................................34
FIG.34: LOCATION MONITOR CONTROL REGISTER.............................................................................................34
FIG.35: BA ROTARY SWITCHES STATUS REGISTER ...........................................................................................34
FIG.36: MOD.V2718 AND A2818/A3818 FRONT PANELS..................................................................................36
FIG.37: PROG_3 SWITCH SETTING....................................................................................................................39
FIG.38: COMPONENT LOCATION........................................................................................................................40
FIG.39: INPUT/OUTPUT CONNECTIONS SCHEME.................................................................................................43
FIG.40: DATAWAY DISPLAY LAYOUT................................................................................................................44
FIG.41: CAENUPGRADER’S “GET FW RELEASE”VIEW....................................................................................46
FIG.42: CAENUPGRADER’S “UPGRADE FIRMWARE”VIEW...............................................................................47
FIG.43: VME INDEX IN THE CONET NETWORK................................................................................................47
FIG.44: FIRMWARE REVISION ON THE DATAWAY DISPLAY................................................................................48
FIG.45: THE SOFTWARE &DOCUMENTATION PACK CD INTRODUCTION...........................................................50
FIG.46: THE MAIN MENU ..................................................................................................................................52
FIG.47: THE I/O SETTING MENU –VME SETTINGS...........................................................................................53
FIG.48: THE I/O SETTING MENU –PULSER........................................................................................................53
FIG.49: THE I/O SETTING MENU –SCALER .......................................................................................................54
FIG.50:THE I/O SETTING MENU –LOCATION MONITOR...................................................................................54
FIG.51: THE I/O SETTING MENU –INPUT ..........................................................................................................55
FIG.52: THE I/O SETTING MENU –INPUT ..........................................................................................................55
FIG.53: THE I/O SETTING MENU –DISPLAY......................................................................................................55
FIG.54: THE I/O SETTING MENU –DISPLAY......................................................................................................56
LIST OF TABLES

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TABLE 1.1: AVAILABLE ITEMS .............................................................................................................................9
TABLE 1.2: CONET CABLES SPECIFICATIONS ....................................................................................................11
TABLE 2.1: ADDRESS MAP FOR THE MODEL V2718...........................................................................................16
TABLE 2.2: REGISTERS MAP ...............................................................................................................................20
TABLE 3.1: FPGA AVAILABLE FUNCTIONS.........................................................................................................41
TABLE 3.2: MOD.V2718 TECHNICAL SPECIFICATIONS.......................................................................................49
TABLE 4.1: SOURCE SELECTION .........................................................................................................................65

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1.General description
1.1. Overview
The Mod. V2718 is a 1-unit wide 6U VME master module, which can be interfaced to the
CONET (Chainable Optical NETwork) and controlled by a standard PC equipped with the
PCI card CAEN Mod. A2818 or the PCIe card A3818. The A2818 is a 32-bit 33 MHz PCI
card supporting both the CONET1 old version of CAEN optical link communication
portocol and the latest CONET2 one (for details, please refer to the Application Note
“AN2472 - CONET1 to CONET2 migration” freely downloadable on CAEN website at
Home / Document Library). The A3818 is a PCI Express (v1.1 or higher) card that can
plug into both x8 and x16 PCI Express slot and allows the control of up to 4 CONET2
independent networks. A3818 doesn’t support CONET1 protocol.
The communication path uses optical fiber cables as physical transmission line. Up to 8
V2718 VME masters can be controlled by one A2818 PCI controller, while up to 32 ones
can be controlled by one A3818 PCIe controller.
The module is capable of performing all the cycles foreseen by the VME64X
specifications
1
.
Important note: the Mod. VX2718 is the VME64X mechanics version of the module and
requires a VME64X type crate; the Mod. VN2738 is the VNX9 (9 Unit) mechanics version
of the module and requires a VNX9 type crate. In the present manual the “generic” term
“V2718” refers to all versions, except as otherwise specified.
The module can work in a “multimaster” system with the possibility of operating as a
system controller, in this case (which is the default option as the board is inserted in the
slot 1), it works as Bus Arbiter, Sysclock Driver, IACK Daiy Chain Driver, etc.
The module features a LED display which allows to monitor the VME bus activity in
detail. The front panel features 5 TTL/NIM programmable outputs on LEMO 00
connectors (default assignment is: DS, AS, DTACK, BERR signals and the output of a
programmable Location Monitor) and two programmable TTL/NIM inputs (on LEMO 00
connectors).
2
Operation as a Slave module is available for reading the Dataway display and the
Internal Test RAM.
The sustained data transfer rate is up to 70 MByte/s by using CONET1 and up to 80
MByte/s by using CONET2. Thanks to the 128KB memory buffer, the activity on the VME
bus is not slowed down by the transfer rate on the CONET when several V2718’s share
the same network. The firmware updates, documentation and useful software supporting
the use with the most common PC platforms (Windows XP/VISTA/7, Linux), are available
on CAEN website at:
Home / Products / Modular Pulse Processing Electronics / VME / Controller (VME) / V2718.
1
2eVME cycles and 3U boards cycles are not implemented yet.
2
LED display and TTL/NIM I/Os are not available on Mod. V/VX2718LC versions

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Table 1.1: Available items
Code
Description
LED display
TTL/NIM I/Os
Form factor
WK2718LCXAAA
V2718KITLC - VME-PCI Bridge
(V2718) + PCI Optical Link (A2818) +
Optical Fibre 5m duplex (AY2705)
no
no
VME6U
WK2718XAAAAA
V2718KIT - VME-PCI Bridge
(V2718) + PCI Optical Link (A2818) +
Optical Fibre 5m duplex (AY2705)
yes
yes
VME6U
WKX2718LCXAA
VX2718KITLC - VME-PCI Bridge
(VX2718) + PCI Optical Link (A2818)
+ Optical Fibre 5m duplex (AY2705)
no
no
VME64X
WKX2718XAAAA
VX2718KIT - VME-PCI Bridge
(VX2718) + PCI Optical Link (A2818)
+ Optical Fibre 5m duplex (AY2705)
yes
yes
VME64X
WK2718XBAAAA
V2718KITB - VME-PCI Bridge
(V2718) + PCIe Optical Link
(A3818A) + Optical Fibre 5m
duplex (AY2705)
yes
yes
VME6U
WKX2718XBAAA
VX2718KITB - VME-PCI Bridge
(VX2718) + PCIe Optical Link
(A3818A) + Optical Fibre 5m
duplex (AY2705)
yes
yes
VME64X
WV2718LCXAAA
V2718LC - VME-PCI Bridge
no
no
VME6U
WV2718XAAAAA
V2718 - VME-PCI Bridge
yes
yes
VME6U
WVX2718LCXAA
VX2718LC - VME-PCI Bridge
no
no
VME64X
WVX2718XAAAA
VX2718 - VME-PCI Bridge
yes
yes
VME64X
WKN2738XAAAA
VN2738KIT - VN2738 + A2818 Kit +
Optical Fibre 20m
yes
yes
VME9U
WVN2738XAAAA
VN2738 - 9U VME-PCI Bridge
yes
yes
VME9U
WA2818XAAAAA
A2818 - PCI Optical Link
PCI
WA3818AXAAAA
A3818A - PCIe 1 Optical Link
PCIe
WA3818BXAAAA
A3818B - PCIe 2 Optical Link
PCIe
WA3818CXAAAA
A3818C - PCIe 4 Optical Link
PCIe
WAI2703XAAAA
AI2703 - Optical Fibre 30cm. simplex
WAI2705XAAAA
AI2705 - Optical Fibre 5 m. simplex
WAI2720XAAAA
AI2720 - Optical Fibre 20 m. simplex
WAI2730XAAAA
AI2730 - Optical Fibre 30 m. simplex
WAI2740XAAAA
AI2740 - Optical Fibre 40 m. simplex
WAY2705XAAAA
AY2705 - Optical Fibre 5 m. duplex
(Rohs compliant)
WAY2720XAAAA
AY2720 - Optical Fibre 20 m. duplex
WAY2730XAAAA
AY2730 - Optical Fibre 30 m. duplex

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1.2. Block diagram
128K SRAM
BUFFER
VME BUS
V2718
A2719
CONET
INTERF.
FPGA
MASTER
SLAVE
SYSTEM
CONTROLLER
RAM
16x32
VME CYCLE
MONITOR
LOCAL BUS
INTERFACE
I/O
CONTROL
NIM/TTL
I/Os
DATA-WAY
DISPLAY
x5
x2
x88
uC
4Mbit FLASH
(FPGA FIRMWARE +
USER DEFINED)
BOOT
LOAD
STD
BCK
FW
A2818
LOCAL BUS
INTERFACE
PCI BUS
FPGA PLX-9054
PCI
INTERFACE
256K SRAM
BUFFER
4Mbit FLASH
(FPGA FIRMWARE +
USER DEFINED)
STD
BCK
FW uC
BOOT
LOAD
CONET
Optical Fiber
Fig. 1: Mod. V2718 block diagram
The FPGA (Field Programmable Gate Array) is the module’s core; it implements the
CONET communication protocol, the LED display and I/O connectors management on
the front side and the VME Master on the backside.
A 128 kbyte buffer allows to provide a temporary data storage during VME cycles: the
VME data rate is thus decoupled from the PCI rate and may take place at full speed.

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1.3. CONET Layout
Thanks to Daisy chain capability, a single A2818 CONET controller can control up to 8
V2718 VME masters, while a single A3818 CONET2 controller (e.g. the 4-link model) an
control upt to 32 V2718 VME masters. For this purpose, various types of cables are
available:
Table 1.2: CONET cables specifications
Cable:
Length:
Connector:
X-30
30 m
1 LC Duplex + 2 LC Simplex
X-20
20 m
1 LC Duplex + 2 LC Simplex
X-5
5 m
1 LC Duplex + 2 LC Simplex
I-40
40 m
2 LC Simplex
I-30
30 m
2 LC Simplex
I-20
20 m
2 LC Simplex
I-5
5 m
2 LC Simplex
I-3
30 cm
2 LC Simplex
If the network is composed by one A2818, or A3818, and only one V2718, then it is
suggested to use X-type cables: such cables have a duplex connector on the A2818 or
A3818 side and two simplex connectors on the crate side; the simplex connector with the
black wrap is for the RX line and the one with the red wrap is for the TX. If more than one
V2718 is present, the best solution is to use the X-type cable for connecting the A2818,
or the A3818, with the first and the last module and the I-type for connecting intermediate
modules. An example using the A2818 is given in Fig. 2.
Fig. 2: CONET cables layout
A2818 X-20
X-20
PC side
TX
RX
RX
TX
crate side
PC side
V2718
V2718
V2718
I-5
I-5
RX
TX
RX
TX
RX
TX
LC Duplex
connectors:
LC Simplex
connectors:
TX
RX
V2718
black
red
black
red
A2818

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12
2.VME Interface
The V2718 provides all of the addressing and data transfer modes documented in the
VME64 specification (except A64 and those intended to improve 3U applications, i.e. A40
and MD32). The V2718 is also compatible with all VME bus modules compliant to pre-
VME64 specifications. As VME bus master, the V2718 supports Read-Modify-Write
(RMW), and Address-Only-with-Handshake (ADOH) but does not accept RETRY* as a
termination from the VME bus slave. The ADOH cycle is used to implement the VME bus
Lock command allowing the PC Host to lock VME bus resources.
2.1. VME bus Requester
Fig. 3: Internal Arbitration for VME bus Requests
When the V2718 operates as VME bus Requester, the functional sequence is the
following:
−The PCI bus sends a VME bus access request
−The Master asserts DWB (Device Want Bus), and waits for DGB (Device Grant Bus)
−The Requester requests the bus to the Arbiter, via VME (whether the Arbiter is the
V2718 itself or not); when the Arbiter has granted the bus, the Requester asserts
DGB and BBSY (on the bus)
−The Master performs the the VME cycle, then releases DWB
−If REL_TYPE is RWD (Release When Done), then the Requester releases BBSY
MASTER REQUESTER ARBITER
VMEBUS
REQ_TYPE
REL_TYPE
ARB_TYPE
SYS_CTRL
DWB
DGB
BR[3:0]
BGO[3:0]
BGI[3:0]
BBSY
BCLR
BGO[3:0]
BBSY
BR[3:0]
ADDRESS,AM,DATA,AS,
DS,IACK,DTACK
A2818
PCIBUS

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13
2.1.1. Fair and Demand Request modes
The V2718 produces requests on all VME bus request levels: BR3*, BR2*, BR1*, and
BR0*. The default setting is for level 3 VME bus request. The request level is a global
programming option set through the Bus Request field in the Control register (see
§ 2.13.2).
The programmed request level is used by the VME bus Master Interface regardless of
the channel currently accessing the VME bus Master Interface.
The Requester may be programmed for either Fair or Demand mode. The request mode
is a global programming option set through the Requester Type bit in the Control register.
In Fair mode, the V2718 does not request the VME bus until there are no other VME bus
requests pending at its programmed level. This mode ensures that every requester on an
equal level has access to the bus.
In Demand mode, the requester asserts its bus request regardless of the state of the
BRn* line. By requesting the bus frequently, requesters far down the daisy chain may be
prevented from ever obtaining bus ownership. This is referred to as “starving” those
requesters. Note that in order to achieve fairness, all bus requesters in a VME bus
system must be set to Fair mode.
2.1.2. VME bus Release
The Requester can be configured as either RWD (release when done) or ROR (release
on request) using the Release Type bit in the Control register. The default setting is for
RWD: the bus is released as soon as the VME access is terminated; in case of
BLT/MBLT cycles, the access is terminated either when the N required bytes are
transferred (although the cycle is divided into several blocks according to the VME
boundaries) or when BERR* is asserted. ROR means the master releases BBSY* only if
a bus request is pending from another VMEbus master and once the channel that is the
current owner of the VME bus Master Interface is done. Ownership of the bus may be
assumed by another channel without re-arbitration on the bus if there are no pending
requests on any level on the VME bus.
2.2. Addressing capabilities
V2718 generates A16, A24, A32, CR/CSR and LCK address phases on the VME bus.
Address Modifiers of any kind (supervisor/non-privileged and program/data) are also
programmed through the PCI bus: the V2718 does not handle the AM: the PC Host
passes them via PCI as VME cycle parameters. The AM broadcasting depends on the
PC drivers.
The master generates ADdress-Only-with-Handshake (ADOH) cycles in support of lock
commands for A16, A24, and A32 spaces.
Supported addressing:
A16, A24, A32, CR/CSR for R/W, RMW, ADO and ADOH
A16, A24, A32 for BLT
A16, A24, A32 for MBLT
ADO Address Only
ADOH Address Only with Handshake

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2.3. Data transfer capabilities
The V2718 supports the following cycles:
Cycle Type
R/W Single Read/Write
RMW Read Modify Write
BLT Block Transfer
MBLT Multiplexed Block Transfer
Data sizing
D08(EO), D16, D32 for R/W, RMW, BLT
3
D64 for MBLT
−BLT/MBLT cycles may be performed with either address increment or with fixed
address (FIFO mode)
−BLT/MBLT cycles are split at hardware level when the boundary (BLT = Nx256 bytes;
MBLT = Nx2 Kbytes) is met: AS is released and then re-asserted, the VME bus is not
re-arbitered. The boundaries are neglected in FIFO operating mode.
−Non aligned accesses are not supported.
It is then possible to perform data cycles (single and BLT) with hardware byte swapping.
The “Swapped” cycles are called: D16_swapped, D32_swapped and D64_swapped.
Such cycles will return “swapped” data, in the following way:
D16_swapped: Byte0 ↔ Byte1, Byte1 ↔ Byte0
D32_swapped: Byte0 ↔ Byte3, Byte1 ↔ Byte2, Byte2 ↔ Byte1, Byte3 ↔ Byte0
D32_swapped: Byte0 ↔ Byte7, Byte1 ↔ Byte6, Byte2 ↔ Byte5, Byte3 ↔ Byte4, Byte4 ↔
Byte3, Byte5 ↔ Byte2, Byte6 ↔ Byte1, Byte7 ↔ Byte0
2.4. Interrupt capabilities
The VME Bus interrupts are transferred to the PCI BUS through the CONET. The
interrupt latency (i.e. the interval between the interrupt appearance on the VME bus and
the time the interrupt is activated on the PCI bus) is always shorter than 5 µs.
The V2718 supports the following IACK cycles:
IACK: D08, D16, D32
VME Bus Interrupts can be individually masked for each V2718 in the chain.
In order to enable the generation of PCI bus interrupts following VME bus interrupts, the
IRQEnable function (see § 4.3.48) must be used; then it is necessary to call IRQWait
(see § 4.3.50) in order to wait for the interrupt. When the IRQWait function returns, the
VME bus interrupts are disabled, so an IACK can be performed in order to obtain the
vector and, for RORA interrupts, the access to the interrupter must be performed in order
to stop the interrupt generation. If it is necessary to receive other VME bus interrupts, the
IRQEnable must be called again.
3
BLT08 not implemented

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15
2.5. Cycle terminations
The V2718 accepts BERR* or DTACK* as cycle terminations. BERR* is handled as cycle
termination whether it is produced by the V2718 itself or by another board. The Status
word broadcasted as the cycle is acknowledged, informs the PC HOST about the cycle
termination type (BERR* or DTACK*).

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16
VMEBUS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
AM0
AM1
AM2
AM3
AM4
AM5
IRQ1
IRQ2
IRQ3
IRQ7
BRQ
IRQ4
IRQ5
IRQ6
DTK
BERR
BGR
SRES
LWRD
DS0
DS1
AS
IACK
WR
DISP_AD
DISP_DT
DISP_CTRL
32 32 24
RAM
32 x16
32
2.6. Slave
The V2718 can be operated as slave for debugging purposes. It responds to VME cycles
(which must be initiated by another master, i.e. a V2718 cannot address itself as a slave)
for accessing the Dataway Display internal registers and a Test RAM (32 x 16). The
V2718 is accessed both with A32 and A24 base address (see § 3.5.1); the module is
provided with only two rotary switches for board addressing, so the addressing mode is
selected via the dip switch 3 (A24→PROG_3 = OFF; A32→PROG_3 = ON), see §
3.5.1.
The Address map for V2718 is listed in Table 2.1. All register addresses are referred to
the Base Address of the board, i.e. the addresses reported in the Tables are the offsets
to be added to the board Base Address.
Table 2.1: Address Map for the Model V2718
ADDRESS
REGISTER/CONTENT
ADDR_MODE
DATA_MODE
R/W
Base + %0000%00FC
Test RAM
A24/A32
D32, BLT32, MBLT
Read/Write
Base + %1000
Display Address
A24/A32
D32
Read only
Base + %1004
Display Data
A24/A32
D32
Read only
Base + %1008
Display Control
A24/A32
D32
Read only
Fig. 4: V2718 Slave operation

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2.7. Location Monitor
The V2718 monitors the cycles on the bus, whether they are held by itself or by other
masters, and produces a Trigger Out LMON signal as soon as a particular cycle is
performed (see Fig. 5). The LMON out is available by default as front panel signal.
Fig. 5: The Location Monitor
2.8. VME bus First Slot Detector
The First Slot Detector module samples BG3IN* immediately after reset to determine
whether the V2718 resides in slot 1. The VME bus specification requires that BG[3:0]*
lines be driven high during reset. This means that if a board is preceded by another
board in the VME bus system, it will always sample BG3IN* high after reset. BG3IN* can
only be sampled low after reset by the first board in the crate (there is no preceding
board to drive BG3IN* high). If BG3IN* is sampled at logic low immediately after reset
(due to the master internal pull-down), then the V2718 is in slot 1 and becomes SYSTEM
CONTROLLER: otherwise, the SYSTEM CONTROLLER module is disabled. This
mechanism may be overridden via dip switch setting: the SYSTEM CONTROLLER bit is
“forced” to one by setting to ON PROG_0, and is “forced” to zero by setting to ON
PROG_1; note that such switches must always be in “opposite” positions (see § 3.5.1).
VME BUS
LM_ADH
LM_ADL
VME_AD
LM_AM
LM_LWORD
LM_WRITE
VME_IACK
VME_WRITE
VME_LWORD
VME_AM
LM_AD
LM_CTRL
/AS
LM_OUT
DQ
LE
DQ
LE
DQ
LE
QD
LE
LM_IACK
DQ
LE

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2.9. System Controller Functions
When located in Slot 1 of the VME crate, the V2718 assumes the role of SYSTEM
CONTROLLER and sets the SYSTEM CONTROLLER status bit in the STATUS register.
In accordance with the VME64 specification, as SYSTEM CONTROLLER the V2718
provides:
−a system clock driver,
−an arbitration module,
−an IACK Daisy Chain Driver (DCD)
−a bus timer.
2.9.1. System Clock Driver
The V2718 provides a 16.66 MHz SYSCLK signal when configured as System Controller.
2.9.2. Arbitration Module
When the V2718 is SYSTEM CONTROLLER, the Arbitration Module is enabled. The
Arbitration
Module supports the following arbitration modes:
−Fixed Priority Arbitration Mode (PRI),
−Round Robin Arbitration Mode (RRS) (default setting).
These are set with the Arbiter bit in the STATUS register
2.9.2.1. Fixed Priority Arbitration Mode (PRI)
In this mode, the order of priority is BR[3], BR[2], BR[1], and BR[0] as
defined by the VME64 specification. The Arbitration Module issues a Bus Grant (BGO
[3:0]) to the highest requesting level.
If a Bus Request of higher priority than the current bus owner becomes asserted, the
Arbitration Module asserts BCLR until the owner releases the bus (BBSY is negated).
2.9.2.2. Round Robin Arbitration Mode (RRS)
This mode arbitrates all levels in a round robin mode, repeatedly scanning from levels 3
to 0.
Only one grant is issued per level and one owner is never forced from the bus in favor of
another requester (BCLR is never asserted).
Since only one grant is issued per level on each round robin cycle, several scans will be
required to service a queue of requests at one level.
2.10. Bus Timer
A programmable bus timer allows users to select a VMEbus time-out period. The time-
out period is programmed through the Bus Timeout bit in the Control register ( = 0 →
timeout = 50 µs; = 1 → timeout = 400µs). The VMEbus Timer module asserts BERR if a
VMEbus transaction times out (indicated by one of the VMEbus data strobes remaining
asserted beyond the time-out period).

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2.11. IACK Daisy Chain Driver
The V2718 can operate as IACK Daisy Chain Driver: it drives low the IACKOUT line of
the first slot, thus starting the chain propagation, as soon as it detects an Interrupt
Acknowledge cycle by an Interrupt Handler, that could be the V2718 itself.
2.12. VME64X Cycles not yet implemented
Presently the module does not implement the following functions, foreseen by the
VME64X:
Unaligned Transfer (UAT)
MD32 cycles
2eVME cycles
BLT08 cycles
A64 addresing
Cycles terminated with RETRY

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2.13. Internal registers
Table 2.2: Registers map
NAME
ADDRESS
Type
Nbit
Function
STATUS
00
read
16
Status register
VME_CTRL
01
read/write
16
VME control register
FW_REV
02
read only
16
Firmware revision
FW_DWNLD
03
read/write
8
Firmware download
FL_ENA
04
read/write
1
Flash enable
IRQ_STAT
05
read only
7
IRQ status
IRQ_MASK
06
read/write
7
IRQ mask
IN_REG
08
read/write
7
Front panel input register
OUT_REG_S
0A
read/write
11
Front panel output register set
IN_MUX_S
0B
read/write
12
Input multiplexer set
OUT_MUX_S
0C
read/write
15
Output multiplexer set
LED_POL_S
0D
read/write
7
LED polarity set
OUT_REG_C
10
write only
11
Front panel output register clear
IN_MUX_C
11
write only
12
Input multiplexer clear
OUT_MUX_C
12
write only
15
Output multiplexer clear
LED_POL_C
13
write only
7
LED polarity clear
PULSEA_0
16
read/write
16
Period and width of pulser A
PULSEA_1
17
read/write
10
# pulses and range of pulser A
PULSEB_0
19
read/write
16
Period and width of pulser B
PULSEB_1
1A
read/write
10
# pulses and range of pulser B
SCALER0
1C
read/write
11
End Count Limit and Autores of scaler
SCALER1
1D
read only
10
Counter value of scaler
DISP_ADL
20
read only
16
Display AD [15:0]
DISP_ADH
21
read only
16
Display AD [31:16]
DISP_DTL
22
read only
16
Display DT [15:0]
DISP_DTH
23
read only
16
Display DT [31:16]
DISP_PC1
24
read only
12
Display control left bar
DISP_PC2
25
read only
12
Display control right bar
LM_ADL
28
read/write
16
Local monitor AD [15:0]
LM_ADH
29
read/write
16
Local monitor AD [31:16]
LM_C
2C
read/write
9
Local monitor controls
B_ID
36
read
8
Status of the 2 rotary switches for the
board VME base address