Caen V812 Technical document

Technical
Information
Manual
Revision n. 4
20 April 2009
MOD. V 812 series
16 CH. CONSTANT
FRACTION
DISCRIMINATORS
NPO:
00101/97:V812x.MUTx/04

CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the
product is defective due to workmanship or materials and has not been caused by mishandling,
negligence on behalf of the User, accident or any abnormal conditions or operations.
CAEN declines all responsibility for damages or injuries
caused by an improper use of the Modules due to
negligence on behalf of the User. It is strongly
recommended to read thoroughly the CAEN User's Manual
before any kind of operation.
CAEN reserves the right to change partially or entirely the contents of this Manual at any time and
without giving any notice.
Disposal of the Product
The product must never be dumped in the Municipal Waste. Please check your local regulations for
disposal of electronics products.

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TABLE OF CONTENTS
1. GENERAL DESCRIPTION....................................................................................................................................5
1.1. FUNCTIONAL DESCRIPTION...............................................................................................................................5
1.2. BLOCK DIAGRAM..............................................................................................................................................7
1.3. TECHNICAL SPECIFICATION TABLE ...................................................................................................................8
2. TECHNICAL SPECIFICATIONS.........................................................................................................................9
2.1. PACKAGING......................................................................................................................................................9
2.2. POWER REQUIREMENTS ....................................................................................................................................9
2.3. FRONT PANEL.................................................................................................................................................10
2.4. EXTERNAL CONNECTORS................................................................................................................................11
2.4.1. INPUT connectors ....................................................................................................................................11
2.4.2. OUTPUT connectors ................................................................................................................................11
2.5. OTHER COMPONENTS .....................................................................................................................................12
2.5.1. Displays ....................................................................................................................................................12
2.5.2. Switches ....................................................................................................................................................12
2.5.3. Jumpers.....................................................................................................................................................12
3. VME INTERFACE ................................................................................................................................................15
3.1. ADDRESSING CAPABILITY ..............................................................................................................................15
3.2. DISCRIMINATOR THRESHOLDS........................................................................................................................16
3.3. PATTERN OF INHIBIT.......................................................................................................................................16
3.4. OUTPUT WIDTH CH.0TO 7AND CH.8TO 15 ..................................................................................................16
3.5. DEAD TIME CH.0TO 7...................................................................................................................................17
3.6. DEAD TIME CH.8TO 15.................................................................................................................................17
3.7. MAJORITY THRESHOLD...................................................................................................................................17
3.8. TEST PULSE ....................................................................................................................................................17
3.9. MODULE IDENTIFIER WORDS ..........................................................................................................................17
4. PRINCIPLES OF OPERATION ..........................................................................................................................19
4.1. THE CONSTANT FRACTION DISCRIMINATION TECHNIQUE ..............................................................................19
4.2. POWER ON /RESET STATUS...........................................................................................................................19
4.3. SETTING THE DELAY ......................................................................................................................................19
4.4. ENABLING/DISABLING THE CHANNELS...........................................................................................................19
4.5. TEST,VETO AND OR SIGNALS........................................................................................................................20
4.6. CHANNELS TEST .............................................................................................................................................20

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4.7. SETTING THE THRESHOLD...............................................................................................................................20
4.8. SETTING THE OUTPUT PULSE WIDTH ...............................................................................................................20
4.9. SETTING THE DEAD TIME ...............................................................................................................................21
4.10. CURRENT SUM SIGNAL...................................................................................................................................21
4.11. MAJORITY SETTING ........................................................................................................................................22
LIST OF FIGURES
FIG.1.1: MODEL TYPE LABEL (EXAMPLE V812 B)...............................................................................................................6
FIG.1.2: BLOCK DIAGRAM..................................................................................................................................................7
FIG.2.1: FRONT PANEL .....................................................................................................................................................10
FIG.2.2: COMPONENTS LOCATION.....................................................................................................................................13
FIG.2.3: JUMPERS LOCATION.............................................................................................................................................14
FIG.3.1: OUTPUT WIDTH VS.REGISTER SET VALUE...........................................................................................................16
FIG.3.2: MODULE IDENTIFIER WORDS..............................................................................................................................18
FIG.4.1: CURRENT SUM SIGNAL........................................................................................................................................21
FIG.4.2: EXAMPLE OF THREE DAISY CHAINED V812 .........................................................................................................23
LIST OF TABLES
TABLE 1.1:VERSIONS AVAILABLE FOR THE MODEL V812...................................................................................................6
TABLE 1.2: TECHNICAL SPECIFICATION TABLE....................................................................................................................8
TABLE 2.1: POWER REQUIREMENTS.....................................................................................................................................9
TABLE 3.1: ADDRESS MAP ................................................................................................................................................15

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1. General description
1.1. Functional description
The CAEN Model V812 is a 16 CHANNEL CONSTANT FRACTION DISCRIMINATOR housed
in a single width VME module. The module accepts 16 negative inputs and produces 16
differential ECL outputs with a fan-out of two on four front panel flat cable connectors (a
functional block diagram is shown in Fig. 1.2). Several version are available, refer to Table 1.1
for details.
Each channel can be turned on or off via VME by using a mask register (Pattern of Inhibit). The
pulse forming stage of the discriminator produces an output pulse whose width is adjustable in
a range from 15 ns to 250 ns via VME. Moreover, in order to protect against multiple pulsing, it
is possible to program via VME a Dead Time during which the discriminator is inhibited from
retriggering. The maximum time walk is ±400 ps (for input signals in the range from -50 mV to -
5 V with 25 ns rise time). The constant fraction is 20%. The constant fraction delay is defined by
a delay line network of 20 ns with 5 taps (see fig. 2.2). The discriminator thresholds are settable
via VME in a range from -1 mV to -255 mV (1 mV step) through an 8-bit DAC.
The module can operate also with small (below 10 mV) input signals, though in this case the
Constant Fraction operation is not performed, i.e. the walk is higher. VETO and TEST inputs
are available on the front panel. The front panel is provided with a Current Sum output that
generates a current proportional to the input multiplicity, i. e. to the number of channels over
threshold, at a rate of -1.0 mA per hit (-50 mV per hit into a 50 Ohm load) ±20 %. A
“MAJORITY” output provides a NIM signal if the number of input channels over threshold
exceeds the MAJORITY programmed value. The logic OR of discriminator outputs is available
on a front panel connector. The relevant “OR” LED lights up if at least one of the unmasked
channels is over threshold. The module’s operations are completely controlled via software for
each channel through the VME bus. The most important are:
•setting the discriminator thresholds (8 bit data) from -1 to -255 mV.
•setting pattern of inhibit; each channel can be turned “ON” or “OFF” by using a mask
register.
•setting output pulse width
•setting the Majority threshold value.
•selection of the Dead Time value.

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Table 1.1:Versions available for the Model V812
Version1Number of channels PAUX connector2
V812316 yes
V812 B 16 no
Fig. 1.1: Model type label (example V812 B)
1A label on the printed board soldering side indicates the module’s version (see Fig 1.1).
2The version with the PAUX connector requires the V430 backplane.
3Available exclusively on request
TYPE
RIF N.
DATE MAY 5th 2002
WV812XBAAAAA

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1.2. Block diagram
Fig. 1.2: Block Diagram
DACs,TEST,
INHIBIT
W LOGIC
VME
INTERFACE
8 bit
DAC
ch.0
8 bit 8 bit 8 bit
ch.1 ch14 ch.15
........................
THRESHOLDS,
.................discr.
INPUTS<0..15>
test
inhibit
ch.0 ch.1 ch.14 ch.15
TEST
VETO
OUTPUTS<0..15> A, B
OR LED
..................
discr. discr. discr.
WIDTH AND
OR
OUT
DEAD TIME
Σ
MAJ
8 bit
DAC
MAJ
DAC DAC DAC
VME
BUS

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1.3. Technical specification table
Table 1.2: Technical specification table
Packaging 6U-high, 1U-wide VME unit
Power requirements Refer to § 2.2
Inputs 16 inputs (negative polarity, 50 Ωimpedance)
Max input voltage -5 V
Min detectable signal -5 mV
Threshold range -1 mV to -255 mV (1 mV step)
Constant fraction 20%
Delay
Selectable in 4 ns steps (20 ns full scale)
Optional:
5ns full scale with 1ns steps
50ns full scale with 10ns steps
100ns full scale with 20ns steps
Outputs 16 outputs with a fan-out of two (ECL, 110 Ωimpedance)
Input/output delay Set delay+4.5±2 ns
Output width Programmable from 15 ns to 250 ns
Dead Time Programmable from 150 ns to 2 μs (±10%)
Max outputs time walk ±400 ps for input signals in the range from -50 mV to - 5 V with 25 ns
rise time
Autowalk
A
utomatic adjustment of input offset and low frequency input noise of
±40 mV
Control inputs NIM logic signals, high impedance:
VETO: allows to veto all channels simultaneously
TEST: triggers all the enabled channels at once
Control outputs
MAJORITY: standard NIM logic signal, 50 Ωimpedance; it
indicates if the number of input channels over threshold exceeds
the MAJORITY level programmed via VME
OR: standard NIM signal, 50 Ωimpedance; logic OR of outputs
Σ:current proportional to input multiplicity (-1 mA ±20% per hit),
high impedance
Displays DTACK: green LED; lights up at each VME access
OR: green LED; it lights up if at least one output signal is present

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2. Technical Specifications
2.1. Packaging
The Mod. V812 is housed in a 6U-high 1U-wide VME unit.
2.2. Power requirements
The power requirements of the Mod. V812 are as follows:
Table 2.1: Power requirements
V812 V812 B
+ 12 V 100 mA 100 mA
- 12 V 60 mA 60 mA
+ 5 V 1 A 5.5 A
- 5 V 3 A

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2.3. Front Panel
Mod. V812
CFD
16 CH
16 CH
OR
MAJ
Σ
I
N
2
0
4
6
3
1
5
7
I
N
12
14
10
8
13
15
11
9
DTK
V
E
T
O
T
E
S
T
- + - +
- + - +
8
0
15
7
OUT
OUT
Fig. 2.1: Front Panel