Cirrus Logic CS4399 User manual

Copyright Cirrus Logic, Inc. 2015–2016
(All Rights Reserved)
http://www.cirrus.com
130-dB, 32-Bit High-Performance DAC
System Features
• Enhanced  oversampling DAC architecture
— 32-bit resolution
— Up to 384-kHz sampling rate
— Low clock jitter sensitivity
— Auto mute detection
• Integrated high performance outputs
— 130-dB dynamic range (A-weighted)
— –108-dB total harmonic distortion + noise (THD+N)
— 110-dB interchannel isolation
• Headphone detection
— Headphone plug-in detection
— Popguard®technology eliminates pop noise
• Integrated PLL
— Support for 11.2896-/22.5792-, 12.288-/24.576-, 9.6-/
19.2-, 12-/24-, and 13-/26-MHz system MCLK rates
— Reference clock sourced from XTI/MCLK pin
— System clock output
• Mono mode support
•I
2C control—up to 1 MHz
• Direct Stream Digital (DSD®) path
— Patented DSD processor
– On-chip 50-kHz filter to meet Scarlet Book Super
Audio Compact Disk (SACD) recommendations
– Matched PCM and DSD analog output levels
– Nondecimating volume control with 0.5-dB step size
and soft ramp
– DSD and Pulse-code modulation (PCM) mixing for
alerts
— Dedicated DSD and DoP pin interface
• Serial audio input path
— Five selectable digital filter responses
– Low-latency mode minimizes pre-echo
– 110 dB of stopband attenuation
— Supports sample rates from 32 to 384 kHz
—I
2S, right-justified, left-justified, TDM, and
DSD-over-PCM (DoP) interface
— Master or slave operation
— Volume control with 0.5-dB step size and soft ramp
— 44.1 kHz deemphasis and inverting feature
• 40-pin QFN or 42-ball CSP package option
Applications
• Smart phones, tablets, portable media players, laptops,
digital headphones, powered speakers, AVR, home
theater systems, Blu-ray/DVD/SACD players and pro
audio
VCP _FILT+
Multibit

Modul ator
Multibit

Modul ator
Interpolation
Filter and
Volume
Control
DSD
Processor
Interpolation
Filter and
Volume
Control
Control Port Level Translator
Register /H ar dwar e
Configur ation
PLL
XTI/ M CLK
DoP to
DSD
Engine
Analog Supply
(VA,VCP)
+1.8V
FILT +
Le vel
Tr an sl ato r
Popguar d®
Circuitry
ASP
FLYN _VCP
FLYP_VA
XTAL
OSC
XTO
VCP_FILT+
VCP _FILT -
FLYN_VA
-VA
Charge Pump
Interrupt
Sources Internal
Voltage
Reference
AOUTA
REFA
XSP/DSD
Audio
Interface
MUX
FILT-
FLYP_VCP
VA
-VA
D igita l Au di o Bus
FLYC_VCP
Battery Supply
(VP )
VCP _FILT -
INT
ADR SDA SCL RESET
CLKOUT
Digital LDOs
Digital Core
Interface
Supply (VL )
+1.8V
Internal
Supply ( VD )
+1 .8 V
TSO
DAC and Filter
VCP_FILT+
VCP_FILT -
AOUTB
REFB
DAC and Filter
VA
-VA
HPDETECT HP_DETECT


SCLK1
LRCK1
SDIN1
DSDCLK/SCLK2
DSDB/LRCLK2
DSDA/SDIN2
DS1113F1
DEC ‘16
CS4399

2DS1113F1
CS4399
General Description
The CS4399 is a high-performance, 32-bit resolution, stereo audio DAC that supports up to 384-kHz sampling frequency.
The advanced 32-bit oversampled multibit modulator with mismatch shaping technology eliminates distortion due to
on-chip component mismatch. Proprietary digital-interpolation filters support five selectable filter responses with
pseudo-linear phase and ultralow latency to minimize pre-echos and ringing artifacts. Other features include volume
control with 0.5-dB steps and digital deemphasis for 44.1-kHz sample rate.
The patented on-chip DSD processor preserves audio integrity by allowing signal processing such as volume control and
50-kHz Scarlet Book recommended filtering to be applied directly to the DSD stream without an intermediate decimation
stage. Additional features like volume matching and channel mixing enable seamless transition between DSD and PCM
playback paths.
The CS4399 accepts I2S, right-justified, left-justified, and TDM-format PCM data at sample rates from 32 to 384 kHz. The
industry-standard high-speed I2C interface capable of up to 1-MHz operation provides easy configuration control. An
integrated PLL allows for maximum clocking flexibility in any system. Popguard®technology eliminates output transients
upon power-up or power-down events.
The CS4399 is available in a commercial-grade 42-ball WLCSP or 40-pin QFN package for operation from –10°C to
+70°C.

DS1113F1 3
CS4399
Table of Contents
1 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . 4
1.1 40-Pin QFN (Top-Down, Through-Package View) . . . . . . . . . 4
1.2 42-Ball WLCSP (Top-down, Through-Package View) . . . . . . 5
1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Electrostatic Discharge (ESD) Protection Circuitry . . . . . . . . 8
2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . 11
Table 3-1. Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3-2. Recommended Operating Conditions . . . . . . . . . . . 11
Table 3-3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 12
Table 3-4. Analog Output Characteristics (HV_EN = 1) . . . . . 12
Table 3-5. Combined DAC Digital, On-Chip Analog and
AOUTx Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3-6. DAC High-Pass Filter (HPF) Characteristics . . . . . 15
Table 3-7. DSD Combined Digital and On-Chip Analog
Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3-8. Digital Interface Specifications and
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3-9. CLKOUT Characteristics . . . . . . . . . . . . . . . . . . . . . 16
Table 3-10. PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3-11. Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . 17
Table 3-12. Power-Supply Rejection Ratio (PSRR)
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3-13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3-14. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3-15. Serial-Port Interface Characteristics . . . . . . . . . . . 18
Table 3-16. DSD Switching Characteristic . . . . . . . . . . . . . . . . 19
Table 3-17. I2C Slave Port Characteristics . . . . . . . . . . . . . . . 19
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 Class H Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Headphone Presence Detect . . . . . . . . . . . . . . . . . . . . . . . 27
4.5 Clocking Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6 Clock Output and Fractional-N PLL . . . . . . . . . . . . . . . . . . . 31
4.7 Filtering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.8 Audio Serial Port (ASP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.9 DSD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.10 DSD and PCM Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.11 Standard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.12 Control Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1 PLL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3 Crystal Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.4 Alert Mixing Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.5 Enable/Disable Nonoversampling Filter . . . . . . . . . . . . . . . . 49
5.6 CS4399 Analog Output and Filtering . . . . . . . . . . . . . . . . . . 49
5.7 Audio Output Power Down Sequences . . . . . . . . . . . . . . . . 49
5.8 Audio Output Power-Up Initialization . . . . . . . . . . . . . . . . . . 51
5.9 Audio Output Power-Up Sequence . . . . . . . . . . . . . . . . . . . 52
5.10 Example Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6 Register Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.2 PLL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.3 ASP and XSP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.4 DSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.5 Analog Output and PCM Registers . . . . . . . . . . . . . . . . . . . 86
7.6 Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . 90
8 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.2 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.3 REFA and REFB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.4 QFN Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9 Performance Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.1 Digital Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.1 40-Pin QFN Package Dimensions . . . . . . . . . . . . . . . . . . 108
10.2 42-Ball WLCSP Package Dimensions . . . . . . . . . . . . . . . 109
11 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4DS1113F1
CS4399
1 Pin Assignments and Descriptions
1 Pin Assignments and Descriptions
1.1 40-Pin QFN (Top-Down, Through-Package View)
Figure 1-1. Top-Down (Through-Package) View—QFN 40-Pin Diagram
Top -Dow n ( Thr ough Package ) Vi ew
40-Pin QFN Package
21
26
27
28
29
30
22
23
24
25
7
6
5
4
3
2
1
10
9
8
1211 13 14 15 16 17 18 19 20
3940 38 37 36 35 34 33 32 31
DSDB/LRCK2
RESET
VCP
FLYP_VCP
FLYC_VCP
HP_DETECT
VCP_FILT+
SCL
SDIN1
TSO
VD
FILT+
FILT–
VA
GNDA
–VA
FLYP_VA
DSDA/SDIN2 SDA LRCK1 XTI/MCLK XTO GNDD SCLK1 CLKOUT DSDCLK/SCLK2
REFA
AOUTA
GNDCP
AOUTB
REFB
VCP_FILT–
INT
VP
VL
ADR
GNDCP
FLYN_VCP
FLYN_VA
GNDCP

DS1113F1 5
CS4399
1.2 42-Ball WLCSP (Top-down, Through-Package View)
1.2 42-Ball WLCSP (Top-down, Through-Package View)
Figure 1-2. Top-Down (Through-Package) View—42-Ball WLCSP Package
VL SCLK1 XTO XTI/MCLK DSDA/
SDIN2
SDIN1
DSDCLK/
SCLK2
CLKOUT LRCK1 SDA SCL TSO
DSDB/
LRCK2
ADR GNDD RESET INT VD
VP VCP TSI FILT+ FILT– VA
FLYP_VCP VCP_FILT+ REFB REFA GNDA –VA
FLYC_VCP GNDCP GNDCP HP_DETECT TSI FLYP_VA
FLYN_VCP VCP_FILT– AOUTB AOUTA GNDCP FLYN_VA
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
Charge Pump Analog I/O Digital I/OGround Power Supplies Te s t

6DS1113F1
CS4399
1.3 Pin Descriptions
1.3 Pin Descriptions
Table 1-1. Pin Descriptions
Pin Name QFN
Pin #
WLCSP
Ball
Power
Supply I/O Pin Description Internal
Connection
Digital I/O
Driver
Digital I/O
Receiver
ADR 30 C2 VL I Address Bit (I²C). In I²C Mode, ADR is a chip address pin. — — —
CLKOUT 33 B2 VL O CLK Output. Single-ended clock output sourced from PLL or
buffered crystal.
Weak
pull-down
CMOS
output
—
SCLK1 34 A2 VL I/O Serial Audio Input Bit Clock 1. Serial bit clock for audio data on
the SDIN pins.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
LRCK1 38 B3 VL I/O Serial Audio Input Left/Right Clock. Word-rate clock for the
audio data on the SDIN pins.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
SDIN1 2 A6 VL I Serial Audio Input Data Port. Audio data serial input pin 1. Weak
pull-down
— Hysteresis
on CMOS
input
DSDA/
SDIN2
40 A5 VL I DSD Data Input A/Serial Data In 2. DSD audio or PCM audio
data serial input pin 2.
Weak
pull-down
— Hysteresis
on CMOS
input
DSDB/
LRCK2
29 C1 VL I/O DSD Data Input B/Serial Audio Input Left/Right Clock 2. DSD
audio data serial input pin or word rate clock for the audio data on
the SDIN2 pin.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
DSDCLK/
SCLK2
32 B1 VL I/O DSD Clock Input/Serial Audio Input Bit Clock 2. DSD clock
input. Serial bit clock for audio data on the SDIN2 pin.
Weak
pull-down
CMOS
output
Hysteresis
on CMOS
input
INT 27 C5 VP O Interrupt. When pulled up, works as system interrupt pin. Open
drain, active low programmable.
—CMOS
open-drain
output
—
RESET 28 C4 VP I System Reset. The device enters system reset when enabled. — — Hysteresis
on CMOS
input
SDA 39 B4 VL I/O Serial Control Data I/O (I²C). In I²C Mode, SDA is the control I/O
data line.
—CMOS
open-drain
output
Hysteresis
on CMOS
input
SCL 1 B5 VL I Software Clock (I²C). Serial control interface clock used to clock
control data bits into and out of the CS4399.
— — Hysteresis
on CMOS
input
XTI/MCLK 37 A4 VL I Crystal/Oscillator Input/MCLK In. Crystal or digital clock input
for the master clock.
Weak
pull-down
— Hysteresis
on CMOS
input
XTO 36 A3 VL O Crystal/Oscillator Output. Crystal output. Weak
pull-down
CMOS
output
—
FILT+
FILT–
5
6
D4
D5
VA O Positive/Negative Voltage Reference. Positive/negative
reference voltage for DAC.
———
HP_
DETECT
22 F4 VP I Headphone Detect. Can be configured to be debounced on
unplugged and plugged events before it is presented as a
noninterrupt status bit (HPDETECT).
—Hi-Z—
AOUTB
AOUTA
16
14
G3
G4
VCP_
FILT±
OAudio Output. Refer to analog specification table for full-scale
output level.
———
REFB
REFA
17
13
E3
E4
VCP_
FILT±
IOutput Reference. Reference for analog output. — — —
VL 31 A1 N/A I Logic Power. Input/Output power supply, typically +1.8 V. — — —
VD 4 C6 N/A I Internal Digital Power. Internal digital power supply, typically
+1.8 V.
———
VA 7 D6 N/A I Analog Power. Power supply for the internal analog section. — — —
VCP 25 D2 N/A I Charge Pump Supply. Provides charge pump voltage to the
analog output circuit.
———
VP 26 D1 N/A I Battery supply. Provides voltage to the Class H circuit. — — —
Digital I/O
Analog I/O
Power Supplies

DS1113F1 7
CS4399
1.3 Pin Descriptions
GNDD 35 C3 N/A I Digital and I/O Ground. Ground for the I/O and core logic. GNDA,
GNDCP, GNDD must be connected to a common ground area
under the chip.
———
GNDA 8 E5 N/A I Analog Ground. Ground reference for the internal analog section.
GNDA, GNDCP, GNDD must be connected to a common ground
area under the chip.
———
GNDCP 12, 15,
19
F2, F3,
G5
N/A I Charge Pump Ground. Ground reference for the charge pump
section. GNDA, GNDCP, GNDD must be connected to a common
ground area under the chip.
———
VCP_FILT+
VCP_FILT–
21
18
E2
G2
VCP/
VP 1
I/O Inverting Charge Pump Filter Connection. Power supply from
the inverting charge pump that provides the positive/negative rail
for the analog output. When operating in external VCP_FILT
mode, these pins can directly take in supply voltage.
———
–VA 9 E6 VA O VA Negative Charge Pump Output. Negative charge pump
output for DAC rail. It is derived from VA.
———
FLYP_VA
FLYN_VA
10
11
F6
G6
VA O –VA Charge Pump Cap Positive/Negative Node. Positive/
negative nodes for the DAC negative charge pump’s flying
capacitor.
———
FLYP_VCP 24 E1 VCP/
VP 1
O–VCP Charge Pump Cap Positive Node. Positive node for the
analog output negative charge pump’s flying capacitor.
———
FLYC_VCP 23 F1 VCP/
VP 1
O–VCP Charge Pump Cap Center Node. Center node for the
analog output negative charge pump’s flying capacitor.
———
FLYN_VCP 20 G1 VCP_
FILT±
O–VCP Charge Pump Cap Negative Node. Negative node for the
analog output negative charge pump’s flying capacitor.
———
TSO 3 B6 N/A I/O Test Output. ———
TSI — D3, F5 Test Input. ———
1.The power supply is determined by ADPT_PWR setting (see Section 4.3.1). VP is used if ADPT_PWR = 001 (VP_LDO Mode) or when necessary for
ADPTPWR = 111 (Adapt-to-Signal Mode).
Table 1-1. Pin Descriptions (Cont.)
Pin Name QFN
Pin #
WLCSP
Ball
Power
Supply I/O Pin Description Internal Connection
Digital I/O
Driver
Digital I/O
Receiver
Ground
Charge Pump
Test

8DS1113F1
CS4399
1.4 Electrostatic Discharge (ESD) Protection Circuitry
1.4 Electrostatic Discharge (ESD) Protection Circuitry
Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the
substrate (GND), as well as the interrelations between some domains. Note that this figure represents the structure for the
internal protection devices and that additional protections can be implemented as part of the integration into the board.
Figure 1-3. Composite ESD Topology
Table 1-2 shows the individual ESD domains and lists the pins associated with each domain.
ESD-sensitive device. The CS4399 is manufactured on a CMOS process. Therefore, it is generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while
handling and storing this device. This device is qualified to current JEDEC ESD standards.
Table 1-2. ESD Domains
ESD Domain Signal Name
(See * in Topology Figures for Pad) Topology
VL/GNDD ADR
DSDCLK/SCLK2
SCL
SDA
DSDB/LRCK2
DSDA/SDIN2
SDIN1
LRCK1
SCLK1
CLKOUT
XTI/MCLK
XTO
VL
GNDD
Substrate
VD VA
–VA
VP
*
*
VCP_FILT+
GNDCP
VCP_FILT–
*
*
VCP
GNDA
VP/GNDCP Domain
VP/VCP_FILT– Domain
VCP_FILT+/VCP_FILT– Domain
*
VL
GNDD
Substrate
*

DS1113F1 9
CS4399
1.4 Electrostatic Discharge (ESD) Protection Circuitry
VA/–VA FLYN_VA
FLYP_VA
FILT+
FILT–
VP/GNDCP RESET
INT
VP/VCP_FILT– FLYP_VCP
FLYC_VCP
HP_DETECT
VCP_FILT+/
VCP_FILT–
FLYN_VCP
AOUTA
AOUTB
REFA
REFB
Table 1-2. ESD Domains (Cont.)
ESD Domain Signal Name
(See * in Topology Figures for Pad) Topology
VA
–VA
GNDA
Substrate
*
VP
*
VCP_FILT+
GNDCP
VCP_FILT–
Substrate
*
*
VP/GNDCP Domain
VP/VCP_FILT– Domain
VCP_FILT+/VCP_FILT– Domain

10 DS1113F1
CS4399
2 Typical Connection Diagram
2 Typical Connection Diagram
Figure 2-1. Typical Connection Diagram
Note:
1. The value for RP_I can be determined by the interrupt pin specification in Table 3-8.
All external passive component
values shown are nominal.
Key for Capacitor Types Required:
* Use low ESR, X7R/X5R capacitors
If no type symbol is shown next to a
capacitor, any type may be used.
** Use C0G capacitors.
Analog
Signal
Conditioning
GNDD GNDA
VA
+1.8 V
CS4399
VL
FLYN_VA
FLYP_VA
2.2 µF
*
-VA
OUTA
OUTB
HPREFA
Headphone
Connector
123
*
2.2 µF
0.1 µF
HPREFB
FLYN_VCP
FLYP_VCP
CLKOUT
Audio
Devices
XTI / MCLK
XTO
See Clocking
Configuration
FILT-
FILT+
15 µF
*
Battery
(3.0 V—5.25 V)
*
2.2 µF
FLYC_VCP
VP
+1.8 V
2.2 µF
*
2.2 µF
*
*
4.7 µF
RESET
Applications
Processor /
Micro-
Controller
INT
R
P_I
VL
ADR
SDA
SCL
VD
0.1 µF
*
15 µF
*
Clocking Configuration
XTAL
External MCLK
System
Clock XTI/MCLK
XTO
*0.1 µF
*
AOUTA
REFA
AOUTB
REFB
HP_DETECT
VCP_FILT+
GNDCP
VCP
VCP_FILT–
See
VCP_FILT
Configuration
VCP_FILT Configuration
EXT_VCPFILT=1EXT_VCPFILT=0
VCP_FILT+
GNDCP
VCP
+1.8 V
VCP_FILT–
2.2 µF
*
2.2 µF
*
2.2 µF
*
VCP_FILT+
GNDCP
VCP
+1.8 V
VCP_FILT–
2.2 µF
*2.2 µF
*
2.2 µF
*
+3.0V
-3.0V
*
2.2 µF
FLYN_VCP
FLYP_VCP
FLYC_VCP
*
2.2 µF
FLYN_VCP
FLYP_VCP
*
2.2 µF
FLYC_VCP
NC
XTI/MCLK
XTO
SCLK1
LRCK1
SDIN1
DSDCLK/SCLK2
DSDB/LRCLK2
DSDA/SDIN2
**
**
PCM / DoP
Digital Audio
Source
DoP / DSD
Digital Audio
Source
1

DS1113F1 11
CS4399
3 Characteristics and Specifications
3 Characteristics and Specifications
Table 3-1 defines parameters as they are characterized in this section.
Table 3-1. Parameter Definitions
Parameter Definition
Dynamic range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. A
signal-to-noise ratio measurement over the specified bandwidth made with a –60-dB signal; 60 dB is added to resulting
measurement to refer the measurement to full scale. This technique ensures that distortion components are below the
noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering
Society, AES17–1991, and the Electronic Industries Association of Japan, EIAJ CP–307. Dynamic range is expressed in
decibel units.
Gain drift The change in gain value with temperature, expressed in ppm/°C units.
Idle channel noise The rms value of the signal with no input applied (properly back-terminated analog input, digital zero, or zero modulation
input). Measured over the specified bandwidth.
Interchannel gain
mismatch
The gain difference between left and right channel pairs. Interchannel gain mismatch is expressed in decibel units.
Interchannel
phase mismatch
The phase difference between left and right channel pairs at
997-Hz sine wave input . Interchannel phase mismatch is ex-
pressed in degree units (with respect to
997-Hz sine wave input) .
Interchannel
isolation
A measure of cross talk between the left and right channel pairs. Interchannel isolation is measured for each channel at
the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Interchannel
isolation is expressed in decibel units.
Load resistance
and capacitance
The recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal
integrity. The load capacitance effectively moves the band-limiting pole of the amp in the output stage. Increasing load ca-
pacitance beyond the recommended value can cause the internal op-amp to become unstable.
Output offset
voltage
The DC offset voltage present at the amplifier’s output when its input signal is in a mute state. The offset exists due to
CMOS process limitations and is proportional to analog volume settings. When measuring the offset out of the headphone
amplifier, the headphone amplifier is ON.
Total harmonic
distortion + noise
(THD+N)
The ratio of the rms sum of distortion and noise spectral components across the specified bandwidth (typically 20 Hz–20
kHz) relative to the rms value of the signal. THD+N is measured at –1 and –20 dBFS for the analog input and at 0 and
–20 dB for the analog output, as suggested in AES17–1991 Annex A. THD+N is expressed in decibel units.
Turn-on time Turn-on time is measured from when the PDN_HP = 0 ACK signal is received to when the signal appears on the HP output.
Table 3-2. Recommended Operating Conditions
GNDD = GNDA = 0 V, all voltages with respect to ground.
Parameters 1
1.Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of
these limits may adversely affect device reliability.
Symbol Minimum Maximum Units
DC power supply Analog VA 1.66 1.94 V
Charge pump VCP 1.66 1.94 V
Filtered charge pump EXT_VCPFLT = 1 VCP_FILT+ 2.85 3.15 V
VCP_FILT– –3.15 –2.85 V
Battery supply HV_EN = 0, EXT_VCPFILT = 0
HV_EN = 1, EXT_VCPFILT = 0
EXT_VCPFILT = 1
VP 3.0
3.3
3.3
5.25
5.25
5.25
V
V
V
Digital Interface VL 1.66 1.94 V
Digital Internal VD 1.66 1.94 V
External voltage
applied to pin2,3
2.The maximum over/undervoltage is limited by the input current.
3.Table 1-1 lists the power supply domain in which each CS4399 pin resides.
HP_DETECT pin
VCP_FILT± domain pins 4
VL domain pins
VA domain pins
VP domain pins
4.VCP_FILT± is specified in Table 3-13.
VINHI
VVCPF
VVL
VVA
VVP
–0.3 – VCP_FILT–
–0.3 – VCP_FILT–
–0.3
–0.3
–0.3
VP + 0.3
0.3 + VCP_FILT+
VL + 0.3
VA + 0.3
VP + 0.3
V
V
V
V
V
Ambient temperature TA–10 +70 C

12 DS1113F1
CS4399
3 Characteristics and Specifications
Table 3-3. Absolute Maximum Ratings
GNDD = GNDA= GNDCP = 0 V; all voltages with respect to ground.
Parameters Symbol Minimum Maximum Units
DC power supply Analog
Battery
Charge pump
Filtered charge pump (positive)
Filtered charge pump (negative)
Digital interface
Digital internal
VA
VP
VCP
VCP_FILT+
VCP_FILT–
VL
VD
–0.3
–0.3
–0.3
–0.3
0.3
–0.3
–0.3
2.33
6.3
2.33
3.3
–3.3
2.33
2.33
V
V
V
V
V
V
V
Input current 1
1.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins do not cause SCR latch-up.
Iin —±10mA
Ambient operating temperature (power applied) TA–50 +115 °C
Storage temperature Tstg –65 +150 °C
Caution: Stresses beyond “Absolute Maximum Ratings” levels may cause permanent damage to the device. These levels are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in Tab le 3 -2, “Recommended Operating
Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3-4. Analog Output Characteristics (HV_EN = 1) 1
Test conditions (unless otherwise specified): Fig. 2-1 shows CS4399 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified
otherwise);
GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with VA =
VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK = 44.1-kHz mode);
PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency f
XTAL
= 22.5792 MHz); Volume = 0 dB; when testing in DSD processor
mode, DSD_ZERODB = 1
; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx .
PCM and DSD Processor Mode Parameter 2,3,4 Minimum Typical Maximum Units
AOUTx
RL= 10 k
CL= 200 pF
OUT_FS = 11
Volume = 0 dB 5,
unless otherwise
specified
Dynamic range
(defined in Table 3-1)
24-bit, 32-bit, DSD
16-bit
A-weighted
Unweighted
A-weighted
Unweighted
124
121
91
88
130
127
97
94
—
—
—
—
dB
dB
dB
dB
THD+N
(defined in Table 3-1)
24-bit, 32-bit, DSD
16-bit
0 dB
–20 dB
–60 dB
0 dB
–20 dB
–60 dB
—
—
—
—
—
—
–108
–97
–67
–94
–74
–34
–101
—
–61
–88
—
–28
dB
dB
dB
dB
dB
dB
Idle channel noise
(A-weighted)
(defined in Table 3-1)
24-bit, 32-bit, DSD — 0.55 — µV
Full-scale output voltage 4.66 4.90 5.14 Vpp
Interchannel isolation 6(defined in Table 3-1) 217 Hz
1 kHz
20 kHz
—
—
—
110
95
68
—
—
—
dB
dB
dB
AOUTx
RL= 600 
CL= 200 pF
OUT_FS = 11
Volume = 0 dB 5,
unless otherwise
specified
Dynamic range
(defined in Table 3-1)
24-bit, 32-bit, DSD
16-bit
A-weighted
Unweighted
A-weighted
Unweighted
124
121
91
88
130
127
97
94
—
—
—
—
dB
dB
dB
dB
THD+N
(defined in Table 3-1)
24-bit, 32-bit, DSD
16-bit
0 dB
–20 dB
–60 dB
0 dB
–20 dB
–60 dB
—
—
—
—
—
—
–108
–97
–67
–94
–74
–34
–101
—
–61
–88
—
–28
dB
dB
dB
dB
dB
dB
Idle channel noise
(A-weighted)
(defined in Table 3-1)
24-bit, 32-bit, DSD — 0.55 — µV
Full-scale output voltage 4.66 4.90 5.14 Vpp
Output power — 5 — mW
Interchannel isolation 6(defined in Table 3-1) 217 Hz
1 kHz
20 kHz
—
—
—
110
95
68
—
—
—
dB
dB
dB

DS1113F1 13
CS4399
3 Characteristics and Specifications
Other characteristics
for AOUTx Interchannel gain mismatch (defined in Tab l e 3 - 1)—±0.1—dB
Interchannel phase mismatch (defined in Table 3-1)—±0.05—°
Output offset voltage: Mute (defined in Table 3-1)—±0.5±1mV
Gain drift (defined in Tabl e 3- 1 ) — ±100 — ppm/°C
Load resistance (RL)600——
Load capacitance (CL)——1nF
Turn-on time (defined in Tab le 3- 1)——10ms
Click/pop during PDN_HP enable or disable A-weighted — — –60 dBV
1. This table also applies to external VCP_FILT supply mode: CS4399 power up procedure is per description in Section 5.10.1; EXT_VCPFILT = 1; VCP_
FILT+ and VCP_FILT– comply to Tab l e 3 - 2 when
EXT_VCPFILT = 1 ; in this mode, HV_EN setting becomes don’t care.
2.One LSB of triangular PDF dither is added to PCM data.
3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table.
4.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index.
5.The volume must be configured as indicated to achieve specified output characteristics.
6.Output test configuration. Symbolized component values are specified in the test conditions.
Table 3-5. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics
Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired
sample rate by multiplying the given characteristic by Fs. Single-Speed Mode refers to 32-, 44.1-, and 48-kHz sample rates. Double-Speed Mode refers
to 88.2- and 96-kHz sample rates. Quad-Speed Mode refers to 176.4- and 192-kHz sample rates. Octuple-Speed Mode refers to 352.8- and 384-kHz
sample rates. MCLK_INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay.
Parameter Minimum Typical Maximum Units
Fast Roll-Off
(FILTER_SLOW_FASTB =0)
Single-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
8.44 3
—
—
—
0.4535 4
0.49
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner 5–0.01 — +0.01 dB
Stopband 0.547 — — Fs
Stopband attenuation 6PHCOMP_LOWLATB =0
PHCOMB_LOWLATB = 1
110 7
105
—
—
—
—
dB
dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 39.5/Fs 8—s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 6.3/Fs 9—s
Deemphasis error 10
(Relative to 1 kHz) Fs = 44.1 kHz — — ±0.14 dB
Fast Roll-Off
(FILTER_SLOW_FASTB =0)
Double-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
7.77
—
—
—
0.227
0.48
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB
Stopband 0.583 — — Fs
Stopband attenuation 680 — — dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 22.3/Fs — s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 7.5/Fs — s
Table 3-4. Analog Output Characteristics (HV_EN = 1) 1(Cont.)
Test conditions (unless otherwise specified): Fig. 2-1 shows CS4399 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified
otherwise);
GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with VA =
VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK = 44.1-kHz mode);
PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency f
XTAL
= 22.5792 MHz); Volume = 0 dB; when testing in DSD processor
mode, DSD_ZERODB = 1
; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx .
PCM and DSD Processor Mode Parameter 2,3,4 Minimum Typical Maximum Units
Test Load
AOUTA CLA
REFA
RLA
Measurement
Device
–
+
–
+AOUTB
REFB
CH1
CH2
CLB RLB

14 DS1113F1
CS4399
3 Characteristics and Specifications
Fast Roll-Off
(FILTER_SLOW_FASTB =0)
Quad-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
9.44
—
—
—
0.114
0.46
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB
Stopband 0.583 — — Fs
Stopband attenuation 680 — — dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 20.7/Fs — s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 11.3/Fs — s
Slow Roll-Off
(FILTER_SLOW_FASTB =1)
Single-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
6.45 11
—
—
—
0.417
0.49
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner 5–0.01 — +0.01 dB
Stopband 0.583 — — Fs
Stopband attenuation 664 — — dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 34.5/Fs
12 —s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 5.6/Fs 13 —s
Deemphasis error 10
(Relative to 1 kHz)
Fs = 44.1 kHz — — ±0.14 dB
Slow Roll-Off
(FILTER_SLOW_FASTB =1)
Double-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
7
—
—
—
0.208
0.458
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB
Stopband 0.792 — — Fs
Stopband attenuation 670 — — dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 22.3/Fs — s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 6.7/Fs — s
Slow Roll-Off
(FILTER_SLOW_FASTB =1)
Quad-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
7.00
—
—
—
0.104
0.43
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner –0.01 — 0.01 dB
Stopband 0.792 — — Fs
Stopband attenuation 675 — — dB
Group delay (linear phase) PHCOMB_LOWLATB = 1 — 20.7/Fs — s
Group delay (minimum phase) PHCOMB_LOWLATB = 0 — 10.6/Fs — s
Nonoversampling (NOS)
(NOS =1)
Single-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
0
0
—
—
0.026
0.444
Fs
Fs
Passband droop 10 Hz to 20 kHz — — 3.2 14 dB
Group delay — 2.7/Fs — s
Nonoversampling (NOS)
(NOS =1)
Double-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
0
0
—
—
0.0246
0.446
Fs
Fs
Passband droop 10 Hz to 20 kHz — — 0.73 dB
Group delay — 4.5/Fs — s
Nonoversampling (NOS)
(NOS =1)
Quad-Speed Mode 1
Passband 2to –0.01-dB corner
to –3-dB corner
0
0
—
—
0.026
0.405
Fs
Fs
Passband droop 10 Hz to 20 kHz — — 0.167 dB
Group delay — 8.4/Fs — s
Octuple-Speed Mode 1 Passband 2to –0.01-dB corner
to –3-dB corner
0
0
—
—
0.0299
0.302
Fs
Fs
Passband droop 10 Hz to 20 kHz — — 0.037 dB
Group delay — 17/Fs — s
1. Filter response is by design.
2. Response is clock-dependent and scales with Fs.
3. 8.5 dB for 32-kHz sample rate.
4. 0.454 Fs for 32-kHz sample rate.
5. Filter ripple specification is invalid with deemphasis enabled.
Table 3-5. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics (Cont.)
Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired
sample rate by multiplying the given characteristic by Fs. Single-Speed Mode refers to 32-, 44.1-, and 48-kHz sample rates. Double-Speed Mode refers
to 88.2- and 96-kHz sample rates. Quad-Speed Mode refers to 176.4- and 192-kHz sample rates. Octuple-Speed Mode refers to 352.8- and 384-kHz
sample rates. MCLK_INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay.
Parameter Minimum Typical Maximum Units

DS1113F1 15
CS4399
3 Characteristics and Specifications
6. For Single-Speed Mode, the measurement bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the measurement bandwidth is from stopband to 1.34 Fs.
7.105 dB for 32-kHz sample rate.
8. 39/Fs for 32-kHz sample rate.
9. 5.9/Fs for 32-kHz sample rate.
10. Deemphasis is available only in 44.1 kHz.
11. 6.5 dB for 32-kHz sample rate.
12. 34/Fs for 32-kHz sample rate.
13. 5.2/Fs for 32-kHz sample rate.
14. 3.9 dB for 32-kHz sample rate (passband droop 10 Hz to 15 kHz).
Table 3-6. DAC High-Pass Filter (HPF) Characteristics
Test conditions (unless specified otherwise): Gains are all set to 0 dB; TA= +25°C.
Parameter 1
1.Response scales with Fs in PCM Mode. Specifications are normalized to Fs and are denormalized by multiplying by Fs. For DSD Mode, Fs is 44.1 kHz.
Minimum Typical Maximum Units
Passband 2
2.For PCM Single-Speed Mode, N = 1.
For PCM Double-Speed Mode, N = 2.
For PCM Quad-Speed Mode, N = 4.
For PCM Octuple-Speed Mode, N = 8.
For DSD 64 x Fs Mode, N = 1.
For DSD 128 x Fs Mode, N = 1.
–0.05-dB corner
–3.0-dB corner
—
—
0.18 x 10-3/N
19.5 x 10-6/N
—
—
Fs
Fs
Passband ripple (0.417x10-3/N Fs to 0.417/N Fs; normalized to 0.417/N Fs) 2— — 0.01 dB
Phase deviation @ 0.453x10-3/N Fs 2—2.45—°
Filter settling time 3
3.Required time for the magnitude of the DC component present at the output of the HPF to reach 5% of the applied DC signal.
— 0.56 4
4.Filter settling time is 0.775 seconds at Fs = 32 kHz.
—s
Table 3-7. DSD Combined Digital and On-Chip Analog Filter Response 1
Test conditions (unless specified otherwise): Digital gains are all set to 0 dB; TA= +25°C;
PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00
(crystal frequency f
XTAL
= 22.5792 MHz).
1.Filter response is by design.
Parameter Minimum Typical Maximum Units
DSD Processor Mode Passband to –3-dB corner — 50 — kHz
Frequency response 20 Hz to 20 kHz –0.05 — 0.05 dB
Roll-off 27 — — dB/Oct

16 DS1113F1
CS4399
3 Characteristics and Specifications
Table 3-8. Digital Interface Specifications and Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground;
parameters can vary with VL and VP; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; min/max performance
data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; TA= +25°C; CL=60pF.
Parameters 1
1.See Table 1-1 for serial and control-port power rails.
Symbol Minimum Maximum Units
Input leakage current 2,3
2.Specification is per pin.
3.Includes current through internal pull-up or pull-down resistors on pin.
LRCK1, DSDB/LRCK2
SDIN1, SCLK1, DSDA/SDIN2, DSDCLK/SCLK2
HP_DETECT
SDA, SCL
INT, RESET
Iin —
—
—
—
—
±4
±3
±100
±100
±100
µA
µA
nA
nA
nA
Internal weak pull-down — 550 2450 k
Input capacitance — — 10 pF
INT current sink (VOL = 0.3 V maximum) —825—µA
VL Logic (non-I2C) High-level output voltage (IOH = –100 µA)
Low-level output voltage
High-level input voltage
Low-level input voltage
VOH
VOL
VIH
VIL
0.9•VL
—
0.7•VL
—
—
0.1•VL
—
0.3•VL
V
V
V
V
VL Logic (I2C only) Hysteresis voltage (Fast Mode and Fast Mode Plus)
Low-level output voltage
High-level input voltage
Low-level input voltage
VHYS
VOL
VIH
VIL
0.05•VL
—
0.7•VL
—
—
0.2•VL
—
0.3•VL
V
V
V
V
HP_DETECT 4
4.The HP_DETECT input circuit allows the HP_DETECT signal to be as low of a voltage as VCP_FILT– and as high as VP. Section 4.4.1 provides
configuration details.
High-level input voltage
Low-level input voltage
VIH
VIL
0.93•VP
—
—
2.0
V
V
HP_DETECT current to VCP_FILT– 4IHP_DETECT 1.00 2.91 µA
Table 3-9. CLKOUT Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; CL= 60 pF; PLL reference input must meet the phase-noise mask specified in Fig. 4-12; TA = +25°C; Output jitter is measured from 100 Hz
to half of the output frequency.
Parameters Symbol Minimum Typical Maximum Units
CLKOUT output frequency fCLKOUT 2.8224
5.6448
7.5264
11.2896
3
6
8
12
3.072
6.144
8.192
12.288
MHz
MHz
MHz
MHz
CLKOUT output duty cycle — 40 50 60 %
CLKOUT output TIE jitter (RMS) CLKOUT_SRC_SEL = 01 tJIT —500—ps
Table 3-10. PLL Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; PLL reference input must meet the phase-noise mask specified in Fig. 4-12; TA = +25°C.
Parameters Symbol Minimum Typical Maximum Units
PLL output frequency fout 22.5792 24 24.576 MHz
PLL lock time tLock — 620 1000 µs
PLL reference clock input — —
—
—
—
—
—
—
—
—
—
11.2896
22.5792
12.2880
24.5760
9.6000
19.2000
12.0000
24.0000
13.0000
26.000
—
—
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL reference clock input jitter — — — 50 ps

DS1113F1 17
CS4399
3 Characteristics and Specifications
Table 3-11. Crystal Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; TA = +25°C
Parameters 1
1.Refer to Section 5.3 for supported crystal options.
Symbol Minimum Typical Maximum Units
Crystal oscillator frequency fXTAL 22.57 22.5792/ 24.576 24.58 MHz
Crystal load capacitance CL_XTAL 5—8pF
Equivalent series resistance esrXTAL ——100
Startup time tXTAL_pup —— 8ms
Shunt capacitance CO——0.8pF
Maximum drive level — 200 — — µW
Table 3-12. Power-Supply Rejection Ratio (PSRR) Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; input test signal held low (all zero data); GNDA = GNDL = GNDCP =
0 V; voltages are with respect to ground; VL = VA = VD = 1.8 V, VP = 3.6 V;
When testing PSRR, PCM input test signal held low (all zero data); TA=
+25°C; PCM_AMUTE = 0.
Parameter 1
1.PSRR test configuration: Typical PSRR can vary by approximately 6 dB below
the indicated values.
Minimum Typical Maximum Units
AOUTx
PSRR with 100-mVpp signal AC coupled to VA supply
217 Hz
1 kHz
20 kHz
—
—
—
75
75
70
—
—
—
dB
dB
dB
AOUTx
PSRR with 100-mVpp signal AC coupled to VCP supply
217 Hz
1 kHz
20 kHz
—
—
—
80
80
60
—
—
—
dB
dB
dB
AOUTx
PSRR with 100-mVpp signal AC coupled to VP supply
217 Hz
1 kHz
20 kHz
—
—
—
100
100
80
—
—
—
dB
dB
dB
Table 3-13. DC Characteristics
Test conditions (unless otherwise specified): Fig. 2-1 shows CS4399 connections; GNDD = GNDA = 0 V; all voltages with respect to ground.
Parameters Minimum Typical Maximum Units
VCP_FILT (No load connected to AOUTx)
EXT_VCPFILT = 0
VP_LDO Mode VCP_FILT+ pin (HV_EN = 1)
VCP_FILT+ pin (HV_EN = 0)
VCP_FILT– pin (HV_EN = 1)
VCP_FILT– pin (HV_EN = 0)
—
—
—
—
3.0
2.6
–3.0
–2.6
—
—
—
—
V
V
V
V
VCP Mode VCP_FILT+ pin
VCP_FILT– pin
—
—
VCP
–VCP
—
—
V
V
–VA –VA pin — – VA — V
Other DC filter characteristics FILT+ voltage — –0.35 — V
FILT– voltage — 0.35 — V
Analog output current limiter on threshold. — 120 160 mA
VD power-on
reset threshold
(VPOR)
Up
Down
—
—
1.15
0.950
—
—
V
V
Operational Amplifier
OUT
GND
Power DAC
OUT
GND
PWR
DUT
+5 V +5 V
++––
+
–
OUT Analog Generator Analog Analyzer
Analog Test Equipment
Analog Output PSRR

18 DS1113F1
CS4399
3 Characteristics and Specifications
Table 3-14. Power Consumption
Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;
performance data taken with VA = VCP = VD = VL = 1.8 V; VP = 3.6 V; TA= +25°C; ASP_SPRATE = 0001(44.1-kHz mode); MCLK_INT= 1
(22.5792 MHz); MCLK_SRC_SEL = 00; all other fields are set to defaults; no signal on any input; control port inactive; all serial ports are set to Slave or
Master Mode as indicated, input clock/data are held low unless active; test load is RL= 600 and CL= 1 nF for AOUTx; measured values include currents
consumed by the DAC and do not include current delivered to external loads unless specified otherwise (e.g., from AOUTx outputs); see
Fig. 2-1 .
Use Cases
Typical Current (µA) Total
Power
(µW)
POUT iVCP iVA iVD iVL iVP
1Off
1
1.Off configuration: Clock/data lines held low; RESET = LOW; VA = VD = VL = 0 V, VCP = 0 V, VP = 3.6 V.
—0000622
2 Standby 2
2.Standby configuration: Clock/data lines held low; RESET = HIGH; VA = VD = VL = 1.8 V, VCP = 1.8 V, VP = 3.6 V; HP_DETECT_CTRL = 11 (enabled);
HPDETECT_PLUG_INT_MASK=0 (unmasked); PDN_XTAL = 1, MCLK_SRC_SEL = 10 (RCO selected as MCLK source).
HPDETECT enabled — 0 0 256 0 32 576
3 A Playback External MCLK = 22.5792 MHz, I2S/DoP
Stereo AOUT
Quiescent 3
3.Quiescent configuration: data lines held low; RESET = HIGH; VA = 1.8 V, VD = VL = VCP = 1.8 V, VP = 3.6 V. Serial port, I2S/DoP Mode (ASP and
SDIN, ASP_M/Sb = 0); PDN_XTAL = 1.
4021 7302 1444 40 32 23167
Table 3-15. Serial-Port Interface Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;
parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =
1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; T
A
= +25°C; C
L
= 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at V
OL
and V
OH
thresholds
(see Table 3-8).
Parameters 1,2,3,4,5
1.MCLK in this table refers to the external clock supplied to the MCLK pin (MCLKEXT).
2.Output clock frequencies follow the master clock (MCLKEXT) frequency proportionally. Any deviation of the clock source from the nominal supported
rates are directly imparted to the output clock rate by the same factor (e.g., +100-ppm offset in the frequency of MCLKEXT becomes a +100-ppm
offset in LRCK/FSYNC and SCLK).
3.I2S interface timing
Symbol Minimum Typical Maximum Units
FSYNC frame rate Fs (See Section 4.8.5)kHz
FSYNC high period 6tHI:FSYNC 1/fSCLK — (n–1)/fSCLK s
Master
Mode FSYNC duty cycle xSP_5050 = 1 — 45 — 55 %
FSYNC delay time after SCLK launching edge 7tD:CLK–FSYNC ——20ns
SCLK frequency fSCLK ——f
MCLK_INT MHz
SCLK high period 8tHI:SCLK 1/(2•fSCLK) –
1/fMCLK_INT
—1/(2•f
SCLK) +
1/fMCLK_INT
ns
SDIN setup time before SCLK latching edge 7tSU:SDI 10 — — ns
SDIN hold time after SCLK latching edge 7tH:SDI 5——ns
Slave
Mode FSYNC setup time before SCLK latching edge 7tSU:FSYNC 10 — — ns
FSYNC hold time after SCLK latching edge 7tH:FSYNC 5——ns
SCLK frequency fSCLK ——24.58MHz
SCLK high period tHI:SCLK 16 — — ns
SCLK low period tLO:SCLK 16 — — ns
SDIN setup time before SCLK latching edge 9tSU:SDI 10 — — ns
SDIN hold time after SCLK latching edge 7tH:SDI 5——ns
SCLK
(C POL = 1 )
SDIN
t
SU:SDI
t
H:SDI
LRCK/FSYNC
t
D:CLK–FSYNC
1/Fs
...
...
f
SCLK
= N · Fs
t
SU:FSYNC
t
H:FSYNC
t
LO:SCLK
t
HI:SCLK
SCLK
(CPOL = 0)
...
1/f
SCLK
...
...
...
...
...

DS1113F1 19
CS4399
3 Characteristics and Specifications
4.TDM interface timing
(shown with xSP_FSD = 010, xSP_LCHI = 1)
5.Applies to Master and Slave Modes, unless specified otherwise.
6.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK high (xSP_LCHI) is set to
768 SCLK periods and LRCK period (xSP_LCPR) is set to 769 SCLK periods.
7.Data may be latched/launched on either the rising or falling edge of SCLK.
8.SCLK duty cycle in Master Mode depends on Master Mode clock configuration, and can vary by up to 1 MCLKEXT period.
9.
Data is latched/launched on the rising or falling edge of SCLK as determined by xSP_SCPOL_OUT, xSP_SCPOL_IN, and xSP_FSD bi ts . See the
SCLK launching specs in
Table 3-15.
Table 3-16. DSD Switching Characteristic
Test conditions (unless specified otherwise): Fig. 2-1 shows CS4399 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;
parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =
1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; T
A
= +25°C; C
L
= 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at V
OL
and V
OH
thresholds (see Table 3-8).
Parameter 1,2
1.Serial audio input interface timing
2.Phase modulation mode serial audio input interface timing
Symbol Minimum Typical Maximum Units
DSDCLK duty cycle — 40 — 60 %
DSDCLK pulse width low tSCLKL 80 — — ns
DSDCLK pulse width high tSCLKH 80 — — ns
DSDCLK frequency (64× oversampled)
(128× oversampled)
— 1.024
2.048
2.8224
5.6448
fMCLK_INT/8
fMCLK_INT/4
MHz
MHz
DSDA/DSDB valid to DSDCLK rising setup time tSDLRS 20 — — ns
DSDCLK rising to DSDA or DSDB hold time tSDH 20 — — ns
DSD clock to data transition (Phase Modulation Mode) tDPM –20 — 20 ns
Table 3-17. I2C Slave Port Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to
ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; TA= +25°C; SDA load capacitance equal to maximum value of CB= 400 pF; minimum
SDA pull-up resistance, RP(min).1
Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS4399 with
the specified load capacitance.
Parameter 2Symbol 3 Minimum Maximum Units
SCL clock frequency fSCL —1000kHz
Clock low time tLOW 500 — ns
Clock high time tHIGH 260 — ns
Start condition hold time (before first clock pulse) tHDST 260 — ns
Setup time for repeated start tSUST 260 — ns
SCLK
SDIN
t
SU :SD I
t
H: SD I
LRCK/FSYNC
t
D :C L K- FSYN C
1/f
SC L K
Don’ t Care
Fr am e location 0 Fr am e locati on N -1
1/Fs
...
...
...
f
SC L K
= N · Fs
t
SU :FSYN C
t
H: FSYN C
t
H I:FS YN C
t
LO:SCLK
t
H I:SC L K
DSDCLK
DSDA,
DSDB
tSDLRS tSDH
tSCLKL
tSCLKH
DSDCLK
(128
• Fs)
DSDCLK
(64
• Fs )
DSDA,
DSDB
t
DPM
t
DPM

20 DS1113F1
CS4399
3 Characteristics and Specifications
Rise time of SCL and SDA Standard Mode
Fast Mode
Fast Mode Plus
tRC —
—
—
1000
300
120
ns
ns
ns
Fall time of SCL and SDA Standard Mode
Fast Mode
Fast Mode Plus
tFC —
—
—
300
300
120
ns
ns
ns
Setup time for stop condition tSUSP 260 — ns
SDA setup time to SCL rising tSUD 50 — ns
SDA input hold time from SCL falling 4tHDDI 0—ns
Output data valid (Data/Ack) 5Standard Mode
Fast Mode
Fast Mode Plus
tVDDO —
—
—
3450
900
450
ns
ns
ns
Bus free time between transmissions tBUF 500 — ns
SDA bus capacitance SCL frequency = 1 MHz, VL= 1.8 V
SCL frequency ≤400 kHz
CB—
—
400
400
pF
pF
SCL/SDA pull-up resistance 1VL= 1.8 V RP350 — Ω
Pulse width of spikes to be suppressed tPS —50ns
Switching time between RCO and MCLK_INT 6— 150 — µs
Power-up delay (delay before I2C can communicate after RESET released) tPUD 1500 — µs
1.The minimum RPvalue (resistor shown in Fig. 2-1 ) is determined by using the maximum level of VL, the minimum sink current strength of its
respective output, and the maximum low-level output voltage VOL. The maximum RPvalue may be determined by how fast its associated signal must
transition (e.g., the lower the value of RP, the faster the I2C bus is able to operate for a given bus load capacitance). See I²C bus specification
referenced in Section 13.
2.All timing is relative to thresholds specified in
Table 3-8 , VIL and VIH for input signals, and VOL and VOH for output signals.
3.I²C control-port timing
4.Data must be held long enough to bridge the transition time, tF, of SCL.
5.Time from falling edge of SCL until data output is valid.
6.Upon setting MCLK_SRC_SEL and sending the I2C stop condition, the switching of RCO and other MCLK_INT sources occurs. A least wait
time as specified is required after changing MCLK_SRC_SEL and sending the I2C stop condition before the next I2C transaction is initiated.
Table 3-17. I2C Slave Port Characteristics (Cont.)
Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to
ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; TA= +25°C; SDA load capacitance equal to maximum value of CB= 400 pF; minimum
SDA pull-up resistance, RP(min).1
Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS4399 with
the specified load capacitance.
Parameter 2Symbol 3 Minimum Maximum Units
t
BUF
t
LOW
Stop
t
HDDI
t
SUD
t
SUST
t
RC
t
HDST
t
HIGH
t
HDST
t
FC
t
SUSP
Start
Repeated
Start Stop
SDA
SCL
t
VDDO