NEC MuPD754144 User manual

1995
DATA SHEET
DESCRIPTION
The µ PD754244 is a 4-bit single-chip microcontroller which incorporates the EEPROMTM for key-less entry
application.
It incorporates a 16 ×8-bit EEPROM, a 4-Kbyte mask ROM to store software, a 128 ×4-bit RAM to store the
processing data, a processing CPU, and a carrier generator which easily outputs waveforms for infrared remote
controller.
The details of functions are described in the following user’s manual. Be sure to read it before designing.
µ PD754144, 754244 User’s Manual: U10676E
FEATURES
•On-chip EEPROM: 16 ×8 bits (mapped to the data memory)
•On-chip key return reset function for key-less entry
•System clock oscillation circuit
•
µ PD754144: RC oscillator (external resistor and capacitor)
•
µ PD754244: Crystal/ceramic oscillator
•Low-voltage operation: VDD = 1.8 to 6.0 V
•Timer function (4 channels)
•Basic interval timer/watchdog timer: 1 channel
•8-bit timer counter : 3 channels
•On-chip memory
•Program memory (ROM)
4096 ×8 bits
•Data memory (static RAM)
128 ×4 bits
•Instruction execution time variable function suited for power saving.
•
µ PD754144:
4, 8, 16, 64 µ s (at fcc = 1.0-MHz operation)
•
µ PD754244:
0.95, 1.91, 3.81, 15.3
µ s (at fx = 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7 µ s (at fx = 6.0-MHz operation)
APPLICATIONS
Automotive appliances such as key-less entry, compact data carrier, etc.
Unless contextually excluded, references in this data sheet to the µPD754244 (crystal/ceramic oscillation: fX)
mean the µ PD754144.
The µ PD754144 and µ PD754244 differ in the notation of their RC oscillation: whenever fX(RC oscillation notation
for
µ PD754244) is described, fCC should be substituted for the µ PD754144.
4-BIT SINGLE-CHIP MICROCONTROLLERS
µ PD754144, 754244
MOS INTEGRATED CIRCUIT
The mark shows major revised points.
Document No. U10040EJ2V1DS00 (2nd edition)
Date Published August 2005 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
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µ PD754144, 754244
2Data Sheet U10040EJ2V1DS
ORDERING INFORMATION
Part Number Package
µ PD754144GS-xxx-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch)
µ PD754144GS-xxx-BA5-A 20-pin plastic SOP (300 mil, 1.27-mm pitch)
µ PD754144GS-xxx-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
µ PD754144GS-xxx-GJG-A 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
µ PD754244GS-xxx-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch)
µ PD754244GS-xxx-BA5-A 20-pin plastic SOP (300 mil, 1.27-mm pitch)
µ PD754244GS-xxx-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
µ PD754244GS-xxx-GJG-A 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
Remarks 1. Products with "-A" at the end of the part number are lead-free products.
2. ××× indicates ROM code suffix.
★
★
★
★
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µ PD754144, 754244
3
Data Sheet U10040EJ2V1DS
Functional Outline
Parameter µ PD754144 µ PD754244
Instruction execution time • 4, 8, 16, 64 µ s•0.95, 1.91, 3.81, 15.3 µ s
(at fcc = 1.0-MHz operation) (at fx = 4.19-MHz operation)
•0.67, 1.33, 2.67, 10.7 µ s
(at fx = 6.0-MHz operation)
On-chip Mask ROM 4096 ×8 bits (0000H-0FFFH)
memory RAM 128 ×4 bits (000H-07FH)
EEPROM 16 ×8 bits (400H-41FH)
System clock oscillator RC oscillator Crystal/ceramic oscillator
(External resistor and capacitor)
General-purpose register • 4-bit operation: 8 ×4 banks
•8-bit operation: 4 ×4 banks
Input/output CMOS input 4 On-chip pull-up resistor can be specified by mask option.
port CMOS input/output 9 On-chip pull-up resistor connection can be specified by means of software.
Total 13
Start-up time after reset 56/fcc 217/fx, 215/fx (selected by mask option)
Stand-by mode release time 29/fcc 220/fx, 217/fx, 215/fx, 213/fx
(selected by the setting of BTM)
Timer 4 channels
•8-bit timer counter
(can be used as 16-bit timer counter) : 3 channels
•Basic interval/watchdog timer : 1 channel
Bit sequential buffer 16 bits
Vectored interrupt External: 1, Internal: 5
Test input External: 1 (key return reset function available)
Standby function STOP/HALT mode
Operating ambient temperature TA= –40 to +85 °C
Operating supply voltage VDD = 1.8 to 6.0 V
Package • 20-pin plastic SOP (300 mil, 1.27-mm pitch)
•20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
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µ PD754144, 754244
4Data Sheet U10040EJ2V1DS
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................6
2. BLOCK DIAGRAM ................................................................................................................................8
3. PIN FUNCTION ..................................................................................................................................... 9
3.1 Port Pins ......................................................................................................................................9
3.2 Non-port Pins ............................................................................................................................10
3.3 Pin Input/Output Circuits .........................................................................................................11
3.4 Recommended Connection of Unused Pins .......................................................................... 12
4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE ............................................... 13
4.1 Difference between Mk I and Mk II Modes ..............................................................................13
4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 14
5. MEMORY CONFIGURATION ............................................................................................................. 15
6. EEPROM .............................................................................................................................................18
7. PERIPHERAL HARDWARE FUNCTIONS .........................................................................................19
7.1 Digital Input/Output Ports ........................................................................................................ 19
7.2 Clock Generator ........................................................................................................................19
7.3 Basic Interval Timer/Watchdog Timer .....................................................................................22
7.4 Timer Counter ...........................................................................................................................23
7.5 Programmable Threshold Port (Analog Input Port) ...............................................................27
7.6 Bit Sequential Buffer ....... 16 Bits ............................................................................................28
8. INTERRUPT FUNCTION AND TEST FUNCTION ..............................................................................29
9. STANDBY FUNCTION ........................................................................................................................31
10. RESET FUNCTION .............................................................................................................................32
10.1 Configuration and Operation Status of RESET Function ..................................................... 32
10.2 Watchdog Flag (WDF), Key Return Flag (KRF) ...................................................................... 36
11. MASK OPTION ...................................................................................................................................38
12. INSTRUCTION SETS ..........................................................................................................................39
13. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48
13.1 µ PD754144 .................................................................................................................................48
13.2 µ PD754244 .................................................................................................................................56
14. CHARACTERISTICS CURVES (REFERENCE VALUES) .................................................................67
14.1 µ PD754144 .................................................................................................................................67
14.2 µ PD754244 .................................................................................................................................69
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µ PD754144, 754244
5
Data Sheet U10040EJ2V1DS
15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES) .....72
16. PACKAGE DRAWINGS ......................................................................................................................76
17. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 78
APPENDIX A. COMPARISON OF FUNCTIONS AMONG µ PD754144, 754244, AND 75F4264 ........... 81
APPENDIX B. DEVELOPMENT TOOLS .................................................................................................82
APPENDIX C. RELATED DOCUMENTS ................................................................................................ 85
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µ PD754144, 754244
6Data Sheet U10040EJ2V1DS
1. PIN CONFIGURATION (TOP VIEW)
• µ PD754144
•20-pin Plastic SOP (300 mil, 1.27-mm pitch)
µ PD754144GS-×××-BA5
µ PD754144GS-×××-BA5-A
•20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch)
µ PD754144GS-×××-GJG
µ PD754144GS-×××-GJG-A
IC: Internally Connected (Connect to VDD directly)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
CL1
CL2
VSS
IC
VDD
P60/AVREF
P61/INT0
P62/PTH00
P63/PTH01
KRREN
P80
P30/PTO0
P31/PTO1
P32/PTO2
P33
P70/KR4
P71/KR5
P72/KR6
P73/KR7
★
★
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µ PD754144, 754244
7
Data Sheet U10040EJ2V1DS
• µ PD754244
•20-pin Plastic SOP (300 mil, 1.27-mm pitch)
µ PD754244GS-×××-BA5
µ PD754244GS-×××-BA5-A
•20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch)
µ PD754244GS-×××-GJG
µ PD754244GS-×××-GJG-A
IC: Internally Connected (Connect to VDD directly)
Pin Identification
AVREF : Analog reference P70 to P73 : Port 7
CL1 and CL2 : System clock (RC) P80 : Port 8
IC : Internally connected PTH00 and PTH01 : Programmable threshold port analog inputs 0 and 1
INT0 : External vectored interrupt 0 PTO0 to PTO2 : Programmable timer outputs 0 to 2
KR4 to KR7 : Key returns 4 to 7 RESET : Reset
KRREN : Key return reset enable VDD : Positive power supply
P30 to P33 : Port 3 VSS : Ground
P60 to P63 : Port 6 X1 and X2 : System clock (crystal/ceramic)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
X1
X2
V
SS
IC
V
DD
P60/AV REF
P61/INT0
P62/PTH00
P63/PTH01
KRREN
P80
P30/PTO0
P31/PTO1
P32/PTO2
P33
P70/KR4
P71/KR5
P72/KR6
P73/KR7
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µ PD754144, 754244
8Data Sheet U10040EJ2V1DS
2. BLOCK DIAGRAM
BASIC INTERVAL
TIMER/WATCHDOG
TIMER
8-BIT TIMER
COUNTER#0
8-BIT
TIMER
COUNTER#1
8-BIT
TIMER
COUNTER#2
CASCADED
16-BIT
TIMER
COUNTER
INTERRUPT
CONTROL
PROGRAMMABLE
THRESHOLD
PORT
INTBT RESET
INTT0 TOUT
INTT1
INTT2
PTO0/P30
PTO1/P31
PTO2/P32
INT0/P61
KRREN
KR4/P70 to
KR7/P73
AVREF/P60
PTH00/P62
PTH01/P63
ALU
PROGRAM COUNTER
PROGRAM MEMORY
(ROM)
4096
× 8 BITS
DECODE
AND
CONTROL
CY
SP (8)
SBS
BANK
GENERAL REG.
DATA MEMORY
(RAM)
128
× 4 BITS
EEPROM
16×8 BITS
PORT3 4
PORT6 4
PORT7 4
PORT8
BIT SEQ. BUFFER (16)
P30 to P33
P60 to P63
P70 to P73
P80
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
STAND BY
CONTROL
fX/2N
CL1 CL2 X1 X2
φ
CPU CLOCK
Apply to the
µPD754144
Apply to the
µPD754244
IC VDD VSS RESET
4
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µ PD754144, 754244
9
Data Sheet U10040EJ2V1DS
3. PIN FUNCTION
3.1 Port Pins
Pin Name Input/Output Alternate Function 8-bit After Reset
I/O Circuit
Function I/O TYPE Note 1
P30 Input/Output PTO0 – Input E-B
P31 PTO1
P32 PTO2
P33 –
P60 Input/Output AVREF –Input F -A
P61 INT0
P62 PTH00
P63 PTH01
P70 Input KR4 – Input B -A
P71 KR5
P72 KR6
P73 KR7
P80 Input/Output – – Input F -A
Notes 1. Circled characters indicate the Schmitt-trigger input.
2. Do not specify an on-chip pull-up resistor connection when using the programmable threshold port.
Programmable 4-bit input/output port
(PORT3).
This port can be specified input/output bit-
wise.
On-chip pull-up resistor connection can be
specified by software in 4-bit units.
Programmable 4-bit input/output port (PORT6).
This port can be specified input/output bit-
wise.
On-chip pull-up resistor can be specified by
software in 4-bit unitsNote2.
Noise eliminator can be selected with P61/INT0.
4-bit input port (PORT7).
On-chip pull-up resistor can be specified by
software bit-wise.
1-bit input/output port (PORT8).
On-chip pull-up resistor connection can be
specified by software.
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µ PD754144, 754244
10 Data Sheet U10040EJ2V1DS
3.2 Non-port Pins
Pin Name Input/Output Alternate Function After Reset
I/O Circuit
Function TYPENote
PTO0 Output P30 Timer counter output pins Input E-B
PTO1 P31
PTO2 P32
INT0 Input P61 Edge detection vectored Noise elimination Input F -A
interrupt input pin circuit can be
(detected edge can be selected.
selected) Asynchronous
Noise elimination circuit input
can be selected.
KR4 to KR7 Input P70 to P73 Falling edge detection testable input pins Input B -A
PTH00 Input P62 Threshold voltage-variable 2-bit analog input pins Input F -A
PTH01 P63
KRREN Input – Key return reset enable pin Input B
The reset signal is generated at the falling edge
of KRn while KRREN is high in STOP mode.
AVREF Input P60 Reference voltage input pin Input F -A
CL1 ––Incorporated in the µ PD754144 only ––
RC (for system clock oscillation) connection pin
CL2 – External clock cannot be input.
X1 Input – Incorporated in the
µ PD754244 only ––
Crystal/ceramic resonator (for system clock
oscillation) connection pin
X2 – When inputting the external clock, input the external
clock to pin X1 and input the inverted phase of the
external clock to pin X2.
RESET Input – System reset input pin (low-level active) – B -A
Pull-up resistor can be incorporated (mask option).
IC – – Internally Connected Connect directly to VDD.– –
VDD ––Positive supply pin – –
VSS ––Ground potential – –
Note Circled characters indicate the Schmitt-trigger input.
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µ PD754144, 754244
11
Data Sheet U10040EJ2V1DS
3.3 Pin Input/Output Circuits
The
µ PD754244 pin input/output circuits are shown schematically.
TYPE A
TYPE B
TYPE D
TYPE E-B
TYPE B-A TYPE F-A
V
DD
IN
P-ch
N-ch
data
output
disable
N-ch
P-ch
IN
OUT
V
DD
P-ch
output
disable
data
P.U.R.
enable
Type D
Type A
IN/OUT
V
DD
P.U.R. (Mask Option)
IN
V
DD
P.U.R.
P.U.R.
enable P-ch
IN/OUT
Type D
Type B
output
disable
data
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Schmitt-trigger input having hysteresis characteristic.
CMOS specification input buffer.
Push-pull output that can be placed in output
high-impedance (both P-ch, N-ch off).
P.U.R.
V
DD
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µ PD754144, 754244
12 Data Sheet U10040EJ2V1DS
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Recommended Connection of Unused Pins
Pin Recommended Connecting Method
P30/PTO0 Input state : Independently connect to VSS or VDD via a resistor.
P31/PTO1 Output state: Leave open.
P32/PTO2
P33
P60/AVREF
P61/INT0
P62/PTH00
P63/PTH01
P70/KR4 Connect to VDD.
P71/KR5
P72/KR6
P73/KR7
P80 Input state : Independently connect to VSS or VDD via a resistor.
Output state: Leave open.
KRREN When this pin is connected to VDD, internal reset signal is gener-
ated at the falling edge of the KRn pin in the STOP mode.
When this pin is connected to VSS, internal reset signal is not
generated even if the falling edge of KRn pin is detected in the
STOP mode.
IC Connect directly to VDD.
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µ PD754144, 754244
13
Data Sheet U10040EJ2V1DS
4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE
4.1 Difference between Mk I and Mk II Modes
The
µ PD754244 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by the bit 3 of the Stack Bank Select register (SBS).
•Mk I mode: Instructions are compatible with the 75X series. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
•Mk II mode: Incompatible with 75X series. Can be used in all the 75XL CPU’s including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I Mode Mk II Mode
Number of stack bytes 2 bytes 3 bytes
for subroutine instructions
BRA !addr1 instruction Not available Available
CALLA !addr1 instruction
CALL !addr instruction 3 machine cycles 4 machine cycles
CALLF !faddr instruction 2 machine cycles 3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.
Therefore, this mode is effective for enhancing software compatibility with products that
have a program area of more than 16 Kbytes.
With regard to the number of stack bytes during execution of subroutine call instructions,
the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II
mode is selected.
However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle
becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use
efficiency and processing performance than on software compatibility, the Mk I mode
should be used.
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µ PD754144, 754244
14 Data Sheet U10040EJ2V1DS
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using
the Mk II mode, it must be initialized to 0000B.
Figure 4-1. Stack Bank Select Register Format
Caution Because SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the
Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select
the Mk II mode.
Address
Stack area specification
Symbol
SBS
F84H SBS3 SBS2 SBS1 SBS0
32 10
Memory bank 0
Mk II mode
Mk I mode
Other than above setting prohibited
Mode switching specification
0 must be set in the bit 2 position
0
0
1
0
0
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µ PD754144, 754244
15
Data Sheet U10040EJ2V1DS
5. MEMORY CONFIGURATION
•Program memory (ROM) • • • 4096 x 8 bits
•Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a
RESET signal is generated are written. Reset and start are possible at an arbitrary address.
•Addresses 0002H to 000FH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored
interrupts are written. Interrupt service can be started at an arbitrary address.
•Addresses 0020H to 007FH
Table area referenced by the GETI instructionNote.
Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the program steps.
•Data memory
•Data area
Static RAM • • • 128 words x 4 bits (000H to 07FH)
EEPROM • • • 16 words x 8 bits (400H to 41FH)
•Peripheral hardware area • • • 128 words x 4 bits (F80H to FFFH)
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µ PD754144, 754244
16 Data Sheet U10040EJ2V1DS
Figure 5-1. Program Memory Map
Note Can be used in the MkII mode only.
Remark In addition to the above, a branch can be made to an address with the low-order 8-bits only of the
PC changed by means of a BR PCDE or BR PCXA instruction.
7654 0
MBE RBE Internal reset start address (high-order 4 bits)
Internal reset start address (low-order 8 bits)
MBE RBE INTBT start address (high-order 4 bits)
INTBT start address (low-order 8 bits)
MBE RBE INT0 start address (high-order 4 bits)
INT0 start address (low-order 8 bits)
MBE RBE INTT0 start address (high-order 4 bits)
INTT0 start address (low-order 8 bits)
MBE RBE INTT1/INTT2 start address (high-order 4 bits)
INTT1/INTT2 start address (low-order 8 bits)
MBE RBE
0
0
0
0
0
0
0
0
0
0
0
0 INTEE start address (high-order 4 bits)
INTEE start address (low-order 8 bits)
GET instruction reference table
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
0020H
007FH
0080H
07FFH
0800H
0FFFH
CALLF !faddr instruction
entry address
Branch address of
BR !addr
BRCB !caddr
BR BCDE
BR BCXA
BRA !addr
Note
CALL !addr
CALLA !addr
Note
instructions
GETI Branch/call
Addresses
BR $addr instruction
relative branch address
(–15 to –1, +2 to +16)
Address
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µ PD754144, 754244
17
Data Sheet U10040EJ2V1DS
Figure 5-2. Data Memory Map
000H
01FH
020H
07FH
080H
0FFH
400H
41FH
420H
4FFH
F80H
FFFH
128 × 4
Not incorporated
16 × 8
Not incorporated
128 × 4
(96 × 4)
(32 × 4)
0
4
15
General-purpose
register area
Stack area
Data area
static RAM (128 × 4)
Data area
EEPROM (16 × 8)
Peripheral hardware area
Data memory Memory bank
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µ PD754144, 754244
18 Data Sheet U10040EJ2V1DS
6. EEPROM
The µ PD754244 incorporates 16 words ×8 bit EEPROM (Electrically Erasable PROM) as well as static RAM
(128 words ×4 bit) as a data memory.
The EEPROM incorporated into the
µ PD754244 has the following features.
(1) Written data is retained if power is turned off.
(2) 8-bit data manipulation (auto-erase/auto-write) is available by memory manipulation instruction as well as
for static RAM. However available instructions are restricted.
(3) It can reduce loads of software because the auto-erase and/or auto-write operation is performed by
hardware.
(4) Write operation control using the interrupt request
The interrupt request is generated under following conditions.
•Terminates write operation
•Write status flag
It is possible to check whether enables or disables write operation by bit manipulation instructions.
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µ PD754144, 754244
19
Data Sheet U10040EJ2V1DS
7. PERIPHERAL HARDWARE FUNCTIONS
7.1 Digital Input/Output Ports
The following two types of I/O ports are provided.
•CMOS input (Port 7) : 4
•CMOS I/O (Ports 3, 6, 8) : 9
Total : 13
Table 7-1. Types and Features of Digital Ports
Port Name Function Operation and Features Remarks
PORT3 4-bit I/O Can be set to input or output mode bit-wise. Also used as PTO0 to PTO2 pins.
PORT6 Also used as AVREF, INT0, PTH00,
and PTH01 pins.
PORT7 4-bit input 4-bit input only port Also used as KR4 to KR7 pins.
On-chip pull-up resistor connection can be specified
by mask option bit-wise.
PORT8 1-bit I/O Can be set to input or output mode bit wise. _
7.2 Clock Generator
The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown
in Figures 7-1 and 7-2.
The operation of the clock generator is set with the processor clock control register (PCC).
The instruction execution time can be changed.
•
µ PD754144
•4, 8, 16, 64 µs (when the system clock fCC operates at 1.0 MHz)
•
µ PD754244
•0.95, 1.91, 3.81, 15.3 µs (when the system clock fXoperates at 4.19 MHz)
•0.67, 1.33, 2.67, 10.7 µs (when the system clock fXoperates at 6.0 MHz)
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µ PD754144, 754244
20 Data Sheet U10040EJ2V1DS
Figure 7-1. µ PD754144 (RC Oscillation) Clock Generator Block Diagram
Note Instruction execution
Remarks 1. fcc: System clock frequency
2. Φ= CPU clock
3. PCC: Processor Clock Control Register
4. One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
CL1
CL2
System
clock
oscillator
Oscillation stops
1/1~1/4096
1/2 1/4 1/16
f
cc
Divider
1/4 Φ
HALT F/F
S
RQ
S
R
Q
STOP F/F
PCC0
PCC1
PCC2
PCC3
PCC2,
PCC3
clear
HALT
Note
STOP
Note
Wait release signal from BT
Reset signal
Standby release signal from
interrupt control circuit
PCC
4
· Basic interval timer (BT)
· Timer counter
· INT0 noise eliminator
· CPU
· INT0 noise
eliminator
Divider
Selector
Internal bus
*