Texas Instruments TIDA-00204 User manual

1
JAJU324B–March 2015–Revised July 2017
TIDU832 翻訳版 —最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC 規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
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参参考考資資料料
TI Designs: TIDA-00204
EMI/EMC 規規格格準準拠拠、、産産業業用用温温度度範範囲囲ののデデュュアアルルポポーートト・・ギギガガビビッッ
トト・・イイーーササネネッットトののリリフファァレレンンスス・・デデザザイインン
概概要要
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を提供しています。開発期間の短縮に役立ちます。
リリソソーースス
TIDA-00204 デザイン・フォルダ
DP83867IR プロダクト・フォルダ
LM46002 プロダクト・フォルダ
AM3359 プロダクト・フォルダ
TPS65910A3 プロダクト・フォルダ
TPS51200 プロダクト・フォルダ
LMZ10501 プロダクト・フォルダ
TPS720 プロダクト・フォルダ
TPS737 プロダクト・フォルダ
TPD4E05U06 プロダクト・フォルダ
TPS717 プロダクト・フォルダ
TPD4S012 プロダクト・フォルダ
CDCE913 プロダクト・フォルダ
E2Eエキスパートに質問
WEBENCH®設計支援ツール
特特長長
• EMIおよびEMC規格に準拠した設計で、2つの
DP83867IRギガビット・イーサネットPHYおよび
AM3359 Sitara™プロセッサを使用して広い入力電圧
範囲(17～60V)に対応し、過酷な工業用環境で動作可
能
• CISPR 11/EN55011 Class Aの放射要件を4.3dB
超上回る
• IEC61800-3 EMCの耐性要件を上回る
– ±6kV ESD CD (IEC 61000-4-2)
– ±4kV EFT (IEC 61000-4-4)
– ±2kV サージ(IEC 61000-4-5)
• Sitara AM3359ファームウェアにUDPおよびTCP/IP
スタックと、HTTP Webサーバのサンプルが含まれてお
り、オンボードのSDカードからブートするため、スタンド
アロンで簡単に動作
• USB仮想COMポート経由でDP83867IRレジスタへアク
セスできるため、RGMII遅延モードなど、特定のカスタ
ムPHY構成が可能
•クロック・シンセサイザを使用してシステム・クロックを生
成し、ジッタと、クロックからの位相シフトを低減
アアププリリケケーーシショョンン
•産業用ドライブ
•ファクトリ・オートメーション/制御
•産業用ネットワーク
•試験および測定機器

JTAG/
UART
Micro
SD
24-V to 5-V
DC-DC
Reset
button
Magnetics
Input: 24 V
(17 V to 60 V)
Micro
USB
DDR3
Status LEDs
10/100/1000
Mb/s
Ethernet
PHY1
DP83867IR RJ45
10/100/1000
Mb/s
Ethernet
PHY2
DP83867IR
6LWDUDŒ30,&
DDR3 P/S Gigabit PHY P/S
Port 1
25-MHz clock
24-MHz
clock Host processor
SitaraŒAM3359
Magnetics
Status LEDs
RJ45 Port 2
25-MHz clock
Application firmware
- IPv4 TCP/IP
- UDP
- IP address:
192.168.1.10
- HTTP webserver
example
Clocking
Distribution
Network
CDCE913
25-MHz
clocks
24-MHz
clock
Copyright © 2017, Texas Instruments Incorporated
System Description www.tij.co.jp
2JAJU324B–March 2015–Revised July 2017
TIDU832 翻訳版 —最新の英語版資料 http://www-s.ti.com/sc/techlit/TIDU832
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EMI/EMC 規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
リファレンス・デザイン
使用許可、知的財産、その他免責事項は、最終ページにあるIMPORTANT NOTICE(重要な注意事項）をご参照くださいますようお願いい
たします。 英語版のTI製品についての情報を翻訳したこの資料は、製品の概要を確認する目的で便宜的に提供しているものです。該当す
る正式な英語版の最新情報は、www.ti.comで閲覧でき、その内 容が常に優先されます。TIでは翻訳の正確性および妥当性につきましては
一切保証いたしません。実際の設計などの前には、必ず最新版の英語版をご参照くださいますようお願いいたします。
1 System Description
This TI design supports dual-port Gigabit Ethernet communication through twisted pair copper cable as
defined in IEEE 802.3ab. It is designed to be evaluated for harsh industrial environment with regards to
standard compliance to CISPR 11 / EN55011 Class A radiated immunity requirements and EMC immunity
requirements for ESD according to 61000-4-2, fast transient burst (EFT) according to IEC61000-4-4, and
surge according to IEC61000-4-5.
The design implements dual-port Gigabit Ethernet using two DP83867IR Gigabit Ethernet PHYs, which
are connected through the Reduced Gigabit Media Independent Interface (RGMII) to AM3359 Sitara
processor with integrated Ethernet MAC and Switch. It offers a wide input voltage range from 17 to 60 V
with nominal 24-V input voltage and meets industrial requirements for EMI and EMC.
For easy standalone operation, the host processor is configured to boot the pre-installed application
firmware from an onboard SD-Card. The application firmware implements a driver for the DP83867IR,
UDP and TCP/IP stack, and HTTP web server examples, based on TI’s SYS/BIOS Industrial SDK and TI’s
Networking Development Kit NDK. A USB virtual COM port offers optional user access to read or write to
DP83867IR registers for custom configurations like RGMII Delay Mode, if required. A JTAG interface on
the AM3359 provides the option for custom software development, test, and debug.
Therefore, this design allows for performance evaluation of two DP83867IR Gigabit Ethernet PHYs and
AM3359 Sitara processor with integrated Ethernet MAC and Switch.
1.1 Key System Specifications
This design allows for performance evaluation of two DP83867IR Gigabit Ethernet PHYs and AM3359
Sitara™ processors with an integrated Ethernet MAC and Switch. It meets industrial requirements for EMI
and EMC, supports industrial temperature grade, and offers a wide input voltage range with a default of
24 V.

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EMI/EMC 規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットのリ
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To allow for easy standalone operation, the AM3359 Sitara boots the application firmware from SD-Card.
The application firmware implements the driver for the DP83867IR, UDP and TCP/IP stack, and HTTP
web server examples and is based on TI’s SYS/BIOS Industrial SDK. An additional option is provided to
access the DP83867IR Gigabit Ethernet PHY registers through USB virtual COM port. A JTAG interface
option is also provided to allow for custom software development with that board.
表表 1. TIDA-00204 Hardware Specification
FUNCTION INFO SPECIFICATION COMMENT
Gigabit Ethernet IEEE 802.3ab
Number of ports 2 —
MDI 1000BASE-T (copper) —
MAC interface RGMII —
EMAC and switch Y Integrated with Sitara AM3359
Status LED Y —
IEEE 1588v2 Y Hardware enabled but not
tested
Separate transformer and
RJ45 jack YOption to place protection
diodes on either side of the
magnetics, used for test
purpose
SMI Y (2.5 MHz) —
Configurable PHY address
(SMI) Y Through strap resistors
DP83867IR
Low power 565 mW —
Integrated termination resistors Y —
RGMII Delay Mode on RX/TX Programmable —
Clock 25 MHz (< 50 ppm) —
Power
Input voltage 24 V (17 to 60 V) —
Output voltage 5 V Intermediate voltage
Output current 850 mA (nominal), 1.2 A
(maximum) —
Indicator LED Y For 5 V, 3.3 V and 2.5 V
Point of load for all ICs Y PMIC for AM3359, 3.3 V (I/O),
2.5 V and 1.1 V for PHYs
Standalone operation Boot from SD-Card interface Y —
USB virtual COM port Access to PHY registers Y Read and write operation to both registers of PHY
supported
JTAG JTAG header Y —
Temperature range Industrial –40°C to 85°C Selected devices support
industrial temperature range
EMI CISPR 11 / EN55011 Class A radiated emissions —
EMC IEC61800-3
IEC61000-4-2 ±4-kV ESD CD,
Criterion B Shielded Ethernet cable
IEC61000-4-4 ±2-kV EFT,
Criterion B Shielded Ethernet cable
IEC61000-4-5 ±1-kV Surge,
Criterion B Shielded Ethernet cable, min 20 m
表表 2. TIDA-00204 Firmware Specification (AM3359)
FUNCTION INFO SPECIFICATION COMMENT
Boot loader Boot application firmware from SD-Card Y —
DDR3 memory Driver for DDR3 Y —
USB virtual COM port Driver for UART Y —

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EMI/EMC 規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
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表表 2. TIDA-00204 Firmware Specification (AM3359) (continued)
FUNCTION INFO SPECIFICATION COMMENT
PHY Driver for DP83867IR Y —
RTOS TI SYS/BIOS Y —
UDP and TCP/IP IPv4 protocol support Y Based on TI’s AM335x
industrial SDK and NDK
Fixed IP 192.168.1.10 —
HTTP Web server example Y Based on TI’s AM335x
industrial SDK and NDK

JTAG/
UART
Micro
SD
24-V to 5-V
DC-DC
Reset
button
Magnetics
Input: 24 V
(17 V to 60 V)
Micro
USB
DDR3
Status LEDs
10/100/1000
Mb/s
Ethernet
PHY1
DP83867IR RJ45
10/100/1000
Mb/s
Ethernet
PHY2
DP83867IR
6LWDUDŒ30,&
DDR3 P/S Gigabit PHY P/S
Port 1
25-MHz clock
24-MHz
clock Host processor
SitaraŒAM3359
Magnetics
Status LEDs
RJ45 Port 2
25-MHz clock
Application firmware
- IPv4 TCP/IP
- UDP
- IP address:
192.168.1.10
- HTTP webserver
example
Clocking
Distribution
Network
CDCE913
25-MHz
clocks
24-MHz
clock
Copyright © 2017, Texas Instruments Incorporated
Optional access
DP83867IR through
virtual COM port
Boot application
firmware from SD card
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Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC 規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
リファレンス・デザイン
2 System Overview
2.1 Block Diagram
図1shows the system block diagram. The major building blocks are the DP83867IR Gigabit Ethernet
PHY, the AM3359 Sitara Host Processor, and the power supplies.
図図 1. System Block Diagram of TIDA-00204
2.2 Design Considerations
2.2.1 Gigabit Ethernet Overview
Ethernet has heavily expanded usage over the years. Ethernet became an attractive option for industrial
networking applications. The opportunity to use open protocols (such as TCP/IP over Ethernet networks)
help replace proprietary communications in industrial control and factory automation applications. When
using Ethernet, there are several speeds available today: 10 Mb/s, 100 Mb/s (Fast Ethernet), 1000 Mb/s
(Gigabit Ethernet), and 10 Gb/s (10-Gigabit Ethernet).
Gigabit Ethernet uses the extended Ethernet MAC layer interface, connected through a Gigabit Media
Independent Interface (GMII) layer to physical layer entities (PHY sublayers) such as 1000BASE-LX,
1000BASE-SX, 1000BASE-CX, and 1000BASE-T. The topology for a 1000-Mb/s full-duplex operation is
comparable to the 100BASE-T full-duplex mode, and the minimum packet transmission time has been
reduced by a factor of ten. The resulting achievable topologies for the half-duplex 1000-Mb/s CSMA/CD
MAC are similar to those found in half duplex 100BASE-T.

MDI_1+
MDI_1-
to RJ45
to PHY 1:1
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EMI/EMC 規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
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表表 3. Gigabit Ethernet Standards
IEEE STANDARD NAME MEDIUM
IEEE 802.3ab 1000BASE-T Twisted-pair copper cable
IEEE 802.3z 1000BASE-SX Fiber optic cable 1000BASE-LX Fiber optic cable
1000BASE-CX Twinax
As previously mentioned, this TI Design uses twisted-pair copper cables as defined IEEE 802.3ab.
2.2.2 Gigabit Ethernet PHY Interfaces
2.2.2.1 Medium Dependent Interface: PHY Layer 1000BASE-T
The 1000BASE-T Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and baseband
medium specifications are intended for users who want a 1000-Mb/s performance over balanced twisted-
pair cabling systems.
The 1000BASE-T PHY supports full-duplex baseband transmission through four pairs of minimum CAT5
balanced cables. The 1000 Mb/s is achieved by transmitting through four wires pairs, each at 250 Mb/s.
Using hybrids and cancellers enable full duplex transmission by allowing symbols to be transmitted and
received on the same wire pairs at the same time. Baseband signaling with a modulation rate of 125 MBd
is used on each of the wire pairs. The transmitted symbols are selected from a four-dimensional five-level
symbol constellation (4D-PAM5). In the absence of data, idle symbols are transmitted.
The IEEE 802.3 specifies specify that a PHY with a MDI that is not a power interface (PI) should provide
electrical isolation between the port device circuits, including frame ground (if any) and all MDI leads. This
electrical isolation shall withstand at least one of the following electrical strength tests:
• 1500 VRMS at 50 to 60 Hz for 60 s
• 2250-V DC for 60 s
• A sequence of ten 2400-V impulses of alternating polarity, applied at intervals of not less than 1 s
To meet this requirement transformers are typically used for isolation. The typical transformer
configuration for 1000BASE-T can be seen in 図2for a one differential pair.
図図 2. Gigabit Ethernet Transformer (One out of Four Pairs)
Depending on the PHY device, parallel termination might be needed for each of the MDI differential signal
pair. The termination impedance is typically 100 Ωdifferentially. Newer devices like the DP83867IR
include integrated termination so no external termination resistors are required.

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2.2.2.2 Medium Independent Interface: MAC Layer Interface
For the MAC layer interface to the Gigabit PHY, there are three different options defined in the IEEE
802.3ab standard: The standard Media Independent Interface (MII), the GMII, SGMII, or the RGMII.
2.2.2.2.1 GMII
The purpose of GMII is to make various physical media transparent to the MAC layer. The GMII accepts
either GMII or MII data, control, and status signals and routes them either to the 1000BASE-T, 100BASE-
TX, or 10BASE-T modules, respectively.
The GMII provides full-duplex operation and is an 8-bit wide transmit and receive data path interface
clocked at 125 MHz defining speeds up to 1000 Mb/s. GMII is backwards compatible with the MII
specification, thereby supporting 10 (2.5 MHz) and 100 (25 MHz) Mb/s speeds. Data and delimiters are
synchronous to clock references. It also provides a simple management interface.
The transmit signals are GTX_CLK, TX_CLK, TX_D[7:0], TX_EN, and TX_ER. The GTX_CLK signal is
supplied to the PHY when it is operating in Gigabit mode. When this is done, the TX_D, TX_EN, and
TX_ER are synchronized to the GTX_CLK signal. For a 10/100-Mb operation, the TX_CLK is supplied to
the MAC, and the TX_CLK signal is used to synchronize the signals (TX_D, TX_EN, and TX_ER). The
receiver signals are RX_CLK, RX_D[7:0], RX_DV, RX_ER, COL, and CS. The GMII uses in total a
maximum of 25 pins.
2.2.2.2.2 RGMII
The RGMII is designed to reduce the number of pins required to interconnect the MAC and PHY (12 pins
for RGMII relative to 24 pins for GMII). With this optimization, the RGMII consists of 12 signals: 6 signals
for receive, which are RX_CTL, RX_CLK, RX_D[3:0], and 6 for transmit, which are TX_CTL,
TX_CLK,TX_D[3:0]. To accomplish this, the data paths and all associated control signals are reduced and
are multiplexed. Both rising and trailing edges of the clock are used. The TX_CTL and RX_CTL signal
carries data valid (DV) on the rising edge and DV XOR ERROR on the falling edge, for CTL signals there
is no change between 10/100Mb/s or 1000Mb/s operation.
For a Gigabit operation, the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-Mb/s
operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.
2.2.2.2.3 SGMII
The SGMII differs from the GMII and RGMII by having a higher clock frequency and the 8b/10b (SerDes)
coded interface. It uses differential pairs at a 625-MHz clock frequency double data rate (DDR) for TX and
RX data and for TX and RX clock. The transmit and receive path uses one differential pair for data and in
some cases one for clock. TX and RX clocks must be generated on device output but are optional on
device input. With revision 1.8 of the SGMII standard, clock recovery can be used, removing the need for
the clock signal. This means that the SGMII can be a 4- to 8-pin solution.

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EMI/EMC 規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
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2.2.2.3 Serial Management Interface
The serial management interface (SMI) consists of a Management Data Clock (MDC) and a Management
Data Input/Output (MDIO) signal. It provides access to the PHY’s internal register space for status
information and configuration. The MDC and MDIO signals can be shared amongst several PHYs due to
the serial communication protocol, where an address is used to identify the corresponding PHY slave. The
MDIO has a standard set of registers from 0 to 31 each containing 16 bits. In IEEE 802ah clause 45, an
extended register set was defined for extra functionality of the PHYs. The SMI is initially specified at a
2.5-MHz clock.

Processor
MAC
Ethernet PHY
OS
IEEE1588 code
(Application layer) 4
3
2
1
Hardware assist
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2.2.3 IEEE 1588v2
Precise time information is important, especially for distributed systems like in factory automation. The
IEEE 1588v2 is an IEEE standard for precision clock synchronization protocol for networked measurement
and control systems. The protocol is used to synchronize the time and clock frequency. It defines a way to
provide sub-microsecond precision synchronization.
To define this synchronization, the start of package detection is needed. Depending on which application
layer this detection happens, the timing error varies. The lower the layer, the smaller the error.
図図 3. Options 1 to 4 for Time Stamp versus Layer
The closer to the PHY the time stamp is set the better the time reference. The time stamp consists of two
signals the Ingress (RX) and Egress (TX) time stamp. Depending on when the time stamp is done, the
delay can vary from nanoseconds to microseconds.
2.3 System Design Theory
2.3.1 Circuit Design and Component Selection
2.3.1.1 DP83867IR 10/100/1000-Mb/s Gigabit Ethernet PHY
The DP83867IR was selected due to following features:
• IEEE 802.3ab 1000BASE-T compliant
• Operating temperature range –40°C to 85°C
• 8-kV IEC 61000-4-2 ESD protection (direct contact)
• RGMII with software (register) programmable and hardware configurable (strap resistors) clock skew
• Integrated termination resistors
• Low power: 565 mW
• SOF detect for IEEE 1588 time stamp
In addition to the above features, the DP83867IR also offers the following features:
• Low deterministic TX and RX latency
• Wake on LAN (WoL)

Strap (GPIO)
VDDIO
RHI
RLO
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• Synchronized clock output to synchronize multiple PHYs using one crystal (or clock)
2.3.1.1.1 DP83867IR Gigabit Ethernet PHY Configuration
When configuring the DP83867IR, this can be done using either a SMI or a strap configuration through the
four-level strap pins. A pull-up resistor and a pull-down resistor of suggested values may be used to set
the voltage ratio of the four-level strap pin input and the supply to select one of the possible selected
modes. The device should feature four-level strap pins, each supporting at least four selectable options,
as shown in 図4and 表4. Strap resistors with 1% tolerance are recommended.
図図 4. Strap Circuit
表表 4. Four-Level Strap Resistor Ratios
MODE RESISTOR RHI (kΩ) RESISTOR RLO (kΩ)
1 OPEN OPEN
2 11 2.49
3 6.04 2.49
4 2.49 OPEN
Because this design employs two DP83867IR, the SMI will have two DP83867IR slaves addresses. This
means that the SMI address of the two DP83867IR have to differ to ensure a valid communication. To set
the DP83867IR SMI address a strap configuration option can be used on one DP83867IR to change the
default address from 0x00. In this design, it was chosen to use the pin RX_D4 to set the SMI address, as
this pin is not used for the RGMII.
A strap configuration option was chosen so the RGMII is always enabled to ensure the RGMII is enabled
when as the RX_D6 pin is used as input pin on the AM3359 Sitara processor.
As the clock out option of the device is not used by default, RX_D7 strap configuration option was done to
disable the clock out of the device. This feature is default on if this strap on is not done and if it needs to
be disabled without strap configuration. It would have to be done using the SMI.