Texas Instruments CC3235 SimpleLink Series Product manual

CC3235x SimpleLink™Wi-Fi®and
Internet of Things
Technical Reference Manual
Literature Number: SWRU543
January 2019

2SWRU543–January 2019
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Contents
Contents
Preface....................................................................................................................................... 36
1 Architecture Overview......................................................................................................... 39
1.1 Introduction.................................................................................................................. 40
1.2 Architecture Overview ..................................................................................................... 41
1.3 Functional Overview ....................................................................................................... 42
1.3.1 Processor Core.................................................................................................... 42
1.3.2 Memory............................................................................................................. 43
1.3.3 Micro-Direct Memory Access Controller (µDMA).............................................................. 44
1.3.4 General-Purpose Timer (GPT) .................................................................................. 45
1.3.5 Watchdog Timer (WDT) .......................................................................................... 45
1.3.6 Multichannel Audio Serial Port (McASP)....................................................................... 45
1.3.7 Serial Peripheral Interface (SPI)................................................................................. 46
1.3.8 Inter-Integrated Circuit (I2C) Interface ......................................................................... 46
1.3.9 Universal Asynchronous Receiver/Transmitter (UART)...................................................... 46
1.3.10 General-Purpose Input/Output (GPIO) ........................................................................ 47
1.3.11 Analog-to-Digital Converter (ADC)............................................................................. 47
1.3.12 SD Card Host .................................................................................................... 47
1.3.13 Parallel Camera Interface ...................................................................................... 48
1.3.14 Debug Interface .................................................................................................. 48
1.3.15 Hardware Cryptography Accelerator........................................................................... 48
1.3.16 Clock, Reset, and Power Management ....................................................................... 48
1.3.17 SimpleLink™ Subsystem........................................................................................ 49
1.3.18 I/O Pads and Pin Multiplexing.................................................................................. 49
2 Cortex®-M4 Processor......................................................................................................... 50
2.1 Overview..................................................................................................................... 51
2.1.1 Block Diagram ..................................................................................................... 52
2.1.2 System-Level Interface ........................................................................................... 52
2.1.3 Integrated Configurable Debug.................................................................................. 52
2.1.4 Trace Port Interface Unit (TPIU) ................................................................................ 53
2.1.5 Cortex®-M4 System Component Details ....................................................................... 53
2.2 Functional Description..................................................................................................... 54
2.2.1 Programming Model .............................................................................................. 54
2.2.2 Register Description .............................................................................................. 55
2.2.3 Memory Model..................................................................................................... 58
2.2.4 Exception Model................................................................................................... 62
2.2.5 Fault Handling ..................................................................................................... 68
2.2.6 Power Management............................................................................................... 71
2.2.7 Instruction Set Summary ......................................................................................... 73
3 Cortex®-M4 Peripherals ....................................................................................................... 77
3.1 Overview..................................................................................................................... 78
3.2 Functional Description..................................................................................................... 78
3.2.1 System Timer (SysTick).......................................................................................... 78
3.2.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 79
3.2.3 System Control Block (SCB)..................................................................................... 80
3.3 Register Map................................................................................................................ 80

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3.3.1 Cortex Registers................................................................................................... 83
4 Direct Memory Access (DMA)............................................................................................. 117
4.1 Overview................................................................................................................... 118
4.2 Functional Description.................................................................................................... 118
4.2.1 Channel Assignment ............................................................................................ 119
4.2.2 Priority............................................................................................................. 120
4.2.3 Arbitration Size................................................................................................... 120
4.2.4 Channel Configuration .......................................................................................... 120
4.2.5 Transfer Mode.................................................................................................... 122
4.2.6 Transfer Size and Increment................................................................................... 125
4.2.7 Peripheral Interface.............................................................................................. 126
4.2.8 Interrupts and Errors ............................................................................................ 127
4.3 Register Description...................................................................................................... 127
4.3.1 DMA Register Map .............................................................................................. 127
4.3.2 µDMA Channel Control Structure.............................................................................. 128
4.3.3 DMA Registers................................................................................................... 128
4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers............................................. 132
5 General-Purpose Input/Outputs (GPIOs).............................................................................. 156
5.1 Overview................................................................................................................... 157
5.2 Functional Description.................................................................................................... 157
5.2.1 Data Control...................................................................................................... 158
5.3 Interrupt Control........................................................................................................... 159
5.3.1 µDMA Trigger Source........................................................................................... 159
5.4 Initialization and Configuration.......................................................................................... 159
5.5 GPIO Registers ........................................................................................................... 161
5.5.1 GPIODATA Register (offset = 0h) [reset = 0h]............................................................... 162
5.5.2 GPIODIR Register (offset = 400h) [reset = 0h] .............................................................. 163
5.5.3 GPIOIS Register (offset = 404h) [reset = 0h] ................................................................ 164
5.5.4 GPIOIBE Register (offset = 408h) [reset = 0h] .............................................................. 165
5.5.5 GPIOIEV Register (offset = 40Ch) [reset = 0h].............................................................. 166
5.5.6 GPIOIM Register (offset = 410h) [reset = 0h]................................................................ 167
5.5.7 GPIORIS Register (offset = 414h) [reset = 0h] .............................................................. 168
5.5.8 GPIOMIS Register (offset = 418h) [reset = 0h].............................................................. 169
5.5.9 GPIOICR Register (offset = 41Ch) [reset = 0h].............................................................. 170
5.5.10 GPIO_TRIG_EN Register ..................................................................................... 171
6 Universal Asynchronous Receivers/Transmitters (UARTs) .................................................... 173
6.1 Overview................................................................................................................... 174
6.1.1 Block Diagram.................................................................................................... 174
6.2 Functional Description.................................................................................................... 175
6.2.1 Transmit and Receive Logic.................................................................................... 175
6.2.2 Baud-Rate Generation .......................................................................................... 176
6.2.3 Data Transmission............................................................................................... 176
6.2.4 Initialization and Configuration................................................................................. 179
6.3 UART Registers........................................................................................................... 181
6.3.1 UARTDR Register (Offset = 0h) [reset = 0h]................................................................. 182
6.3.2 UARTRSR_UARTECR Register (Offset = 4h) [reset = 0h] ................................................ 183
6.3.3 UARTFR Register (Offset = 18h) [reset = 90h].............................................................. 185
6.3.4 UARTIBRD Register (Offset = 24h) [reset = 0h]............................................................. 187
6.3.5 UARTFBRD Register (Offset = 28h) [reset = 0h]............................................................ 188
6.3.6 UARTLCRH Register (Offset = 2Ch) [reset = 0h] ........................................................... 189
6.3.7 UARTCTL Register (Offset = 30h) [reset = 300h]........................................................... 191
6.3.8 UARTIFLS Register (Offset = 34h) [reset = 12h]............................................................ 193

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6.3.9 UARTIM Register (Offset = 38h) [reset = 0h]................................................................ 194
6.3.10 UARTRIS Register (Offset = 3Ch) [reset = 0h]............................................................. 196
6.3.11 UARTMIS Register (Offset = 40h) [reset = 0h] ............................................................. 198
6.3.12 UARTICR Register (Offset = 44h) [reset = 0h] ............................................................. 200
6.3.13 UARTDMACTL Register (Offset = 48h) [reset = 0h]....................................................... 202
7 Inter-Integrated Circuit (I2C) Interface.................................................................................. 203
7.1 Overview................................................................................................................... 204
7.1.1 Block Diagram.................................................................................................... 204
7.1.2 Signal Description ............................................................................................... 205
7.2 Functional Description.................................................................................................... 206
7.2.1 I2C Bus Functional Overview .................................................................................. 206
7.2.2 Supported Speed Modes ....................................................................................... 210
7.2.3 Interrupts.......................................................................................................... 211
7.2.4 Loopback Operation............................................................................................. 211
7.2.5 FIFO and µDMA Operation..................................................................................... 211
7.2.6 Command Sequence Flow Charts............................................................................. 213
7.2.7 Initialization and Configuration................................................................................. 221
7.3 I2C Registers.............................................................................................................. 222
7.3.1 I2CMSA Register (Offset = 0h) [reset = 0h].................................................................. 223
7.3.2 I2CMCS Register (Offset = 4h) [reset = 20h] ................................................................ 224
7.3.3 I2CMDR Register (Offset = 8h) [reset = 0h].................................................................. 229
7.3.4 I2CMTPR Register (Offset = Ch) [reset = 1h]................................................................ 230
7.3.5 I2CMIMR Register (Offset = 10h) [reset = 0h]............................................................... 231
7.3.6 I2CMRIS Register (Offset = 14h) [reset = 0h] ............................................................... 233
7.3.7 I2CMMIS Register (Offset = 18h) [reset = 0h] ............................................................... 235
7.3.8 I2CMICR Register (Offset = 1Ch) [reset = 0h]............................................................... 237
7.3.9 I2CMCR Register (Offset = 20h) [reset = 0h]................................................................ 239
7.3.10 I2CMCLKOCNT Register (Offset = 24h) [reset = 0h]...................................................... 240
7.3.11 I2CMBMON Register (Offset = 2Ch) [reset = 3h] .......................................................... 241
7.3.12 I2CMBLEN Register (Offset = 30h) [reset = 0h]............................................................ 242
7.3.13 I2CMBCNT Register (Offset = 34h) [reset = 0h]............................................................ 243
7.3.14 I2CSOAR Register (Offset = 800h) [reset = 0h]............................................................ 244
7.3.15 I2CSCSR Register (Offset = 804h) [reset = 0h] ............................................................ 245
7.3.16 I2CSDR Register (Offset = 808h) [reset = 0h].............................................................. 247
7.3.17 I2CSIMR Register (Offset = 80Ch) [reset = 0h] ............................................................ 248
7.3.18 I2CSRIS Register (Offset = 810h) [reset = 0h] ............................................................. 250
7.3.19 I2CSMIS Register (Offset = 814h) [reset = 0h]............................................................. 252
7.3.20 I2CSICR Register (Offset = 818h) [reset = 0h] ............................................................. 254
7.3.21 I2CSOAR2 Register (Offset = 81Ch) [reset = 0h].......................................................... 256
7.3.22 I2CSACKCTL Register (Offset = 820h) [reset = 0h] ....................................................... 257
7.3.23 I2CFIFODATA Register (Offset = F00h) [reset = 0h] ...................................................... 258
7.3.24 I2CFIFOCTL Register (Offset = F04h) [reset = 00040004h].............................................. 259
7.3.25 I2CFIFOSTATUS Register (Offset = F08h) [reset = 00010005h] ........................................ 261
7.3.26 I2CPP Register (Offset = FC0h) [reset = 1h] ............................................................... 262
7.3.27 I2CPC Register (Offset = FC4h) [reset = 1h] ............................................................... 263
8 SPI (Serial Peripheral Interface).......................................................................................... 264
8.1 Overview................................................................................................................... 265
8.1.1 Features........................................................................................................... 265
8.2 Functional Description.................................................................................................... 266
8.2.1 SPI ................................................................................................................ 266
8.2.2 SPI Transmission................................................................................................ 266
8.2.3 Master Mode ..................................................................................................... 270
8.2.4 Slave Mode....................................................................................................... 277

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8.2.5 Interrupts.......................................................................................................... 280
8.2.6 DMA Requests................................................................................................... 280
8.2.7 Reset .............................................................................................................. 281
8.3 Initialization and Configuration.......................................................................................... 281
8.3.1 Basic Initialization................................................................................................ 281
8.3.2 Master Mode Operation Without Interrupt (Polling) ......................................................... 281
8.3.3 Slave Mode Operation With Interrupt ......................................................................... 282
8.3.4 Generic Interrupt Handler Implementation ................................................................... 282
8.4 Access to Data Registers................................................................................................ 282
8.5 Module Initialization....................................................................................................... 283
8.5.1 Common Transfer Sequence................................................................................... 283
8.5.2 End-of-Transfer Sequences.................................................................................... 284
8.5.3 FIFO Mode........................................................................................................ 285
8.6 SPI Registers.............................................................................................................. 290
8.6.1 SPI_SYSCONFIG Register (offset = 10h) [reset = 0h] ..................................................... 291
8.6.2 SPI_SYSSTATUS Register (offset = 114h) [reset = 0h].................................................... 292
8.6.3 SPI_IRQSTATUS Register (offset = 118h) [reset = 0h] .................................................... 293
8.6.4 SPI_IRQENABLE Register (offset = 11Ch) [reset = 0h].................................................... 295
8.6.5 SPI_MODULCTRL Register (offset = 128h) [reset = 4h]................................................... 296
8.6.6 SPI_CHCONF Register (offset = 12Ch) [reset = 60000h].................................................. 297
8.6.7 SPI_CHSTAT Register (offset = 130h) [reset = 0h]......................................................... 300
8.6.8 SPI_CHCTRL Register (offset = 134h) [reset = 0h]......................................................... 301
8.6.9 SPI_TX Register (offset = 138h) [reset = 0h] ................................................................ 302
8.6.10 SPI_RX Register (offset = 13Ch) [reset = 0h] .............................................................. 303
8.6.11 SPI_XFERLEVEL Register (offset = 17Ch) [reset = 0h]................................................... 304
9 General-Purpose Timers.................................................................................................... 305
9.1 Overview................................................................................................................... 306
9.2 Block Diagram............................................................................................................. 306
9.3 Functional Description.................................................................................................... 307
9.3.1 GPTM Reset Conditions........................................................................................ 308
9.3.2 Timer Modes ..................................................................................................... 309
9.3.3 DMA Operation................................................................................................... 314
9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................... 314
9.4 Initialization and Configuration.......................................................................................... 315
9.4.1 One-Shot and Periodic Timer Mode........................................................................... 315
9.4.2 Input Edge-Count Mode......................................................................................... 315
9.4.3 Input Edge-Time Mode.......................................................................................... 316
9.4.4 PWM Mode ....................................................................................................... 316
9.5 Timer Registers ........................................................................................................... 317
9.5.1 GPTMCFG Register (offset = 0h) [reset = 0h]............................................................... 318
9.5.2 GPTMTAMR Register (offset = 4h) [reset = 0h]............................................................. 319
9.5.3 GPTMTBMR Register (offset = 8h) [reset = 0h]............................................................. 321
9.5.4 GPTMCTL Register (offset = Ch) [reset = 0h] ............................................................... 323
9.5.5 GPTMIMR Register (offset = 18h) [reset = 0h] .............................................................. 325
9.5.6 GPTMRIS Register (offset = 1Ch) [reset = 0h] .............................................................. 327
9.5.7 GPTMMIS Register (offset = 20h) [reset = 0h] .............................................................. 329
9.5.8 GPTMICR Register (offset = 24h) [reset = 0h]............................................................... 331
9.5.9 GPTMTAILR Register (offset = 28h) [reset = FFFFFFFFh]................................................ 333
9.5.10 GPTMTBILR Register (offset = 2Ch) [reset = FFFFh]..................................................... 334
9.5.11 GPTMTAMATCHR Register (offset = 30h) [reset = FFFFFFFFh] ....................................... 335
9.5.12 GPTMTBMATCHR Register (offset = 34h) [reset = FFFFh].............................................. 336
9.5.13 GPTMTAPR Register (offset = 38h) [reset = 0h]........................................................... 337
9.5.14 GPTMTBPR Register (offset = 3Ch) [reset = 0h]........................................................... 338

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9.5.15 GPTMTAPMR Register (offset = 40h) [reset = 0h]......................................................... 339
9.5.16 GPTMTBPMR Register (offset = 44h) [reset = 0h]......................................................... 340
9.5.17 GPTMTAR Register (offset = 48h) [reset = FFFFFFFFh]................................................. 341
9.5.18 GPTMTBR Register (offset = 4Ch) [reset = FFFFh] ....................................................... 342
9.5.19 GPTMTAV Register (offset = 50h) [reset = FFFFFFFFh] ................................................. 343
9.5.20 GPTMTBV Register (offset = 54h) [reset = FFFFh]........................................................ 344
9.5.21 GPTMDMAEV Register (offset = 6Ch) [reset = 0h] ........................................................ 345
10 Watchdog Timer ............................................................................................................... 347
10.1 Overview................................................................................................................... 348
10.1.1 Block Diagram................................................................................................... 348
10.2 Functional Description.................................................................................................... 349
10.2.1 Initialization and Configuration................................................................................ 349
10.3 WATCHDOG Registers.................................................................................................. 350
10.3.1 WDTLOAD Register (offset = 0h) [reset = FFFFFFFFh] .................................................. 351
10.3.2 WDTVALUE Register (offset = 4h) [reset = FFFFFFFFh]................................................. 352
10.3.3 WDTCTL Register (offset = 8h) [reset = 80000000h]...................................................... 353
10.3.4 WDTICR Register (offset = Ch) [reset = 0h] ................................................................ 354
10.3.5 WDTRIS Register (offset = 10h) [reset = 0h] ............................................................... 355
10.3.6 WDTTEST Register (offset = 418h) [reset = 0h] ........................................................... 356
10.3.7 WDTLOCK Register (offset = C00h) [reset = 0h]........................................................... 357
10.4 MCU Watchdog Controller Usage Caveats ........................................................................... 358
10.4.1 System Watchdog .............................................................................................. 358
10.4.2 System Watchdog Recovery Sequence..................................................................... 360
11 SD Host Controller Interface .............................................................................................. 361
11.1 Overview................................................................................................................... 362
11.2 SD Host Features......................................................................................................... 362
11.3 1-Bit SD Interface......................................................................................................... 362
11.3.1 Clock and Reset Management................................................................................ 364
11.4 Initialization and Configuration Using Peripheral APIs............................................................... 364
11.4.1 Basic Initialization and Configuration......................................................................... 364
11.4.2 Sending Command............................................................................................. 365
11.4.3 Card Detection and Initialization.............................................................................. 366
11.4.4 Block Read ...................................................................................................... 368
11.4.5 Block Write ...................................................................................................... 369
11.5 Performance and Testing................................................................................................ 369
11.6 Peripheral Library APIs .................................................................................................. 370
11.7 SD-HOST Registers...................................................................................................... 375
11.7.1 MMCHS_CSRE Register (Offset = 124h) [reset = 0h]..................................................... 376
11.7.2 MMCHS_CON Register (Offset = 12Ch) [reset = 0h]...................................................... 377
11.7.3 MMCHS_BLK Register (Offset = 204h) [reset = 0h]....................................................... 379
11.7.4 MMCHS_ARG Register (Offset = 208h) [reset = 0h] ...................................................... 380
11.7.5 MMCHS_CMD Register (Offset = 20Ch) [reset = 0h]...................................................... 381
11.7.6 MMCHS_RSP10 Register (Offset = 210h) [reset = 0h].................................................... 383
11.7.7 MMCHS_RSP32 Register (Offset = 214h) [reset = 0h].................................................... 384
11.7.8 MMCHS_RSP54 Register (Offset = 218h) [reset = 0h].................................................... 385
11.7.9 MMCHS_RSP76 Register (Offset = 21Ch) [reset = 0h] ................................................... 386
11.7.10 MMCHS_DATA Register (Offset = 220h) [reset = 0h] ................................................... 387
11.7.11 MMCHS_PSTATE Register (Offset = 224h) [reset = 0h] ................................................ 388
11.7.12 MMCHS_HCTL Register (Offset = 228h) [reset = 0h].................................................... 390
11.7.13 MMCHS_SYSCTL Register (Offset = 22Ch) [reset = 0h]................................................ 391
11.7.14 MMCHS_STAT Register (Offset = 230h) [reset = 0h].................................................... 393
11.7.15 MMCHS_IE Register (Offset = 234h) [reset = 0h] ........................................................ 397
11.7.16 MMCHS_ISE Register (Offset = 238h) [reset = 0h] ...................................................... 399

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12 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port................................................... 401
12.1 Overview................................................................................................................... 402
12.1.1 I2S Format....................................................................................................... 402
12.2 Functional Description.................................................................................................... 403
12.3 Programming Model...................................................................................................... 403
12.3.1 Clock and Reset Management................................................................................ 403
12.3.2 I2S Data Port Interface......................................................................................... 404
12.3.3 Initialization and Configuration................................................................................ 404
12.4 Peripheral Library APIs for I2S Configuration......................................................................... 406
12.4.1 Basic APIs for Enabling and Configuring the Interface.................................................... 406
12.4.2 APIs for Data Access if DMA is Not Used................................................................... 408
12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral....................... 409
12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral........................................ 413
12.5 I2S Registers.............................................................................................................. 415
12.5.1 AFIFOREV Register (Offset = 0h) [reset = 0h] ............................................................. 417
12.5.2 WFIFOCTL Register (Offset = 10h) [reset = 1004h]....................................................... 418
12.5.3 PDIR Register (Offset = 14h) [reset = 0h]................................................................... 419
12.5.4 RFIFOCTL Register (Offset = 18h) [reset = 1004h]........................................................ 421
12.5.5 RFIFOSTS Register (Offset = 1Ch) [reset = 0h]............................................................ 422
12.5.6 GBLCTL Register (Offset = 44h) [reset = 0h]............................................................... 423
12.5.7 RGBLCTL Register (Offset = 60h) [reset = 0h]............................................................. 425
12.5.8 RMASK Register (Offset = 64h) [reset = 0h]................................................................ 427
12.5.9 RFMT Register (Offset = 68h) [reset = 0h].................................................................. 428
12.5.10 AFSRCTL Register (Offset = 6Ch) [reset = 0h] ........................................................... 430
12.5.11 RTDM Register (Offset = 78h) [reset = 0h]................................................................ 431
12.5.12 RINTCTL Register (Offset = 7Ch) [reset = 0h]............................................................ 432
12.5.13 RSTAT Register (Offset = 80h) [reset = 0h]............................................................... 434
12.5.14 RSLOT Register (Offset = 84h) [reset = 0h]............................................................... 436
12.5.15 REVTCTL Register (Offset = 8Ch) [reset = 0h] ........................................................... 437
12.5.16 XGBLCTL Register (Offset = A0h) [reset = 0h] ........................................................... 438
12.5.17 XMASK Register (Offset = A4h) [reset = 0h] .............................................................. 440
12.5.18 XFMT Register (Offset = A8h) [reset = 0h] ................................................................ 441
12.5.19 AFSXCTL Register (Offset = ACh) [reset = 0h]........................................................... 443
12.5.20 ACLKXCTL Register (Offset = B0h) [reset = 60h]........................................................ 444
12.5.21 AHCLKXCTL Register (Offset = B4h) [reset = 8000h] ................................................... 445
12.5.22 XTDM Register (Offset = B8h) [reset = 0h]................................................................ 446
12.5.23 XINTCTL Register (Offset = BCh) [reset = 0h]............................................................ 447
12.5.24 XSTAT Register (Offset = C0h) [reset = 0h]............................................................... 449
12.5.25 XSLOT Register (Offset = C4h) [reset = 17Fh] ........................................................... 451
12.5.26 XEVTCTL Register (Offset = CCh) [reset = 0h]........................................................... 452
12.5.27 SRCTLn Register (Offset = 180h) [reset = 0h]............................................................ 453
12.5.28 XBUFn Register (Offset = 200h) [reset = 0h].............................................................. 455
12.5.29 RBUFn Register (Offset = 280h) [reset = 0h] ............................................................. 456
13 Analog-to-Digital Converter (ADC) ...................................................................................... 457
13.1 Overview................................................................................................................... 458
13.2 Key Features .............................................................................................................. 458
13.3 ADC Register Mapping................................................................................................... 459
13.4 ADC_MODULE Registers ............................................................................................... 460
13.4.1 ADC Register Description ..................................................................................... 460
13.5 Initialization and Configuration ......................................................................................... 479
13.6 Peripheral Library APIs for ADC Operation ........................................................................... 479
13.6.1 Overview......................................................................................................... 479
13.6.2 Configuring the ADC Channels ............................................................................... 479

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13.6.3 Basic APIs for Enabling and Configuring the Interface.................................................... 480
13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup] ........................................ 481
13.6.5 APIs for Interrupt Usage ....................................................................................... 482
13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples........................................ 485
14 Parallel Camera Interface Module ....................................................................................... 487
14.1 Overview................................................................................................................... 488
14.2 Image Sensor Interface .................................................................................................. 488
14.3 Functional Description.................................................................................................... 489
14.3.1 Modes of Operation ............................................................................................ 489
14.3.2 FIFO Buffer...................................................................................................... 492
14.3.3 Reset ............................................................................................................. 492
14.3.4 Clock Generation ............................................................................................... 492
14.3.5 Interrupt Generation............................................................................................ 493
14.3.6 DMA Interface................................................................................................... 493
14.4 Programming Model...................................................................................................... 494
14.4.1 Camera Core Reset............................................................................................ 494
14.4.2 Enable the Picture Acquisition ................................................................................ 494
14.4.3 Disable the Picture Acquisition................................................................................ 495
14.5 Interrupt Handling......................................................................................................... 495
14.5.1 FIFO_OF_IRQ (FIFO Overflow) .............................................................................. 495
14.5.2 FIFO_UF_IRQ (FIFO Underflow)............................................................................. 495
14.6 Camera Registers ........................................................................................................ 496
14.6.1 CC_SYSCONFIG Register (Offset = 10h) [reset = 0h].................................................... 497
14.6.2 CC_SYSSTATUS Register (Offset = 14h) [reset = X] ..................................................... 498
14.6.3 CC_IRQSTATUS Register (Offset = 18h) [reset = 0h]..................................................... 499
14.6.4 CC_IRQENABLE Register (Offset = 1Ch) [reset = 0h].................................................... 501
14.6.5 CC_CTRL Register (Offset = 40h) [reset = 1001h] ........................................................ 503
14.6.6 CC_CTRL_DMA Register (Offset = 44h) [reset = 207h] .................................................. 505
14.6.7 CC_CTRL_XCLK Register (Offset = 48h) [reset = 0h] .................................................... 506
14.6.8 CC_FIFODATA Register (Offset = 4Ch) [reset = X] ....................................................... 507
14.7 Peripheral Library APIs .................................................................................................. 508
14.8 Developer’s Guide........................................................................................................ 511
14.8.1 Using Peripheral Driver APIs for Capturing an Image ..................................................... 511
14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors................................. 513
15 Power, Reset, and Clock Management................................................................................. 515
15.1 Overview................................................................................................................... 516
15.1.1 Power Management Unit (PMU).............................................................................. 516
15.1.2 VBAT Wide-Voltage Connection.............................................................................. 517
15.1.3 Supply Brownout and Blackout ............................................................................... 517
15.1.4 Application Processor Power Modes......................................................................... 518
15.2 Power Management Control Architecture ............................................................................. 519
15.2.1 Global Power-Reset-Clock Manager (GPRCM) ............................................................ 520
15.2.2 Application Reset-Clock Manager (ARCM) ................................................................. 522
15.3 PRCM APIs................................................................................................................ 522
15.3.1 MCU Initialization ............................................................................................... 522
15.3.2 Reset Control.................................................................................................... 522
15.3.3 Peripheral Reset................................................................................................ 522
15.3.4 Reset Cause..................................................................................................... 523
15.3.5 Clock Control.................................................................................................... 523
15.3.6 Low-Power Modes.............................................................................................. 524
15.3.7 Sleep (SLEEP).................................................................................................. 524
15.3.8 Low-Power Deep Sleep (LPDS).............................................................................. 525
15.3.9 Hibernate (HIB) ................................................................................................. 526

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15.3.10 Slow Clock Counter........................................................................................... 528
15.4 Peripheral Macros ........................................................................................................ 529
15.5 Power Management Framework........................................................................................ 529
15.6 PRCM Registers .......................................................................................................... 529
15.6.1 CAMCLKCFG Register (offset = 0h) [reset = 0h]........................................................... 531
15.6.2 CAMCLKEN Register (offset = 4h) [reset = 0h] ............................................................ 532
15.6.3 CAMSWRST Register (offset = 8h) [reset = 0h]............................................................ 533
15.6.4 MCASPCLKEN Register (offset = 14h) [reset = 0h] ....................................................... 534
15.6.5 MCASPSWRST Register (offset = 18h) [reset = 0h]....................................................... 535
15.6.6 SDIOMCLKCFG Register (offset = 20h) [reset = 0h] ...................................................... 536
15.6.7 SDIOMCLKEN Register (offset = 24h) [reset = 0h] ........................................................ 537
15.6.8 SDIOMSWRST Register (offset = 28h) [reset = 0h] ....................................................... 538
15.6.9 APSPICLKCFG Register (offset = 2Ch) [reset = 0h]....................................................... 539
15.6.10 APSPICLKEN Register (offset = 30h) [reset = 0h] ....................................................... 540
15.6.11 APSPISWRST Register (offset = 34h) [reset = 0h]....................................................... 541
15.6.12 DMACLKEN Register (offset = 48h) [reset = 0h] ......................................................... 542
15.6.13 DMASWRST Register (offset = 4Ch) [reset = 0h] ........................................................ 543
15.6.14 GPIO0CLKEN Register (offset = 50h) [reset = 0h] ....................................................... 544
15.6.15 GPIO0SWRST Register (offset = 54h) [reset = 0h] ...................................................... 545
15.6.16 GPIO1CLKEN Register (offset = 58h) [reset = 0h] ....................................................... 546
15.6.17 GPIO1SWRST Register (offset = 5Ch) [reset = 0h]...................................................... 547
15.6.18 GPIO2CLKEN Register (offset = 60h) [reset = 0h] ....................................................... 548
15.6.19 GPIO2SWRST Register (offset = 64h) [reset = 0h] ...................................................... 549
15.6.20 GPIO3CLKEN Register (offset = 68h) [reset = 0h] ....................................................... 550
15.6.21 GPIO3SWRST Register (offset = 6Ch) [reset = 0h]...................................................... 551
15.6.22 GPIO4CLKEN Register (offset = 70h) [reset = 0h] ....................................................... 552
15.6.23 GPIO4SWRST Register (offset = 74h) [reset = 0h] ...................................................... 553
15.6.24 WDTCLKEN Register (offset = 78h) [reset = 0h] ......................................................... 554
15.6.25 WDTSWRST Register (offset = 7Ch) [reset = 0h] ........................................................ 555
15.6.26 UART0CLKEN Register (offset = 80h) [reset = 0h]....................................................... 556
15.6.27 UART0SWRST Register (offset = 84h) [reset = 0h]...................................................... 557
15.6.28 UART1CLKEN Register (offset = 88h) [reset = 0h]....................................................... 558
15.6.29 UART1SWRST Register (offset = 8Ch) [reset = 0h] ..................................................... 559
15.6.30 GPT0CLKCFG Register (offset = 90h) [reset = 0h] ...................................................... 560
15.6.31 GPT0SWRST Register (offset = 94h) [reset = 0h]........................................................ 561
15.6.32 GPT1CLKEN Register (offset = 98h) [reset = 0h] ........................................................ 562
15.6.33 GPT1SWRST Register (offset = 9Ch) [reset = 0h] ....................................................... 563
15.6.34 GPT2CLKEN Register (offset = A0h) [reset = 0h]........................................................ 564
15.6.35 GPT2SWRST Register (offset = A4h) [reset = 0h] ....................................................... 565
15.6.36 GPT3CLKEN Register (offset = A8h) [reset = 0h]........................................................ 566
15.6.37 GPT3SWRST Register (offset = ACh) [reset = 0h]....................................................... 567
15.6.38 MCASPCLKCFG0 Register (offset = B0h) [reset = A0000h]............................................ 568
15.6.39 MCASPCLKCFG1 Register (offset = B4h) [reset = 0h] .................................................. 569
15.6.40 I2CLCKEN Register (offset = D8h) [reset = 0h]........................................................... 570
15.6.41 I2CSWRST Register (offset = DCh) [reset = 0h].......................................................... 571
15.6.42 LPDSREQ Register (offset = E4h) [reset = 0h] ........................................................... 572
15.6.43 TURBOREQ Register (offset = ECh) [reset = 0h] ........................................................ 573
15.6.44 DSLPWAKECFG Register (offset = 108h) [reset = 0h] .................................................. 574
15.6.45 DSLPTIMRCFG Register (offset = 10Ch) [reset = 0h] ................................................... 575
15.6.46 SLPWAKEEN Register (offset = 110h) [reset = 0h] ...................................................... 576
15.6.47 SLPTMRCFG Register (offset = 114h) [reset = 0h] ...................................................... 577
15.6.48 WAKENWP Register (offset = 118h) [reset = 0h]......................................................... 578
15.6.49 RCM_IS Register (offset = 120h) [reset = 0h]............................................................. 579

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15.6.50 RCM_IEN Register (offset = 124h) [reset = 0h]........................................................... 580
16 I/O Pads and Pin Multiplexing............................................................................................. 581
16.1 Overview................................................................................................................... 582
16.2 I/O Pad Electrical Specifications........................................................................................ 583
16.3 Analog and Digital Pin Multiplexing .................................................................................... 584
16.4 Special Analog/Digital Pins.............................................................................................. 584
16.4.1 Pins 45 and 52.................................................................................................. 584
16.4.2 Pins 29 and 30.................................................................................................. 584
16.4.3 Pins 57, 58, 59, and 60 ........................................................................................ 584
16.5 Analog Mux Control Registers .......................................................................................... 587
16.6 Pins Available for Applications.......................................................................................... 589
16.7 Functional Pin Mux Configurations..................................................................................... 591
16.8 Pin Mapping Recommendations........................................................................................ 603
16.8.1 Pad Configuration Registers for Application Pins .......................................................... 604
16.8.2 PAD Behavior During Reset and Hibernate................................................................. 605
16.8.3 Control Architecture ............................................................................................ 606
16.8.4 CC32xx Pin-mux Examples ................................................................................... 606
16.8.5 Wake on Pad.................................................................................................... 609
16.8.6 Sense on Power ................................................................................................ 610
17 Advance Encryption Standard Accelerator (AES) ................................................................. 611
17.1 AES Overview............................................................................................................. 612
17.2 AES Functional Description ............................................................................................. 612
17.2.1 AES Block Diagram ............................................................................................ 612
17.2.2 AES Algorithm................................................................................................... 615
17.2.3 AES Operating Modes ......................................................................................... 616
17.2.4 Hardware Requests ............................................................................................ 626
17.3 AES Module Programming Guide ...................................................................................... 627
17.3.1 AES Low-Level Programming Models ....................................................................... 627
17.4 AES Registers............................................................................................................. 632
17.4.1 AES_KEY2_6 Register (Offset = 0h) [reset = 0h].......................................................... 633
17.4.2 AES_KEY2_7 Register (Offset = 4h) [reset = 0h].......................................................... 633
17.4.3 AES_KEY2_4 Register (Offset = 8h) [reset = 0h].......................................................... 634
17.4.4 AES_KEY2_5 Register (Offset = Ch) [reset = 0h].......................................................... 634
17.4.5 AES_KEY2_2 Register (Offset = 10h) [reset = 0h]......................................................... 635
17.4.6 AES_KEY2_3 Register (Offset = 14h) [reset = 0h]......................................................... 635
17.4.7 AES_KEY2_0 Register (Offset = 18h) [reset = 0h]......................................................... 636
17.4.8 AES_KEY2_1 Register (Offset = 1Ch) [reset = 0h] ........................................................ 636
17.4.9 AES_KEY1_6 Register (Offset = 20h) [reset = 0h]......................................................... 637
17.4.10 AES_KEY1_7 Register (Offset = 24h) [reset = 0h]....................................................... 637
17.4.11 AES_KEY1_4 Register (Offset = 28h) [reset = 0h]....................................................... 638
17.4.12 AES_KEY1_5 Register (Offset = 2Ch) [reset = 0h]....................................................... 638
17.4.13 AES_KEY1_2 Register (Offset = 30h) [reset = 0h]....................................................... 639
17.4.14 AES_KEY1_3 Register (Offset = 34h) [reset = 0h]....................................................... 639
17.4.15 AES_KEY1_0 Register (Offset = 38h) [reset = 0h]....................................................... 640
17.4.16 AES_KEY1_1 Register (Offset = 3Ch) [reset = 0h]....................................................... 640
17.4.17 AES_IV_IN_0 Register (Offset = 40h) [reset = 0h] ....................................................... 641
17.4.18 AES_IV_IN_1 Register (Offset = 44h) [reset = 0h] ....................................................... 641
17.4.19 AES_IV_IN_2 Register (Offset = 48h) [reset = 0h] ....................................................... 642
17.4.20 AES_IV_IN_3 Register (Offset = 4Ch) [reset = 0h]....................................................... 642
17.4.21 AES_CTRL Register (Offset = 50h) [reset = X]........................................................... 643
17.4.22 AES_C_LENGTH_0 Register (Offset = 54h) [reset = 0h]................................................ 646
17.4.23 AES_C_LENGTH_1 Register (Offset = 58h) [reset = X]................................................. 647
17.4.24 AES_AUTH_LENGTH Register (Offset = 5Ch) [reset = 0h]............................................. 648

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17.4.25 AES_DATA_IN_0 Register (Offset = 60h) [reset = 0h]................................................... 649
17.4.26 AES_DATA_IN_1 Register (Offset = 64h) [reset = 0h]................................................... 649
17.4.27 AES_DATA_IN_2 Register (Offset = 68h) [reset = 0h]................................................... 650
17.4.28 AES_DATA_IN_3 Register (Offset = 6Ch) [reset = 0h] .................................................. 650
17.4.29 AES_TAG_OUT_0 Register (Offset = 70h) [reset = 0h] ................................................. 651
17.4.30 AES_TAG_OUT_1 Register (Offset = 74h) [reset = 0h] ................................................. 651
17.4.31 AES_TAG_OUT_2 Register (Offset = 78h) [reset = 0h] ................................................. 652
17.4.32 AES_TAG_OUT_3 Register (Offset = 7Ch) [reset = 0h]................................................. 652
17.4.33 AES_REVISION Register (Offset = 80h) [reset = X] ..................................................... 653
17.4.34 AES_SYSCONFIG Register (Offset = 84h) [reset = X] .................................................. 655
17.4.35 AES_IRQSTATUS Register (Offset = 8Ch) [reset = X] .................................................. 656
17.4.36 AES_IRQENABLE Register (Offset = 90h) [reset = X]................................................... 657
17.4.37 CRYPTOCLKEN Register (Offset = B8h) [reset = X]..................................................... 658
17.4.38 DTHE_AES_IM Register (Offset = 820h) [reset = X]..................................................... 659
17.4.39 DTHE_AES_RIS Register (Offset = 824h) [reset = X] ................................................... 660
17.4.40 DTHE_AES_MIS Register (Offset = 828h) [reset = X]................................................... 661
17.4.41 DTHE_AES_IC Register (Offset = 82Ch) [reset = X]..................................................... 662
18 Data Encryption Standard Accelerator (DES) ....................................................................... 663
18.1 DES Functional Description ............................................................................................. 664
18.2 DES Block Diagram ...................................................................................................... 664
18.2.1 µDMA Control ................................................................................................... 665
18.2.2 Interrupt Control................................................................................................. 665
18.2.3 Register Interface............................................................................................... 666
18.2.4 DES Enginer..................................................................................................... 666
18.3 DES-Supported Modes of Operation................................................................................... 666
18.3.1 ECB Feedback Mode .......................................................................................... 666
18.4 DES Module Programming Guide – Low-Level Programming Models ............................................ 668
18.4.1 Surrounding Modules Global Initialization................................................................... 668
18.4.2 Operational Modes Configuration ............................................................................ 669
18.4.3 DES Events Servicing.......................................................................................... 671
18.5 DES Registers............................................................................................................. 673
18.5.1 DTHE_DES_IM Register (Offset = 830h) [reset = Dh]..................................................... 674
18.5.2 DTHE_DES_RIS Register (Offset = 834h) [reset = 0h] ................................................... 675
18.5.3 DTHE_DES_MIS Register (Offset = 838h) [reset = 0h] ................................................... 676
18.5.4 DTHE_DES_IC Register (Offset = 83Ch) [reset = 0h]..................................................... 677
18.5.5 DES_KEY3_L Register (Offset = 1000h) [reset = 0h] ..................................................... 678
18.5.6 DES_KEY3_H Register (Offset = 1004h) [reset = 0h]..................................................... 679
18.5.7 DES_KEY2_L Register (Offset = 1008h) [reset = 0h] ..................................................... 680
18.5.8 DES_KEY2_H Register (Offset = 100Ch) [reset = 0h] .................................................... 681
18.5.9 DES_KEY1_L Register (Offset = 1010h) [reset = 0h] ..................................................... 682
18.5.10 DES_KEY1_H Register (Offset = 1014h) [reset = 0h] ................................................... 683
18.5.11 DES_IV_L Register (Offset = 1018h) [reset = 0h] ........................................................ 684
18.5.12 DES_IV_H Register (Offset = 101Ch) [reset = 0h] ....................................................... 685
18.5.13 DES_CTRL Register (Offset = 1020h) [reset = 80000000h] ............................................ 686
18.5.14 DES_LENGTH Register (Offset = 1024h) [reset = 0h]................................................... 687
18.5.15 DES_DATA_L Register (Offset = 1028h) [reset = 0h].................................................... 688
18.5.16 DES_DATA_H Register (Offset = 102Ch) [reset = 0h]................................................... 689
18.5.17 DES_SYSCONFIG Register (Offset = 1034h) [reset = 0h].............................................. 690
18.5.18 DES_IRQSTATUS Register (Offset = 103Ch) [reset = 0h].............................................. 691
18.5.19 DES_IRQENABLE Register (Offset = 1040h) [reset = 0h] .............................................. 692
19 SHA/MD5 Accelerator........................................................................................................ 693
19.1 SHA/MD5 Functional Description....................................................................................... 694
19.1.1 SHA/MD5 Block Diagram...................................................................................... 694

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19.1.2 µDMA and Interrupt Requests ................................................................................ 695
19.1.3 Operation Description.......................................................................................... 695
19.1.4 SHA/MD5 Programming Guide ............................................................................... 701
19.2 SHA-MD5 Registers...................................................................................................... 705
19.2.1 SHAMD5_ODIGEST_A Register (Offset = 0h) [reset = 0h]............................................... 708
19.2.2 SHAMD5_ODIGEST_B Register (Offset = 4h) [reset = 0h]............................................... 709
19.2.3 SHAMD5_ODIGEST_C Register (Offset = 8h) [reset = 0h]............................................... 710
19.2.4 SHAMD5_ODIGEST_D Register (Offset = Ch) [reset = 0h].............................................. 711
19.2.5 SHAMD5_ODIGEST_E Register (Offset = 10h) [reset = 0h] ............................................. 712
19.2.6 SHAMD5_ODIGEST_F Register (Offset = 14h) [reset = 0h] ............................................. 713
19.2.7 SHAMD5_ODIGEST_G Register (Offset = 18h) [reset = 0h]............................................. 714
19.2.8 SHAMD5_ODIGEST_H Register (Offset = 1Ch) [reset = 0h]............................................. 715
19.2.9 SHAMD5_IDIGEST_A Register (Offset = 20h) [reset = 0h]............................................... 716
19.2.10 SHAMD5_IDIGEST_B Register (Offset = 24h) [reset = 0h]............................................. 717
19.2.11 SHAMD5_IDIGEST_C Register (Offset = 28h) [reset = 0h]............................................. 718
19.2.12 SHAMD5_IDIGEST_D Register (Offset = 2Ch) [reset = 0h] ............................................ 719
19.2.13 SHAMD5_IDIGEST_E Register (Offset = 30h) [reset = 0h]............................................. 720
19.2.14 SHAMD5_IDIGEST_F Register (Offset = 34h) [reset = 0h] ............................................. 721
19.2.15 SHAMD5_IDIGEST_G Register (Offset = 38h) [reset = 0h]............................................. 722
19.2.16 SHAMD5_IDIGEST_H Register (Offset = 3Ch) [reset = 0h] ............................................ 723
19.2.17 SHAMD5_DIGEST_COUNT Register (Offset = 40h) [reset = 0h]...................................... 724
19.2.18 SHAMD5_MODE Register (Offset = 44h) [reset = X] .................................................... 725
19.2.19 SHAMD5_LENGTH Register (Offset = 48h) [reset = 0h] ................................................ 727
19.2.20 SHAMD5_DATA0_IN Register (Offset = 80h) [reset = 0h] .............................................. 729
19.2.21 SHAMD5_DATA1_IN Register (Offset = 84h) [reset = 0h] .............................................. 730
19.2.22 SHAMD5_DATA2_IN Register (Offset = 88h) [reset = 0h] .............................................. 731
19.2.23 SHAMD5_DATA3_IN Register (Offset = 8Ch) [reset = 0h].............................................. 732
19.2.24 SHAMD5_DATA4_IN Register (Offset = 90h) [reset = 0h] .............................................. 733
19.2.25 SHAMD5_DATA5_IN Register (Offset = 94h) [reset = 0h] .............................................. 734
19.2.26 SHAMD5_DATA6_IN Register (Offset = 98h) [reset = 0h] .............................................. 735
19.2.27 SHAMD5_DATA7_IN Register (Offset = 9Ch) [reset = 0h].............................................. 736
19.2.28 SHAMD5_DATA8_IN Register (Offset = A0h) [reset = 0h].............................................. 737
19.2.29 SHAMD5_DATA9_IN Register (Offset = A4h) [reset = 0h].............................................. 738
19.2.30 SHAMD5_DATA10_IN Register (Offset = A8h) [reset = 0h] ............................................ 739
19.2.31 SHAMD5_DATA11_IN Register (Offset = ACh) [reset = 0h]............................................ 740
19.2.32 SHAMD5_DATA12_IN Register (Offset = B0h) [reset = 0h] ............................................ 741
19.2.33 SHAMD5_DATA13_IN Register (Offset = B4h) [reset = 0h] ............................................ 742
19.2.34 SHAMD5_DATA14_IN Register (Offset = B8h) [reset = 0h] ............................................ 743
19.2.35 SHAMD5_DATA15_IN Register (Offset = BCh) [reset = 0h]............................................ 744
19.2.36 SHAMD5_SYSCONFIG Register (Offset = 110h) [reset = X]........................................... 745
19.2.37 SHAMD5_IRQSTATUS Register (Offset = 118h) [reset = X] ........................................... 746
19.2.38 SHAMD5_IRQENABLE Register (Offset = 11Ch) [reset = X]........................................... 747
19.2.39 DTHE_SHA_IM Register (Offset = 810h) [reset = X]..................................................... 748
19.2.40 DTHE_SHA_RIS Register (Offset = 814h) [reset = X] ................................................... 749
19.2.41 DTHE_SHA_MIS Register (Offset = 818h) [reset = X]................................................... 750
19.2.42 DTHE_SHA_IC Register (Offset = 81Ch) [reset = X]..................................................... 751
20 Cyclical Redundancy Check (CRC) ..................................................................................... 752
20.1 Functional Description.................................................................................................... 753
20.1.1 CRC Support.................................................................................................... 753
20.2 Initialization and Configuration.......................................................................................... 755
20.2.1 CRC Initialization and Configuration ......................................................................... 755
20.3 CRC Registers ............................................................................................................ 756
20.3.1 CRCCTRL Register (Offset = C00h) [reset = 0h]........................................................... 757

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20.3.2 CRCSEED Register (Offset = C10h) [reset = 0h] .......................................................... 759
20.3.3 CRCDIN Register (Offset = C14h) [reset = 0h]............................................................. 760
20.3.4 CRCRSLTPP Register (Offset = C18h) [reset = 0h]....................................................... 761
21 On-Chip Parallel Flash....................................................................................................... 762
21.1 Flash Memory Configuration ............................................................................................ 763
21.2 Interrupts................................................................................................................... 763
21.3 Flash Memory Programming ............................................................................................ 763
21.4 32-Word Flash Memory Write Buffer................................................................................... 764
21.5 Flash Registers ........................................................................................................... 765
21.5.1 FMA Register (Offset = 0h) [reset = 0h] ..................................................................... 766
21.5.2 FMD Register (Offset = 4h) [reset = 0h]..................................................................... 767
21.5.3 FMC Register (Offset = 8h) [reset = 0h]..................................................................... 768
21.5.4 FCRIS Register (Offset = Ch) [reset = 0h] .................................................................. 770
21.5.5 FCIM Register (offset = 10h) [reset = 0h] ................................................................... 772
21.5.6 FCMISC Register (Offset = 14h) [reset = 0h]............................................................... 773
21.5.7 FMC2 Register (Offset = 20h) [reset = 0h].................................................................. 775
21.5.8 FWBVAL Register (Offset = 30h) [reset = 0h] .............................................................. 776
21.5.9 FWBn Register (Offset = 100h) [reset = 0h] ................................................................ 777
21.6 CC3235SF Boot Flow.................................................................................................... 778
21.7 Flash User Application and Memory Partition......................................................................... 778
21.8 Programming, Bootstrapping, and Updating the Flash User Application.......................................... 780
21.9 Image Authentication and Integrity Check............................................................................. 781
21.10 Debugging Flash User Application Using JTAG...................................................................... 783
A Software Development Kit Examples................................................................................... 784
B CC3235x Device Miscellaneous Registers............................................................................ 785
B.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh] .................................................................. 786
B.2 DMA_IMS Register (offset = 90h) [reset = 0h]........................................................................ 788
B.3 DMA_IMC Register (offset = 94h) [reset = 0h]........................................................................ 790
B.4 DMA_ICR Register (offset = 9Ch) [reset = 0h] ....................................................................... 792
B.5 DMA_MIS Register (offset = A0h) [reset = 0h] ....................................................................... 794
B.6 DMA_RIS Register (offset = A4h) [reset = 0h]........................................................................ 796
B.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]................................................................... 798

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List of Figures
List of Figures
1-1. CC32xx MCU and Wi-Fi®System-on-Chip.............................................................................. 41
2-1. Application CPU Block Diagram.......................................................................................... 52
2-2. TPIU Block Diagram ....................................................................................................... 53
2-3. Cortex®-M4 Register Set .................................................................................................. 55
2-4. Data Storage................................................................................................................ 61
2-5. Vector Table ................................................................................................................ 66
2-6. Exception Stack Frame.................................................................................................... 68
2-7. Power-Management Architecture in CC32xx SoC..................................................................... 72
3-1. ACTLR Register............................................................................................................ 84
3-2. STCTRL Register .......................................................................................................... 86
3-3. STRELOAD Register ...................................................................................................... 87
3-4. STCURRENT Register .................................................................................................... 88
3-5. EN_0 to EN_6 Register.................................................................................................... 89
3-6. DIS_0 to DIS_6 Register.................................................................................................. 90
3-7. PEND_0 to PEND_6 Register............................................................................................ 91
3-8. UNPEND_0 to UNPEND_6 Register .................................................................................... 92
3-9. ACTIVE_0 to ACTIVE_6 Register........................................................................................ 93
3-10. PRI_0 to PRI_49 Register................................................................................................. 94
3-11. CPUID Register............................................................................................................. 95
3-12. INTCTRL Register.......................................................................................................... 96
3-13. VTABLE Register........................................................................................................... 98
3-14. APINT Register............................................................................................................. 99
3-15. SYSCTRL Register....................................................................................................... 101
3-16. CFGCTRL Register....................................................................................................... 102
3-17. SYSPRI1 Register........................................................................................................ 104
3-18. SYSPRI2 Register........................................................................................................ 105
3-19. SYSPRI3 Register........................................................................................................ 106
3-20. SYSHNDCTRL Register ................................................................................................. 107
3-21. FAULTSTAT Register.................................................................................................... 110
3-22. HFAULTSTAT Register.................................................................................................. 114
3-23. FAULTDDR Register..................................................................................................... 115
3-24. SWTRIG Register......................................................................................................... 116
4-1. Ping-Pong Mode .......................................................................................................... 123
4-2. Memory Scatter-Gather Mode .......................................................................................... 124
4-3. Peripheral Scatter-Gather Mode........................................................................................ 125
4-4. DMA_SRCENDP Register............................................................................................... 129
4-5. DMA_DSTENDP Register............................................................................................... 129
4-6. DMA_CHCTL Register................................................................................................... 130
4-7. DMA_STAT Register..................................................................................................... 133
4-8. DMA_CFG Register ...................................................................................................... 134
4-9. DMA_CTLBASE Register................................................................................................ 135
4-10. DMA_ALTBASE Register................................................................................................ 136
4-11. DMA_WAITSTAT Register .............................................................................................. 137
4-12. DMA_SWREQ Register.................................................................................................. 138
4-13. DMA_USEBURSTSET Register........................................................................................ 139
4-14. DMA_USEBURSTCLR Register........................................................................................ 140
4-15. DMA_REQMASKSET Register ......................................................................................... 141

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4-16. DMA_REQMASKCLR Register......................................................................................... 142
4-17. DMA_ENASET Register ................................................................................................. 143
4-18. DMA_ENACLR Register................................................................................................. 144
4-19. DMA_ALTSET Register.................................................................................................. 145
4-20. DMA_ALTCLR Register.................................................................................................. 146
4-21. DMA_PRIOSET Register................................................................................................ 147
4-22. DMA_PRIOCLR Register................................................................................................ 148
4-23. DMA_ERRCLR Register................................................................................................. 149
4-24. DMA_CHASGN Register ................................................................................................ 150
4-25. DMA_CHMAP0 Register................................................................................................. 151
4-26. DMA_CHMAP1 Register................................................................................................. 152
4-27. DMA_CHMAP2 Register................................................................................................. 153
4-28. DMA_CHMAP3 Register................................................................................................. 154
4-29. DMA_PV Register ........................................................................................................ 155
5-1. Digital I/O Pads ........................................................................................................... 157
5-2. GPIODATA Write Example.............................................................................................. 158
5-3. GPIODATA Read Example.............................................................................................. 158
5-4. GPIODATA Register ..................................................................................................... 162
5-5. GPIODIR Register........................................................................................................ 163
5-6. GPIOIS Register .......................................................................................................... 164
5-7. GPIOIBE Register ........................................................................................................ 165
5-8. GPIOIEV Register ........................................................................................................ 166
5-9. GPIOIM Register.......................................................................................................... 167
5-10. GPIORIS Register ........................................................................................................ 168
5-11. GPIOMIS Register........................................................................................................ 169
5-12. GPIOICR Register........................................................................................................ 170
5-13. GPIO_TRIG_EN Register ............................................................................................... 171
6-1. UART Module Block Diagram........................................................................................... 175
6-2. UART Character Frame.................................................................................................. 176
6-3. UARTDR Register ........................................................................................................ 182
6-4. UARTRSR_UARTECR Register........................................................................................ 183
6-5. UARTFR Register ........................................................................................................ 185
6-6. UARTIBRD Register...................................................................................................... 187
6-7. UARTFBRD Register..................................................................................................... 188
6-8. UARTLCRH Register..................................................................................................... 189
6-9. UARTCTL Register....................................................................................................... 191
6-10. UARTIFLS Register ...................................................................................................... 193
6-11. UARTIM Register......................................................................................................... 194
6-12. UARTRIS Register........................................................................................................ 196
6-13. UARTMIS Register ....................................................................................................... 198
6-14. UARTICR Register ....................................................................................................... 200
6-15. UARTDMACTL Register................................................................................................. 202
7-1. I2C Block Diagram........................................................................................................ 205
7-2. I2C Bus Configuration.................................................................................................... 206
7-3. START and STOP Conditions .......................................................................................... 207
7-4. Complete Data Transfer With a 7-Bit Address........................................................................ 207
7-5. R/S Bit in First Byte....................................................................................................... 207
7-6. Data Validity During Bit Transfer on the I2C Bus..................................................................... 208
7-7. Master Single TRANSMIT ............................................................................................... 214

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7-8. Master Single RECEIVE................................................................................................. 215
7-9. Master TRANSMIT of Multiple Data Bytes ............................................................................ 216
7-10. Master RECEIVE of Multiple Data Bytes .............................................................................. 217
7-11. Master RECEIVE with Repeated START after Master TRANSMIT................................................ 218
7-12. Master TRANSMIT with Repeated START after Master RECEIVE................................................ 219
7-13. Slave Command Sequence ............................................................................................. 220
7-14. I2CMSA Register ......................................................................................................... 223
7-15. I2CMCS Register ......................................................................................................... 224
7-16. I2CMDR Register......................................................................................................... 229
7-17. I2CMTPR Register........................................................................................................ 230
7-18. I2CMIMR Register........................................................................................................ 231
7-19. I2CMRIS Register ........................................................................................................ 233
7-20. I2CMMIS Register ........................................................................................................ 235
7-21. I2CMICR Register ........................................................................................................ 237
7-22. I2CMCR Register......................................................................................................... 239
7-23. I2CMCLKOCNT Register................................................................................................ 240
7-24. I2CMBMON Register..................................................................................................... 241
7-25. I2CMBLEN Register...................................................................................................... 242
7-26. I2CMBCNT Register...................................................................................................... 243
7-27. I2CSOAR Register........................................................................................................ 244
7-28. I2CSCSR Register........................................................................................................ 245
7-29. I2CSDR Register.......................................................................................................... 247
7-30. I2CSIMR Register ........................................................................................................ 248
7-31. I2CSRIS Register......................................................................................................... 250
7-32. I2CSMIS Register......................................................................................................... 252
7-33. I2CSICR Register......................................................................................................... 254
7-34. I2CSOAR2 Register...................................................................................................... 256
7-35. I2CSACKCTL Register................................................................................................... 257
7-36. I2CFIFODATA Register.................................................................................................. 258
7-37. I2CFIFOCTL Register.................................................................................................... 259
7-38. I2CFIFOSTATUS Register .............................................................................................. 261
7-39. I2CPP Register............................................................................................................ 262
7-40. I2CPC Register ........................................................................................................... 263
8-1. SPI Block Diagram........................................................................................................ 265
8-2. SPI Full-Duplex Transmission (Example).............................................................................. 267
8-3. Phase and Polarity Combinations ...................................................................................... 268
8-4. Full-Duplex Single Transfer Format With PHA = 0................................................................... 269
8-5. Full-Duplex Single Transfer Format With PHA = 1................................................................... 270
8-6. Contiguous Transfers With SPIEN Kept Active (Two Data Pins Interface Mode)................................ 272
8-7. Transmit/Receive Mode With No FIFO Used ......................................................................... 274
8-8. Transmit/Receive Mode With Only Receive FIFO Enabled......................................................... 274
8-9. Transmit/Receive Mode With Only Transmit FIFO Used............................................................ 275
8-10. Transmit/Receive Mode With Both FIFO Directions Used .......................................................... 275
8-11. Buffer Almost Full Level (AFL).......................................................................................... 276
8-12. Buffer Almost Empty Level (AEL)....................................................................................... 276
8-13. 3-Pin Mode System Overview........................................................................................... 277
8-14. Flow Chart – Module Initialization ...................................................................................... 283
8-15. Flow Chart – Common Transfer Sequence ........................................................................... 284
8-16. Flow Chart – Transmit and Receive (Master and Slave)............................................................ 285

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List of Figures
8-17. Flow Chart – FIFO Mode Common Sequence (Master)............................................................. 286
8-18. Flow Chart – FIFO Mode Transmit and Receive With Word Count (Master)..................................... 288
8-19. Flow Chart – FIFO Mode Transmit and Receive without Word Count (Master).................................. 289
8-20. SPI_SYSCONFIG Register.............................................................................................. 291
8-21. SPI_SYSSTATUS Register.............................................................................................. 292
8-22. SPI_IRQSTATUS Register .............................................................................................. 293
8-23. SPI_IRQENABLE Register .............................................................................................. 295
8-24. SPI_MODULCTRL Register............................................................................................. 296
8-25. SPI_CHCONF Register.................................................................................................. 297
8-26. SPI_CHSTAT Register................................................................................................... 300
8-27. SPI_CHCTRL Register................................................................................................... 301
8-28. SPI_TX Register .......................................................................................................... 302
8-29. SPI_RX Register.......................................................................................................... 303
8-30. SPI_XFERLEVEL Register.............................................................................................. 304
9-1. GPTM Module Block Diagram .......................................................................................... 307
9-2. Input Edge-Count Mode Example, Counting Down .................................................................. 311
9-3. 16-Bit Input Edge-Time Mode Example................................................................................ 312
9-4. 16-Bit PWM Mode Example............................................................................................. 314
9-5. GPTMCFG Register...................................................................................................... 318
9-6. GPTMTAMR Register.................................................................................................... 319
9-7. GPTMTBMR Register.................................................................................................... 321
9-8. GPTMCTL Register....................................................................................................... 323
9-9. GPTMIMR Register....................................................................................................... 325
9-10. GPTMRIS Register ....................................................................................................... 327
9-11. GPTMMIS Register....................................................................................................... 329
9-12. GPTMICR Register....................................................................................................... 331
9-13. GPTMTAILR Register.................................................................................................... 333
9-14. GPTMTBILR Register.................................................................................................... 334
9-15. GPTMTAMATCHR Register............................................................................................. 335
9-16. GPTMTBMATCHR Register............................................................................................. 336
9-17. GPTMTAPR Register .................................................................................................... 337
9-18. GPTMTBPR Register .................................................................................................... 338
9-19. GPTMTAPMR Register .................................................................................................. 339
9-20. GPTMTBPMR Register .................................................................................................. 340
9-21. GPTMTAR Register ...................................................................................................... 341
9-22. GPTMTBR Register ...................................................................................................... 342
9-23. GPTMTAV Register ...................................................................................................... 343
9-24. GPTMTBV Register ...................................................................................................... 344
9-25. GPTMDMAEV Register.................................................................................................. 345
10-1. WDT Module Block Diagram............................................................................................ 348
10-2. WDTLOAD Register...................................................................................................... 351
10-3. WDTVALUE Register .................................................................................................... 352
10-4. WDTCTL Register ........................................................................................................ 353
10-5. WDTICR Register......................................................................................................... 354
10-6. WDTRIS Register......................................................................................................... 355
10-7. WDTTEST Register ...................................................................................................... 356
10-8. WDTLOCK Register...................................................................................................... 357
10-9. Watchdog Flow Chart .................................................................................................... 359
10-10. System Watchdog Recovery Sequence ............................................................................... 360

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List of Figures
11-1. SDHost Controller Interface Block Diagram........................................................................... 363
11-2. MMCHS_CSRE Register ................................................................................................ 376
11-3. MMCHS_CON Register.................................................................................................. 377
11-4. MMCHS_BLK Register................................................................................................... 379
11-5. MMCHS_ARG Register.................................................................................................. 380
11-6. MMCHS_CMD Register.................................................................................................. 381
11-7. MMCHS_RSP10 Register ............................................................................................... 383
11-8. MMCHS_RSP32 Register ............................................................................................... 384
11-9. MMCHS_RSP54 Register ............................................................................................... 385
11-10. MMCHS_RSP76 Register ............................................................................................... 386
11-11. MMCHS_DATA Register................................................................................................. 387
11-12. MMCHS_PSTATE Register ............................................................................................. 388
11-13. MMCHS_HCTL Register................................................................................................. 390
11-14. MMCHS_SYSCTL Register ............................................................................................. 391
11-15. MMCHS_STAT Register................................................................................................. 393
11-16. MMCHS_IE Register ..................................................................................................... 397
11-17. MMCHS_ISE Register ................................................................................................... 399
12-1. I2S Protocol................................................................................................................ 402
12-2. I2S Module................................................................................................................. 403
12-3. Logical Clock Path........................................................................................................ 404
12-4. AFIFOREV Register...................................................................................................... 417
12-5. WFIFOCTL Register...................................................................................................... 418
12-6. PDIR Register............................................................................................................. 419
12-7. RFIFOCTL Register ...................................................................................................... 421
12-8. RFIFOSTS Register...................................................................................................... 422
12-9. GBLCTL Register......................................................................................................... 423
12-10. RGBLCTL Register....................................................................................................... 425
12-11. RMASK Register.......................................................................................................... 427
12-12. RFMT Register............................................................................................................ 428
12-13. AFSRCTL Register ....................................................................................................... 430
12-14. RTDM Register............................................................................................................ 431
12-15. RINTCTL Register ........................................................................................................ 432
12-16. RSTAT Register........................................................................................................... 434
12-17. RSLOT Register .......................................................................................................... 436
12-18. REVTCTL Register ....................................................................................................... 437
12-19. XGBLCTL Register ....................................................................................................... 438
12-20. XMASK Register.......................................................................................................... 440
12-21. XFMT Register ............................................................................................................ 441
12-22. AFSXCTL Register ....................................................................................................... 443
12-23. ACLKXCTL Register ..................................................................................................... 444
12-24. AHCLKXCTL Register.................................................................................................... 445
12-25. XTDM Register............................................................................................................ 446
12-26. XINTCTL Register ........................................................................................................ 447
12-27. XSTAT Register........................................................................................................... 449
12-28. XSLOT Register........................................................................................................... 451
12-29. XEVTCTL Register ....................................................................................................... 452
12-30. SRCTLn Registers........................................................................................................ 453
12-31. XBUFn Registers ......................................................................................................... 455
12-32. RBUFn Registers ......................................................................................................... 456

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List of Figures
13-1. Architecture of the ADC Module in CC32xx........................................................................... 458
13-2. Operation of the ADC .................................................................................................... 459
13-3. ADC_CTRL Register ..................................................................................................... 461
13-4. ADC_CH0_IRQ_EN Register ........................................................................................... 462
13-5. ADC_CH2_IRQ_EN Register ........................................................................................... 463
13-6. ADC_CH4_IRQ_EN Register ........................................................................................... 464
13-7. ADC_CH6_IRQ_EN Register ........................................................................................... 465
13-8. ADC_CH0_IRQ_STATUS Register .................................................................................... 466
13-9. ADC_CH2_IRQ_STATUS Register .................................................................................... 467
13-10. ADC_CH4_IRQ_STATUS Register .................................................................................... 468
13-11. ADC_CH6_IRQ_STATUS Register .................................................................................... 469
13-12. ADC_DMA_MODE_EN Register ....................................................................................... 470
13-13. ADC_TIMER_CONFIGURATION Register............................................................................ 471
13-14. ADC_TIMER_CURRENT_COUNT Register .......................................................................... 471
13-15. CHANNEL0FIFODATA Register........................................................................................ 472
13-16. CHANNEL2FIFODATA Register........................................................................................ 472
13-17. CHANNEL4FIFODATA Register........................................................................................ 473
13-18. CHANNEL6FIFODATA Register........................................................................................ 473
13-19. ADC_CH0_FIFO_LVL Register......................................................................................... 474
13-20. ADC_CH2_FIFO_LVL Register......................................................................................... 475
13-21. ADC_CH4_FIFO_LVL Register......................................................................................... 476
13-22. ADC_CH6_FIFO_LVL Register......................................................................................... 477
13-23. ADC_CH_ENABLE Register ............................................................................................ 478
14-1. Camera Module Interfaces .............................................................................................. 488
14-2. Synchronization Signals and Frame Timing........................................................................... 489
14-3. Synchronization Signals and Data Timing............................................................................. 489
14-4. Different Scenarios of CAM_P_HS and CAM_P_VS ................................................................ 490
14-5. CAM_P_HS Toggles Between Pixels in Decimation................................................................. 490
14-6. Parallel Camera Interface State Machine ............................................................................. 491
14-7. FIFO Image Data Format................................................................................................ 491
14-8. Assertion and Deassertion of the DMA Request Signal............................................................. 494
14-9. CC_SYSCONFIG Register .............................................................................................. 497
14-10. CC_SYSSTATUS Register.............................................................................................. 498
14-11. CC_IRQSTATUS Register............................................................................................... 499
14-12. CC_IRQENABLE Register............................................................................................... 501
14-13. CC_CTRL Register....................................................................................................... 503
14-14. CC_CTRL_DMA Register ............................................................................................... 505
14-15. CC_CTRL_XCLK Register .............................................................................................. 506
14-16. CC_FIFODATA Register................................................................................................. 507
15-1. Power Management Unit Configuration................................................................................ 517
15-2. Sleep Modes .............................................................................................................. 519
15-3. Power Management Control Architecture in CC32xx................................................................ 521
15-4. CAMCLKCFG Register .................................................................................................. 531
15-5. CAMCLKEN Register .................................................................................................... 532
15-6. CAMSWRST Register.................................................................................................... 533
15-7. MCASPCLKEN Register................................................................................................. 534
15-8. MCASPSWRST Register................................................................................................ 535
15-9. SDIOMCLKCFG Register................................................................................................ 536
15-10. SDIOMCLKEN Register.................................................................................................. 537

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15-11. SDIOMSWRST Register................................................................................................. 538
15-12. APSPICLKCFG Register................................................................................................. 539
15-13. APSPICLKEN Register .................................................................................................. 540
15-14. APSPISWRST Register.................................................................................................. 541
15-15. DMACLKEN Register .................................................................................................... 542
15-16. DMASWRST Register.................................................................................................... 543
15-17. GPIO0CLKEN Register .................................................................................................. 544
15-18. GPIO0SWRST Register ................................................................................................. 545
15-19. GPIO1CLKEN Register .................................................................................................. 546
15-20. GPIO1SWRST Register ................................................................................................. 547
15-21. GPIO2CLKEN Register .................................................................................................. 548
15-22. GPIO2SWRST Register ................................................................................................. 549
15-23. GPIO3CLKEN Register .................................................................................................. 550
15-24. GPIO3SWRST Register ................................................................................................. 551
15-25. GPIO4CLKEN Register .................................................................................................. 552
15-26. GPIO4SWRST Register ................................................................................................. 553
15-27. WDTCLKEN Register .................................................................................................... 554
15-28. WDTSWRST Register.................................................................................................... 555
15-29. UART0CLKEN Register.................................................................................................. 556
15-30. UART0SWRST Register................................................................................................. 557
15-31. UART1CLKEN Register.................................................................................................. 558
15-32. UART1SWRST Register................................................................................................. 559
15-33. GPT0CLKCFG Register ................................................................................................. 560
15-34. GPT0SWRST Register................................................................................................... 561
15-35. GPT1CLKEN Register ................................................................................................... 562
15-36. GPT1SWRST Register................................................................................................... 563
15-37. GPT2CLKEN Register ................................................................................................... 564
15-38. GPT2SWRST Register................................................................................................... 565
15-39. GPT3CLKEN Register ................................................................................................... 566
15-40. GPT3SWRST Register................................................................................................... 567
15-41. MCASPCLKCFG0 Register ............................................................................................. 568
15-42. MCASPCLKCFG1 Register ............................................................................................. 569
15-43. I2CLCKEN Register ...................................................................................................... 570
15-44. I2CSWRST Register ..................................................................................................... 571
15-45. LPDSREQ Register....................................................................................................... 572
15-46. TURBOREQ Register .................................................................................................... 573
15-47. DSLPWAKECFG Register............................................................................................... 574
15-48. DSLPTIMRCFG Register ................................................................................................ 575
15-49. SLPWAKEEN Register................................................................................................... 576
15-50. SLPTMRCFG Register................................................................................................... 577
15-51. WAKENWP Register ..................................................................................................... 578
15-52. RCM_IS Register ......................................................................................................... 579
15-53. RCM_IEN Register ....................................................................................................... 580
16-1. Board Configuration to Use Pins 45 and 52........................................................................... 585
16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals..................................................... 586
16-3. I/O Pad Data and Control Path Architecture in CC32xx............................................................. 606
16-4. Wake on Pad for Hibernate Mode...................................................................................... 609
17-1. AES Block Diagram ...................................................................................................... 613
17-2. AES - ECB Feedback Mode............................................................................................. 616