Winbond W77E516 User manual

Preliminary W77E516
8-BIT MICROCONTROLLER
Publication Release Date: August 16, 2002
-1-Revision A1
Table of Contents-
1. GENERAL DESCRIPTION...........................................................................................................................3
2. FEATURES..................................................................................................................................................3
3. PIN CONFIGURATIONS..............................................................................................................................4
4. PIN DESCRIPTION......................................................................................................................................5
5. BLOCK DIAGRAM .......................................................................................................................................6
6. FUNCTIONAL DESCRIPTION.....................................................................................................................7
I/O Ports.....................................................................................................................................................7
Serial I/O....................................................................................................................................................7
Timers........................................................................................................................................................8
Interrupts....................................................................................................................................................8
Data Pointers.............................................................................................................................................8
Power Management...................................................................................................................................8
On-chip Data SRAM..................................................................................................................................8
7. MEMORY ORGANIZATION.........................................................................................................................8
Program Memory.......................................................................................................................................8
Data Memory .............................................................................................................................................9
Special Function Registers......................................................................................................................10
Special Function Registers......................................................................................................................11
Instruction................................................................................................................................................34
Instruction Timing ....................................................................................................................................41
Power Management.................................................................................................................................49
Reset Conditions .....................................................................................................................................51
Reset State..............................................................................................................................................52
Interrupts..................................................................................................................................................53
8. PROGRAMMABLE TIMERS/COUNTERS.................................................................................................56
Timer/Counters 0 & 1...............................................................................................................................56
Time-base Selection................................................................................................................................57
Timer/Counter 2.......................................................................................................................................59
Watchdog Timer......................................................................................................................................62
Serial Port................................................................................................................................................64
Framing Error Detection ..........................................................................................................................70
Multiprocessor Communications..............................................................................................................70

Preliminary W77E516
-2-
9. TIMED ACCESS PROTECTION................................................................................................................71
10. ABSOLUTE MAXIMUM RATINGS...........................................................................................................72
11. AC CHARACTERISTICS .........................................................................................................................74
External Clock Characteristics.................................................................................................................74
AC Specification......................................................................................................................................74
MOVX Characteristics Using Strech Memory Cycles..............................................................................75
12. TIMING WAVEFORMS............................................................................................................................76
Program Memory Read Cycle..................................................................................................................76
Data Memory Read Cycle........................................................................................................................77
Data Memory Write Cycle........................................................................................................................77
13. TYPICAL APPLICATION CIRCUITS........................................................................................................78
Expanded External Program Memory and Crystal...................................................................................78
Expanded External Data Memory and Oscillator.....................................................................................79
14. PACKAGE DIMENSIONS........................................................................................................................79
40-pin DIP................................................................................................................................................79
44-pin PLCC............................................................................................................................................80
44-pin QFP ..............................................................................................................................................80
15. APPLICATION NOTE...............................................................................................................................81
In-system Programming Software Examples...........................................................................................81

Preliminary W77E516
Publication Release Date: August 16, 2002
-3-Revision A1
1. GENERAL DESCRIPTION
The W77E516 is a fast 8051 compatible microcontroller with a redesigned processor core without
wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the original
8051 for the same crystal speed. Typically, the instruction executing time of W77E516 is 1.5 to 3 times
faster then that of traditional 8051, depending on the type of instruction. In general, the overall
performance is about 2.5 times better than the original for the same crystal speed. Giving the same
throughput with lower clock speed, power consumption has been improved. Consequently, the
W77E516 is a fully static CMOS design; it can also be operated at a lower crystal clock. The W77E516
contains In-System Programmable (ISP) 64 KB Flash EPROM; 4KB auxiliary Flash EPROM for loader
program; operating voltage from 4.5V to 5.5V; on-chip 1 KB MOVX SRAM; three power saving modes.
2. FEATURES
•8-bit CMOS microcontroller
•High speed architecture of 4 clocks/machine cycle runs up to 40 MHz
•Pin compatible with standard 80C52
•Instruction-set compatible with MCS-51
•64KB on-chip Mask-ROM
•Four 8-bit I/O Ports
•One extra 4-bit I/O port and Wait State control signal (available on 44-pin PLCC/QFP package)
•Three 16-bit Timers
•12 interrupt sources with two levels of priority
•On-chip oscillator and clock circuitry
•Two enhanced full duplex serial ports
•64KB In-System Programmable Flash EPROM (APROM)
•4KB Auxiliary Flash EPROM for loader program (LDROM)
•256 bytes scratch-pad RAM
•1KB on-chip SRAM for MOVX instruction
•Programmable Watchdog Timer
•Dual 16-bit Data Pointers
•Software programmable access cycle to external RAM/peripherals
•Packages:
−DIP 40: W77E516-25/40
−PLCC 44: W77E516P-25/40
−QFP 44: W77E516F-25/40

Preliminary W77E516
-4-
3. PIN CONFIGURATIONS
VDD1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
40
34
35
36
37
38
30
31
32
33
26
27
28
29
21
22
23
24
25
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.5, A13
P2.6, A14
P2.7, A15
P2.0, A8
P2.1, A9
P2.2, A10
P2.3, A11
P2.4, A12
T2, P1.0
40-Pin DIP (W77E516)
RXD1, P1.2
TXD1, P1.3
INT2, P1.4
INT3, P1.5
INT4, P1.6
RXD, P3.0
TXD, P3.1
INT5, P1.7
RST
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL1
XTAL2
VSS
T2EX, P1.1
44-Pin PLCC (W77E516P) 44-Pin QFP (W77E516F)
34
4039 38 37 36 3544 43 42 41 33
32
31
30
29
28
27
26
25
24
23
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
22212019181716151413
12
11
4
3
2
1
8
7
6
5
10
9
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
X
T
A
L
1
V
S
S
P
2
.
4
,
A
1
2
P
2
.
3
,
A
1
1
P
2
.
2
,
A
1
0
P
2
.
1
,
A
9
P
2
.
0
,
A
8
X
T
A
L
2
P
3
.
7
,
/
R
D
P
3
.
6
,
/
W
R
40
2 1 44 43 42 41 6543 39
38
37
36
35
34
33
32
31
30
29
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
2827262524232221201918
17
10
9
8
7
14
13
12
11
16
15
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
X
T
A
L
1
V
S
S
P
2
.
4
,
A
1
2
P
2
.
3
,
A
1
1
P
2
.
2
,
A
1
0
P
2
.
1
,
A
9
P
2
.
0
,
A
8
X
T
A
L
2
P
3
.
7
,
/
R
D
P
3
.
6
,
/
W
R
A
D
3
,
P
0
.
3
T
2
,
P
1
.
0
P
1
.
2
V
D
D
A
D
2
,
P
0
.
2
A
D
1
,
P
0
.
1
A
D
0
,
P
0
.
0
T
2
E
X
,
P
1
.
1
P
1
.
3
P
1
.
4
,
X
D
1
R
,
X
D
1
TA
D
3
,
P
0
.
3
T
2
,
P
1
.
0
P
1
.
2
V
D
D
A
D
2
,
P
0
.
2
A
D
1
,
P
0
.
1
A
D
0
,
P
0
.
0
T
2
E
X
,
P
1
.
1
P
1
.
3
P
1
.
4
,,
X
XD
D1
1
RT
,
N
T
2
I
,
N
T
2
I
P
4
.
2
P
4
.
2
P
4
.
0
,
/
W
A
I
T
P
4
.
0
,
/
W
A
I
T

Preliminary W77E516
Publication Release Date: August 16, 2002
-5-Revision A1
4. PIN DESCRIPTION
SYMBOL TYPE DESCRIPTIONS
EA
IEXTERNAL ACCESS ENABLE: It should be kept high for internal program
access..
PSEN
O
PROGRAM STORE ENABLE:
PSEN
enables the external ROM data onto
the Port 0 address/data bus during fetch and MOVC operations.
ALE O
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
RST I
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
XTAL1 ICRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2 OCRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS IGROUND: Ground potential
VDD IPOWER SUPPLY: Supply voltage for operation.
P0.0 −P0.7
I/O
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides
a multiplexed low order address/data bus during accesses to external memory.
P1.0 −P1.7
I/O
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
RXD1(P1.2): Serial port 1 RXD
TXD1(P1.3): Serial port 1 TXD
INT2(P1.4): External Interrupt 2
INT3 (P1.5): External Interrupt 3
INT4(P1.6): External Interrupt 4
INT5 (P1.7): External Interrupt 5
P2.0 −P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
P3.0 −P3.7
I/O
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have
alternate functions, which are described below:
RXD(P3.0): Serial Port 0 input
TXD(P3.1): Serial Port 0 output
INT0 (P3.2): External Interrupt 0
INT1
(P3.3): External Interrupt 1
T0(P3.4): Timer 0 External Input
T1(P3.5): Timer 1 External Input
WR
(P3.6): External Data Memory Write Strobe
RD
(P3.7): External Data Memory Read Strobe
P4.0 −P4.3
I/O PORT 4: Port 4 is a 4-bit bi-directional I/O port. The P4.0 also provides the
alternate function
WAIT
which is the wait state control signal.
* Note: TYPE I: input, O: output, I/O: bi-directional.

Preliminary W77E516
-6-
5. BLOCK DIAGRAM
Address
Bus
P3.0
∫
P3.7
P1.0
∫
P1.7
ALU
Port 0
Latch
Port 1
Latch
Timer
1
Timer
0
Port
0
Port
1
2 UARTs
XTAL1
PSEN
ALE GND VCC RST XTAL2
Oscillator
Interrupt
PSW
Instruction
Decoder
&
Sequencer
Reset Block
Bus & lock
Controller
SFR RAM Address
Power control
&
Power monitor
256 bytes
RAM & SFR
Stack
Pointer
B
Addr. Reg.
Incrementor
PC
Temp Reg.
DPTR 1
T2 Register T1 Register
ACC
Port 3
Latch
Port
3
P0.0
∫
Port 2
Latch
Port
2
P2.0
∫
Timer
2
1KB SRAM
DPTR
Watchdog Timer
Port 4
Latch
Port
4
P4.0
∫
P4.3
64KB ROM

Preliminary W77E516
Publication Release Date: August 16, 2002
-7-Revision A1
6. FUNCTIONAL DESCRIPTION
The W77E516 is 8052 pin compatible and instruction set compatible. It includes the resources of the
standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, and full duplex serial port and
interrupt sources.
The W77E516 features a faster running and better performance 8-bit CPU with a redesigned core
processor without wasted clock and memory cycles. It improves the performance not just by running at
high frequency but also by reducing the machine cycle duration from the standard 8052 period of
twelve clocks to four clock cycles for the majority of instructions. This improves performance by an
average of 1.5 to 3 times. The W77E516 also provides dual Data Pointers (DPTRs) to speed up block
data memory transfers. It can also adjust the duration of the MOVX instruction (access to off-chip data
memory) between two machine cycles and nine machine cycles. This flexibility allows the W77E516 to
work efficiently with both fast and slow RAMs and peripheral devices. In addition, the W77E516
contains on-chip 1KB MOVX SRAM, the address of which is between 0000H and 03FFH. It only can
be accessed by MOVX instruction; this on-chip SRAM is optional under software control.
The W77E516 is an 8052 compatible device that gives the user the features of the original 8052
device, but with improved speed and power consumption characteristics. It has the same instruction
set as the 8051 family, with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1).
While the original 8051 family was designed to operate at 12 clock periods per machine cycle, the
W77E516 operates at a much reduced clock rate of only 4 clock periods per machine cycle. This
naturally speeds up the execution of instructions. Consequently, the W77E516 can run at a higher
speed as compared to the original 8052, even if the same crystal is used. Since the W77E516 is a fully
static CMOS design, it can also be operated at a lower crystal clock, giving the same throughput in
terms of instruction execution, yet reducing the power consumption.
The 4 clocks per machine cycle feature in the W77E516 is responsible for a three-fold increase in
execution speed. The W77E516 has all the standard features of the 8052, and has a few extra
peripherals and features as well.
I/O Ports
The W77E516 has four 8-bit ports and one extra 4-bit port. Port 0 can be used as an Address/Data
bus when external program is running or external memory/device is accessed by MOVC or MOVX
instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull-
ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is used chiefly as the
upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also has strong pull-ups
and pull-downs when it serves as an address bus. Port 1 and 3 act as I/O ports with alternate
functions. Port 4 is only available on 44-pin PLCC/QFP package type. It serves as a general purpose
I/O port as Port 1 and Port 3. The P4.0 has an alternate function
WAIT
that is the wait state control
signal. When wait state control signal is enabled, P4.0 is input only.
Serial I/O
The W77E516 has two enhanced serial ports that are functionally similar to the serial port of the
original 8052 family. However the serial ports on the W77E516 can operate in different modes in order
to obtain timing similarity as well. Note that the serial port 0 can use Timer 1 or 2 as baud rate
generator, but the serial port 1 can only use Timer 1 as baud rate generator. The serial ports
have the enhanced features of Automatic Address recognition and Frame Error detection.

Preliminary W77E516
-8-
Timers
The W77E516 has three 16-bit timers that are functionally similar to the timers of the 8052 family.
When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing
the user with the option of operating in a mode that emulates the timing of the original 8052. The
W77E516 has an additional feature, the watchdog timer. This timer is used as a System Monitor or as
a very long time period timer.
Interrupts
The Interrupt structure in the W77E516 is slightly different from that of the standard 8052. Due to the
presence of additional features and peripherals, the number of interrupt sources and vectors has been
increased. The W77E516 provides 12 interrupt resources with two-priority level, including six external
interrupt sources, timer interrupts, serial I/O interrupts and power-fail interrupt.
Data Pointers
The original 8052 had only one 16-bit Data Pointer (DPL, DPH). In the W77E516, there is an additional
16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations that were unused in
the original 8052. In addition there is an added instruction, DEC DPTR (op-code A5H), which helps in
improving programming flexibility for the user.
Power Management
Like the standard 80C52, the W77E516 also has IDLE and POWER DOWN modes of operation. The
W77E516 provides a new Economy mode that allow user to switch the internal clock rate divided by 4,
64 or 1024. In the IDLE mode, the clock to the CPU core is stopped while the timers; serial ports and
interrupts clock continue to operate. In the POWER DOWN mode, the entire clock is stopped and the
chip operation is completely stopped. This is the lowest power consumption state.
On-chip Data SRAM
The W77E516 has 1K Bytes of data space SRAM which is read/write accessible and is memory
mapped. This on-chip MOVX SRAM is reached by the MOVX instruction. It is not used for executable
program memory. There is no conflict or overlap among the 256 bytes Scratchpad RAM and the 1K
Bytes MOVX SRAM as they use different addressing modes and separate instructions. Setting the
DME0 bit in the PMR register enables the on-chip MOVX SRAM. After a reset, the DME0 bit is cleared
such that the on-chip MOVX SRAM is disabled, and all data memory spaces 0000H −FFFFH access
to the external memory.
7. MEMORY ORGANIZATION
The W77E516 separates the memory into two separate sections, the Program Memory and the Data
Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is
used to store data or for memory mapped devices.
Program Memory
The Program Memory on the W77E516 can be up to 64Kbytes long. All instructions are fetched for
execution from this memory area. The MOVC instruction can also access this memory region.

Preliminary W77E516
Publication Release Date: August 16, 2002
-9-Revision A1
Data Memory
The W77E516 can access up to 64Kbytes of external Data Memory. This memory region is accessed
by the MOVX instructions. Unlike the 8051 derivatives, the W77E516 contains on-chip 1K bytes MOVX
SRAM of Data Memory, which can only be accessed by MOVX instructions.
These 1K bytes of SRAM are between address 0000H and 03FFH. Access to the on-chip MOVX
SRAM is optional under software control. When enabled by software, any MOVX instruction that uses
this area will go to the on-chip RAM. MOVX addresses greater than 03FFH automatically go to external
memory through Port 0 and 2. When disabled, the 1KB memory area is transparent to the system
memory map. Any MOVX directed to the space between 0000H and FFFFH goes to the expanded bus
on Port 0 and 2. This is the default condition. In addition, the W77E516 has the standard 256 bytes of
on-chip Scratchpad RAM. This can be accessed either by direct addressing or by indirect addressing.
There are also some Special Function Registers (SFRs), which can only be accessed by direct
addressing. Since the Scratchpad RAM is only 256 bytes, it can be used only when data contents are
small. In the event that larger data contents are present, two selections can be used. One is on-chip
MOVX SRAM, the other is the external Data Memory. The on-chip MOVX SRAM can only be accessed
by a MOVX instruction, the same as that for external Data Memory. However, the on-chip RAM has the
fastest access times.
0000h
FFFFh
80h
7Fh
00h
Indirect
Addressing
RAM
Direct &
Indirect
Addressing
RAM
SFRs
Direct
Addressing
FFh
64 K
Bytes
External
Data
Memory
1K Bytes
On-chip SRAM
0000h
03FFh
64K Bytes
On-chip
Program
Memory
APROM
0FFFh
4K Bytes
LDROM
Figure 1. Memory Map

Preliminary W77E516
-10 -
FFh
80h
7Fh
30h
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
26h
25h
24h
23h
22h
21h
20h
1Fh
18h
17h
10h
0Fh
08h
07h
00h
78
79
7A
7B
7C
7D
7E
7F
70
71
72
73
74
75
76
77
68
69
6A
6B
6C
6D
6E
6F
60
61
62
63
64
65
66
67
58
59
5A
5B
5C
50
51
52
53
54
5D
5E
5F
55
56
57
48
49
4A
4B
4C
4D
4E
4F
40
41
42
43
44
45
46
47
38
39
3A
3B
3C
3D
3E
3F
30
31
32
33
34
35
36
37
28
29
2A
2B
2C
2D
2E
2F
20
21
22
23
24
25
26
27
18
19
1A
1B
1C
1D
1E
1F
10
11
12
13
14
15
16
17
08
09
0A
0B
0C
0D
0E
0F
00
01
02
03
04
05
06
07
Indirect RAM
Direct RAM
Bank 3
Bank 2
Bank 1
Bank 0
Figure 2. Scratchpad RAM / Register Addressing
Bit Addressable
20H −2FH

Preliminary W77E516
Publication Release Date: August 16, 2002
-11 -Revision A1
Special Function Registers
The W77E516 uses Special Function Registers (SFRs) to control and monitor peripherals and their
Modes.
The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of
the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit
without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or
8. The W77E516 contains all the SFRs present in the standard 8052. However, some additional SFRs
have been added. In some cases unused bits in the original 8052 have been given new functions. The
list of SFRs is as follows. The table is condensed with eight locations per row. Empty locations indicate
that there are no registers at these addresses. When a bit or register is not implemented, it will read
high.
Table 1. Special Function Register Location Table
F8 EIP
F0 B
E8 EIE
E0 ACC
D8 WDCON
D0 PSW
C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 NVMCON NVMDAT
C0 SCON1 SBUF1 WSCON PMR STATUS NVMSEL TA
B8 IP SADEN SADEN1
B0 P3
A8 IE SADDR SADDR1 SFRAL SFRAH SFDFD SFRCN
A0 P2 P4CSIN P4
98 SCON0 SBUF P42AL P42AH P43AL P43AH CHPCON
90 P1 EXIF P4CONA P4CONB P40AL P40AH P41AL P41AH
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON
80 P0 SP DPL DPH DPL1 DPH1 DPS PCON
Note: The SFRs in the column with dark borders are bit-addressable.

Preliminary W77E516
-12 -
A brief description of the SFRs now follows.
Port 0
Bit: 76543210
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
Mnemonic: P0 Address: 80h
Port 0 is an open-drain bi-directional I/O port. This port also provides a multiplexed low order
address/data bus during accesses to external memory.
Stack Pointer
Bit: 76543210
SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
Mnemonic: SP Address: 81h
The Stack Pointer stores the Scratchpad RAM address where the stack begins. In other words, it
always points to the top of the stack.
Data Pointer Low
Bit: 76543210
DPL.7
DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
Mnemonic: DPL Address: 82h
This is the low byte of the standard 8052 16-bit data pointer.
Data Pointer High
Bit: 76543210
DPH.7
DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
Mnemonic: DPH Address: 83h
This is the high byte of the standard 8052 16-bit data pointer.
Data Pointer Low1
Bit: 76543210
DPL1.7
DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
Mnemonic: DPL1 Address: 84h
This is the low byte of the new additional 16-bit data pointer that has been added to the W77E516.
The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The
instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are
not required they can be used as conventional register locations by the user.

Preliminary W77E516
Publication Release Date: August 16, 2002
-13 -Revision A1
Data Pointer High1
Bit: 76543210
DPH1.7
DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
Mnemonic: DPH1 Address: 85h
This is the high byte of the new additional 16-bit data pointer that has been added to the W77E516.
The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The
instructions that use DPTR will now access DPL1 and DPH1 in place of DPL and DPH. If they are
not required they can be used as conventional register locations by the user.
Data Pointer Select
Bit: 76543210
-------DPS.0
Mnemonic: DPS Address: 86h
DPS.0: This bit is used to select either the DPL, DPH pair or the DPL1, DPH1 pair as the
activeData Pointer. When set to 1, DPL1, DPH1 will be selected, otherwise DPL, DPH will
be selected.
DPS.1 −7: These bits are reserved, but will read 0.
Power Control
Bit: 76543210
SM0D
SMOD0
--GF1 GF0 PD IDL
Mnemonic: PCON Address: 87h
SMOD : This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.
SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7(SCON1.7)
indicates a Frame Error and acts as the FE(FE_1) flag. When SMOD0 is 0, then
SCON.7(SCON1.7) acts as per the standard 8052 function.
GF1-0: These two bits are general purpose user flags.
PD: Setting this bit causes the W77E516 to go into the POWER DOWN mode. In this mode all the
clocks are stopped and program execution is frozen.
IDL: Setting this bit causes the W77E516 to go into the IDLE mode. In this mode the clocks to the
CPU are stopped, so program execution is frozen. But the clock to the serial, timer and
interrupt blocks is not stopped, and these blocks continue operating.
Timer Control
Bit: 76543210
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Mnemonic: TCON Address: 88h

Preliminary W77E516
-14 -
TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
TR1: Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
TF0: Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
TR0: Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
IE1: Interrupt 1 edge detect: Set by hardware when an edge/level is detected on
INT1
. This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
IT1: Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
IE0: Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0. This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
IT0: Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
Timer Mode Control
Bit: 76543210
GATE
CT/
M1 M0 GATE
CT/
M1 M0
TIMER1 TIMER0
Mnemonic: TMOD Address: 89h
GATE: Gating control: When this bit is set, Timer/counter x is enabled only while
INTx
pin is
high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit
is set.
CT/: Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When
set, the timer counts high-to-low edges of the Tx pin.

Preliminary W77E516
Publication Release Date: August 16, 2002
-15 -Revision A1
M1, M0: Mode Select bits:
M1 M0 Mode
00Mode 0: 8-bits with 5-bit prescale.
01Mode 1: 18-bits, no prescale.
10Mode 2: 8-bits with auto-reload from THx
11Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0
control bits. TH0 is a 8-bit timer only controlled by Timer 1 control bits. (Timer 1)
Timer/counter is stopped.
Timer 0 LSB
Bit: 76543210
TL0.7
TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0
Mnemonic: TL0 Address: 8Ah
TL0.7 −0: Timer 0 LSB
Timer 1 LSB
Bit: 76543210
TL1.7
TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0
Mnemonic: TL1 Address: 8Bh
TL1.7 −0: Timer 1 LSB
Timer 0 MSB
Bit: 76543210
TH0.7
TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0
Mnemonic: TH0 Address: 8Ch
TH0.7 −0: Timer 0 MSB
Timer 1 MSB
Bit: 76543210
TH1.7
TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0
Mnemonic: TH1 Address: 8Dh
TH1.7 −0: Timer 1 MSB

Preliminary W77E516
-16 -
Clock Control
Bit: 76543210
WD1 WD0 T2M T1M T0M MD2 MD1 MD0
Mnemonic: CKCON Address: 8Eh
WD1 −0: Watchdog timer mode select bits: These bits determine the time-out period for the
watchdog timer. In all four time-out options the reset time-out is 512 clocks more than
the interrupt time-out period.
WD1 WD0 Interrupt time-out Reset time-out
00217 217 + 512
01220 220 + 512
10223 223 + 512
11226 226 + 512
T2M: Timer 2 clock select: When T2M is set to 1, timer 2 uses a divide by 4 clock, and when set to
0 it uses a divide by 12 clock.
T1M: Timer 1 clock select: When T1M is set to 1, timer 1 uses a divide by 4 clock, and when set to
0 it uses a divide by 12 clock.
T0M: Timer 0 clock select: When T0M is set to 1, timer 0 uses a divide by 4 clock, and when set to
0 it uses a divide by 12 clock.
MD2 −0: Stretch MOVX select bits: These three bits are used to select the stretch value for the
MOVXinstruction. Using a variable MOVX length enables the user to access slower
external memorydevices or peripherals without the need for external circuits. The
RD
or
WR
strobe will be stretched by the selected interval. When accessing the on-chip
SRAM, the MOVX instruction is always in 2 machine cycles regardless of the stretch
setting. By default, the stretch has value of 1. If the user needs faster accessing, then a
stretch value of 0 should be selected.
MD2 MD1 MD0 Stretch value MOVX duration
0 0 0 02 machine cycles
0 0 1 13 machine cycles (Default)
0 1 0 24 machine cycles
0 1 1 35 machine cycles
1 0 0 46 machine cycles
1 0 1 57 machine cycles
1 1 0 68 machine cycles
1 1 1 79 machine cycles

Preliminary W77E516
Publication Release Date: August 16, 2002
-17 -Revision A1
Port 1
Bit: 76543210
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
Mnemonic: P1 Address: 90h
P1.7 −0: General purpose I/O port. Most instructions will read the port pins in case of a port read
access, however in case of read-modify-write instructions, the port latch is read. Some
pins also have alternate input or output functions. This alternate functions are described
below:
P1.0: T2 External I/O for Timer/Counter 2
P1.1: T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2: RXD1 Serial Port 1 Receive
P1.3: TXD1 Serial Port 1 Transmit
P1.4: INT2 External Interrupt 2
P1.5: INT3External Interrupt 3
P1.6: INT4 External Interrupt 4
P1.7: INT5External Interrupt 5
External Interrupt Flag
Bit: 76543210
IE5 IE4 IE3 IE2 ----
Mnemonic: EXIF Address: 91h
IE5: External Interrupt 5 flag. Set by hardware when a falling edge is detected on INT5.
IE4: External Interrupt 4 flag. Set by hardware when a rising edge is detected on INT4.
IE3: External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3.
IE2: External Interrupt 2 flag. Set by hardware when a rising edge is detected on INT2.
Port 4 Control Register A
Bit: 76543210
P41M1
P41M0 P41C1 P41C0 P40M1 P40M0 P40C1 P40C0
Mnemonic: P4CONA Address: 92h
Port 4 Control Register B
Bit: 76543210
P43M1
P43M0 P43C1 P43C0 P42M1 P42M0 P42C1 P42C0
Mnemonic: P4CONB Address: 93h

Preliminary W77E516
-18 -
BIT NAME FUNCTION
P4xM1, P4xM0 Port 4 alternate modes.
= 00: Mode 0. P4.x is a general purpose I/O port which is the same as Port 1.
= 01: Mode 1. P4.x is a Read Strobe signal for chip select purpose. The
address range depends on the SFR P4xAH, P4xAL and bits P4xC1, P4xC0.
= 10: Mode 2. P4.x is a Write Strobe signal for chip select purpose. The
address range depends on the SFR P4xAH, P4xAL and bits P4xC1, P4xC0.
= 11: Mode 3. P4.x is a Read/Write Strobe signal for chip select purpose.
The address range depends on the SFR P4xAH, P4xAL and bits P4xC1,
P4xC0
P4xC1, P4xC0 Port 4 Chip-select Mode address comparison:
= 00: Compare the full address (16 bits length) with the base address registers
P4xAH and P4xAL.
= 01: Compare the 15 high bits (A15 −A1) of address bus with the
base
address registers P4xAH and P4xAL.
= 10: Compare the 14 high bits (A15 −
A2) of address bus with the base
address registers P4xAH and P4xAL.
= 11: Compare the 8 high bits (A15 −A8) of address bus with the base
address registers P4xAH and P4xAL.
P4.0 Base Address Low Byte Register
Bit: 76543210
A7 A6 A5 A4 A3 A2 A1 A0
Mnemonic: P40AL Address: 94h
P4.0 Base Address High Byte Register
Bit: 76543210
A15 A14 A13 A12 A11 A10 A9 A8
Mnemonic: P40AH Address: 95h
P4.1 Base Address Low Byte Register
Bit: 76543210
A7 A6 A5 A4 A3 A2 A1 A0
Mnemonic: P41AL Address: 96h

Preliminary W77E516
Publication Release Date: August 16, 2002
-19 -Revision A1
P4.1 Base Address High Byte Register
Bit: 76543210
A15 A14 A13 A12 A11 A10 A9 A8
Mnemonic: P41AH Address: 97h
Serial Port Control
Bit: 76543210
SM0/FE
SM1 SM2 REN TB8 RB8 TI RI
Mnemonic: SCON Address: 98h
SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines
whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When
used as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually
cleared in software to clear the FE condition.
SM1: Serial port Mode bit 1:
SM0 SM1 Mode Description Length Baud rate
000Synchronous 84/12 Tclk
011Asynchronous 10 Variable
102Asynchronous 11 64/32 Tclk
113Asynchronous 11 Variable
SM2: Multiple processors communication. Setting this bit to 1 enables the multiprocessor
communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be
activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be
activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port
clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives
compatibility with the standard 8052. When set to 1, the serial clock become divide by 4 of the
oscillator clock. This results in faster synchronous serial communication.
REN: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.
TB8: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software
as desired.
RB8: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit
that was received. In mode 0 it has no function.
TI: Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
RI: Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2 apply to this bit. This bit can be cleared only by software.

Preliminary W77E516
-20 -
Serial Data Buffer
Bit: 76543210
SBUF.7
SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
Mnemonic: SBUF Address: 99h
SBUF.7 −0: Serial data on the serial port 0 is read from or written to this location. It actually
consists of two separate internal 8-bit registers. One is the receive resister, and the
other is the transmit buffer. Any read access gets data from the receive data buffer,
while write access is to the transmit data buffer.
P4.2 Base Address Low Byte Register
Bit: 76543210
A7 A6 A5 A4 A3 A2 A1 A0
Mnemonic: P42AL Address: 9Ah
P4.2 Base Address High Byte Register
Bit: 76543210
A15 A14 A13 A12 A11 A10 A9 A8
Mnemonic: P42AH Address: 9Bh
P4.3 Base Address Low Byte Register
Bit: 76543210
A7 A6 A5 A4 A3 A2 A1 A0
Mnemonic: P43AL Address: 9Ch
P4.3 Base Address High Byte Register
Bit: 76543210
A15 A14 A13 A12 A11 A10 A9 A8
Mnemonic: P43AH Address: 9Dh
ISP Control Register
Bit: 76543210
SWRST/HWB
-LDAP ---LDSEL ENP
Mnemonic: CHPCON Address: 9Fh
SWRST/HWB: Set this bit to launch a whole device reset that is same as asserting high to RST pin,
micro controller will be back to initial state and clear this bit automatically. To read
this bit, its alternate function to indicate the ISP hardware reboot mode is invoking
when read it in high.