Cypress Semiconductor CY62157ESL User manual

CY62157ESL MoBL®
8-Mbit (512K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-43141 Rev. ** Revised January 04, 2008
Features
■Very high speed: 45 ns
■Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■Ultra low standby power
❐Typical Standby current: 2 μA
❐Maximum Standby current: 8 μA
■Ultra low active power
❐Typical active current: 1.8 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■CMOS for optimum speed and power
■Available in Pb-free 44-pin TSOP II package
Functional Description
The CY62157ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE HIGH or both BHE and
BLE are HIGH). The input or output pins (IO0through IO15) are
placed in a high impedance state when:
■Deselected (CE HIGH)
■Outputs are disabled (OE HIGH)
■Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0through IO7) is written into the location
specified on the address pins (A0through A18). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8through IO15)
is written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8to IO15. See the Truth Table on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
512K x 16
RAM Array IO0–IO7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11 A12 A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3IO8–IO15
WE
BLE
BHE
A16
A0
A1
A17
A9
A10
A18
CE
PowerDown
Circuit BHE
BLE
CE
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 2 of 12
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View)
Product Portfolio
Product Range VCC Range (V) [1] Speed
(ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(μA)
f = 1MHz f = fmax
Typ [2] Max Typ [2] Max Typ [2] Max
CY62157ESL Industrial 2.2V–3.6V and 4.5V–5.5V 45 1.8 3 18 25 2 8
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29 30
A5
18
17
20
19 27
28
25
26
22
21 23
24
A6
A7
A3
A2
A1
A0
A17
A4
A9
A10
A11
A12
A15
A16
OE
BHE
BLE
CE
WE
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
VCC VCC
VSS
VSS
10
A18
A14
A8
A13
Notes
1. Datasheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3V, and VCC = 5V, TA= 25°C.
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 3 of 12
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential..................–0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State[3, 4] ...........................................–0.5V to 6.0V
DC Input Voltage[3, 4]........................................–0.5V to 6.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch up Current......................................................>200 mA
Operating Range
Device Range Ambient
Temperature VCC[5]
CY62157ESL Industrial –40°C to +85°C 2.2V–3.6V,
and
4.5V–5.5V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns UnitMin Typ [2] Max
VOH Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 V
2.7 < VCC < 3.6 IOH = –1.0 mA 2.4
4.5 < VCC < 5.5 IOH = –1.0 mA 2.4
VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V
2.7 < VCC < 3.6 IOL = 2.1mA 0.4
4.5 < VCC < 5.5 IOL = 2.1mA 0.4
VIH Input HIGH Voltage 2.2 < VCC < 2.7 1.8 VCC + 0.3 V
2.7 < VCC < 3.6 2.2 VCC + 0.3
4.5 < VCC < 5.5 2.2 VCC + 0.5
VIL Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 V
2.7 < VCC < 3.6 –0.3 0.8
4.5 < VCC < 5.5 –0.5 0.8
IIX Input Leakage Current GND <VI< VCC –1 +1 μA
IOZ OutputLeakage Current GND <VO <VCC,Output Disabled –1 +1 μA
ICC VCC Operating Supply
Current f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA,
CMOS levels
18 25 mA
f = 1 MHz 1.8 3
ISB1 Automatic CE Power
down Current — CMOS
Inputs
CE > VCC − 0.2V, VIN >VCC – 0.2V or VIN <0.2V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE), VCC = VCC(max)
28μA
ISB2 Automatic CE Power
down Current — CMOS
Inputs
CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
28μA
Notes
3. VIL(min) = –2.0V for pulse durations less than 20 ns.
4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization.
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 4 of 12
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output Capacitance 10 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 77 °C/W
ΘJC Thermal Resistance
(Junction to Case) 13 °C/W
AC Test Loads and Waveforms
Parameters 2.5V 3.0V 5.0V Unit
R1 16667 1103 1800 Ω
R2 15385 1554 990 Ω
RTH 8000 645 639 Ω
VTH 1.20 1.75 1.77 V
VCCVCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
TH
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 5 of 12
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ[2] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V VCC = 1.5V 2 5 μA
VCC = 2.0V 2 8
tCDR [6] Chip Deselect to Data
Retention Time 0ns
tR [7] Operation Recovery Time tRC ns
Data Retention Waveform
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) >100 μs.
8. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE or
BHE.BLE[8]
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 6 of 12
Switching Characteristics
Over the Operating Range [9]
Parameter Description 45 ns Unit
Min Max
Read Cycle
tRC Read Cycle Time 45 ns
tAA Address to Data Valid 45 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 45 ns
tDOE OE LOW to Data Valid 22 ns
tLZOE OE LOW to LOW-Z[10] 5ns
tHZOE OE HIGH to High-Z[10, 11] 18 ns
tLZCE CE LOW to Low-Z[10] 10 ns
tHZCE CE HIGH to High-Z[10, 11] 18 ns
tPU CE LOW to Power Up 0 ns
tPD CE HIGH to Power Down 45 ns
tDBE BLE/BHE LOW to Data Valid 45 ns
tLZBE BLE/BHE LOW to Low-Z[10, 12] 5ns
tHZBE BLE/BHE HIGH to HIGH-Z[10, 11] 18 ns
Write Cycle[13]
tWC Write Cycle Time 45 ns
tSCE CE LOW to Write End 35 ns
tAW Address Setup to Write End 35 ns
tHA Address Hold from Write End 0 ns
tSA Address Setup to Write Start 0 ns
tPWE WE Pulse Width 35 ns
tBW BLE/BHE LOW to Write End 35 ns
tSD Data Setup to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z[10, 11] 18 ns
tLZWE WE HIGH to Low-Z[10] 10 ns
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.
10.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12.If both byte enables are toggled together, this value is 10 ns.
13.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 7 of 12
Switching Waveforms
Figure 2. Read Cycle No.1: Address Transition Controlled. [14, 15]
Figure 3. Read Cycle No. 2: OE Controlled [15, 16]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGHIMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
14.The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
15.WE is HIGH for read cycle.
16.Address valid before or similar to CE, BHE, BLE transition LOW.
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 8 of 12
Figure 4. Write Cycle No 1: WE Controlled [13, 17, 18]
Figure 5. Write Cycle 2: CE Controlled [13, 17, 18]
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tWC
tHZOE
DATAIN
NOTE 19
tBW
tSCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 19
Notes
17.Data IO is high impedance if OE = VIH.
18.If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
19.During this period, the IOs are in output state. Do not apply input signals.
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 9 of 12
Figure 6. Write Cycle 3: WE controlled, OE LOW [18]
Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW [18]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
tBW
NOTE 19
CE
ADDRESS
WE
DATA IO
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 19
DATA IO
ADDRESS
CE
WE
BHE /BLE
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CY62157ESL MoBL®
Document #: 001-43141 Rev. ** Page 10 of 12
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High-Z Deselect/Power down Standby (ISB)
X X X H H High-Z Deselect/Power down Standby (ISB)
L H L L L Data Out (IO0–IO15)Read Active(I
CC)
LHLHLDataOut(IO
0–IO7);
IO8–IO15 in High-Z Read Active (ICC)
L H L L H Data Out (IO8–IO15);
IO0–IO7 in High-Z Read Active (ICC)
L H H L L High-Z Output Disabled Active (ICC)
L H H H L High-Z Output Disabled Active (ICC)
L H H L H High-Z Output Disabled Active (ICC)
L L X L L Data In (IO0–IO15) Write Active (ICC)
L L X H L Data In (IO0–IO7);
IO8–IO15 in High-Z Write Active (ICC)
L L X L H Data In (IO8–IO15);
IO0–IO7 in High-Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
45 CY62157ESL-45ZSXI 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Industrial
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