Cypress Semiconductor CY7C1041DV33 User manual

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05473 Rev. *E Revised July 17, 2008
CY7C1041DV33
4 Mbit (256K x 16) Static RAM
Features
■Pin and function compatible with CY7C1041CV33
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 90 mA at 10 ns (industrial)
■Low CMOS standby power
❐ISB2 = 10 mA
■2.0V data retention
■Automatic power down when deselected
■TTL compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II packages
Functional Description
TheCY7C1041DV33[1] is ahighperformance CMOS StaticRAM
organized as 256K words by 16 bits. To write to the device, take
Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte
LOW Enable (BLE) is LOW, then data from IO pins (IO0 to IO7)
is written into the location specified on the address pins (A0to
A17). If Byte HIGH Enable (BHE) is LOW, then data from IO pins
(IO8to IO15) is written into the location specified on the address
pins (A0to A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
BLE is LOW, then data from the memory location specified by
theaddress pins appears on IO0to IO7. If BHE is LOW, then data
from memory appears on IO8to IO15. See the Truth Table on
page 9 for a complete description of read and write modes.
The input and output pins (IO0to IO15) are placed in a high
impedance state when the device is deselected (CE HIGH),
outputs are disabled (OE HIGH), BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid
array (FBGA) package.
14 15
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K × 16
A0
A11
A13 A12
A A A16
A17
A9
A10
IO0–IO7
OE
IO8–IO15
CE
WE
BLE
BHE
Logic Block Diagram
Note
1. For guidelines on SRAM system design, refer to the “System Design Guidelines” Cypress application note, available at www.cypress.com.
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 2 of 13
Selection Guide
Description –10 (Industrial) –12 (Automotive)[2] Unit
Maximum Access Time 10 12 ns
Maximum Operating Current 90 95 mA
Maximum CMOS Standby Current 10 15 mA
Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II
Figure 2. 48-Ball VFBGA (Pinout 1) [3, 4] Figure 3. 48-Ball VFBGA (Pinout 2) [3, 4]
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29 30
A
17
18
17
20
19 27
28
25
26
22
21 23
24
A
16
A
15
A
0
A
1
A
2
A
3
A
4
A
7
A
6
A
14
A
13
A
12
A
11
A
9
A
8
A
10
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
5
WE
VCC
A11
A10
NC
A6
A0
A3CE
IO
2
IO 0
IO1
A4
A5
IO3
IO5
IO4
IO6
IO7
VSS
A9
A8
OE
VSS
A7
IO8
BHE
NC
A17
A2
A1
BLE
VCC
IO9
IO10
IO11
IO12
IO13 IO14
IO15
A15 A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
WE
VCC
A11
A10
NC
A6
A0
A3CE
IO
10
IO 8
IO9
A4
A5
IO
11
IO13
IO12
IO14
IO15
VSS
A9
A8
OE
VSS
A7
IO0
BHE
NC
A17
A2
A1
BLE
VCC
IO2
IO 1
IO3
IO4
IO5IO6
IO7
A15 A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
Notes
2. Automotive product information is Preliminary.
3. NC pins are not connected on the die.
4. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte IOs (IO[7:0] and IO[15:8]
balls) are swapped.
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 3 of 13
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VCC Relative to GND [5]....–0.3V to +4.6V
DC Voltage Applied to Outputs
in High-Z State [5]....................................–0.3V to VCC +0.3V
DC Input Voltage [5] ................................–0.3V to VCC +0.3V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40°C to +85°C3.3V±0.3V 10 ns
Automotive –40°C to +125°C3.3V ±0.3V 12 ns
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions –10 (Industrial) –12 (Automotive) Unit
Min Max Min Max
VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 0.4 V
VIH[5] Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIL[5] Input LOW Voltage –0.3 0.8 –0.3 0.8 V
IIX Input Leakage Current GND < VI< VCC –1 +1 –1 +1 μA
IOZ Output Leakage
Current GND < VOUT <VCC, Output Disabled –1 +1 –1 +1 μA
ICC VCC Operating
Supply Current VCC = Max, f = fMAX = 1/tRC 100 MHz 90 -mA
83 MHz 80 95 mA
66 MHz 70 85 mA
40 MHz 60 75 mA
ISB1 Automatic CE Power Down
Current—TTL Inputs Max VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
20 25 mA
ISB2 Automatic CE Power Down
Current—CMOS Inputs Max VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10 15 mA
Note
5. Minimum voltage is –2.0V andVIH(max) = VCC + 2V for pulse durations of less than 20 ns.
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 4 of 13
Capacitance[6]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = 3.3V 8 pF
COUT IO Capacitance 8 pF
Thermal Resistance[6]
Parameter Description Test Conditions FBGA
Package SOJ Package TSOP II Package Unit
ΘJA Thermal Resistance (Junction
to Ambient) Still Air, soldered on a 3 × 4.5 inch, four layer printed circuit board 27.89 57.91 50.66 °C/W
ΘJC Thermal Resistance (Junction
to Case) 14.74 36.73 17.17 °C/W
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows.[7]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT Z = 50Ω
50Ω
1.5V
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317Ω
R2
351Ω
High-Z Characteristics
10 ns device
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. AC characteristics (except High-Z) are tested using the load conditions shown in AC Test Loads and Waveforms (a). High-Z characteristics are tested for all speeds
using the test load shown in (c).
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 5 of 13
AC Switching Characteristics Over the Operating Range[8]
Parameter Description –10 (Industrial) –12 (Automotive) Unit
Min Max Min Max
Read Cycle
tpower[9] VCC(Typical) to the First Access 100 100 μs
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 3 3ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Valid 5 6ns
tLZOE OE LOW to Low-Z 0 0ns
tHZOE OE HIGH to High-Z[10, 11] 56ns
tLZCE CE LOW to Low-Z[11] 3 3 ns
tHZCE CE HIGH to High-Z[10, 11] 56ns
tPU CE LOW to Power Up 0 0ns
tPD CE HIGH to Power Down 10 12 ns
tDBE Byte Enable to Data Valid 5 6ns
tLZBE Byte Enable to Low-Z 0 0ns
tHZBE Byte Disable to High-Z 6 6ns
Write Cycle[12, 13]
tWC Write Cycle Time 10 12 ns
tSCE CE LOW to Write End 7 8ns
tAW Address Setup to Write End 7 8ns
tHA Address Hold from Write End 0 0ns
tSA Address Setup to Write Start 0 0ns
tPWE WE Pulse Width 7 8ns
tSD Data Setup to Write End 5 6ns
tHD Data Hold from Write End 0 0ns
tLZWE WE HIGH to Low-Z[11] 3 3 ns
tHZWE WE LOW to High-Z[10, 11] 56ns
tBW Byte Enable to End of Write 7 8ns
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
9. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
10.tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads and Waveforms. Transition is measuredwhen the outputs enter
a high impedance state.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given
device.
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 6 of 13
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions[14] Min Max Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Ind’l 10 mA
Auto 15 mA
tCDR[6] Chip Deselect to Data Retention Time 0 ns
tR[15] Operation Recovery Time tRC ns
Data Retention Waveform
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Figure 4. Read Cycle No. 1[16, 17]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
Notes
12.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
13.The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
14.No input may exceed VCC + 0.3V.
15.Full device operation requires linear VCC ramp from VDR to VCC(min.) >50 μs or stable at VCC(min.) >50 μs.
16.Device is continuously selected. OE, CE, BHE, and BHE = VIL.
17.WE is HIGH for read cycle.
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 7 of 13
Figure 5. Read Cycle No. 2 (OE Controlled)[17, 18]
Figure 6. Write Cycle No. 1 (CE Controlled)[19, 20]
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
CURRENT
ICC
ISB
tHD
tSD
tSCE tSA
tHA
tAW
tPWE
tWC
BW
DATAIO
ADDRESS
CE
WE
BHE, BLE
t
Notes
18.Address valid prior to or coincident with CE transition LOW.
19.Data IO is high impedance if OE or BHE and BLE = VIH.
20.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 8 of 13
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
Figure 8. Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[19, 20]
Switching Waveforms (continued)
tHD
tSD
tBW tSA
tHA
tAW
tPWE
tWC
tSCE
DATAIO
ADDRESS
BHE,BLE
WE
CE
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA IO
OE
NOTE 21
BHE,BLE
Note
21.During this period the IOs are in the output state and input signals should not be applied.
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 9 of 13
Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW)
Truth Table
CE OE WE BLE BHE IO0–IO7IO8–IO15 Mode Power
H X X X X High-Z High-Z Power Down Standby (ISB)
L L H L L Data Out Data Out Read All Bits Active (ICC)
L L H L H Data Out High-Z Read Lower Bits Only Active (ICC)
L L H H L High-Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Data In Write All Bits Active (ICC)
L X L L H Data In High-Z Write Lower Bits Only Active (ICC)
L X L H L High-Z Data In Write Upper Bits Only Active (ICC)
L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC)
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA IO
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
NOTE 21
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 10 of 13
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
10 CY7C1041DV33-10BVI 51-85150 48-Ball VFBGA Industrial
CY7C1041DV33-10BVXI 48-Ball VFBGA (Pb-Free) Pinout - 1 [4]
CY7C1041DV33-10BVJXI 48-Ball VFBGA (Pb-Free) Pinout - 2 [4]
CY7C1041DV33-10VXI 51-85082 44-Pin (400-mil) Molded SOJ (Pb-Free)
CY7C1041DV33-10ZSXI 51-85087 44-Pin TSOP II (Pb-Free)
12 CY7C1041DV33-12BVXE 51-85150 48-Ball VFBGA (Pb-Free) Automotive
CY7C1041DV33-12VXE 51-85082 44-Pin (400-mil) Molded SOJ (Pb-Free)
CY7C1041DV33-12ZSXE 51-85087 44-Pin TSOP II (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
Package Diagrams Figure 10. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)
a
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 11 of 13
Figure 11. 44-Pin (400-mil) Molded SOJ (51-85082)
Figure 12. 44-Pin TSOP II (51-85087)
Package Diagrams(continued)
51-85082-*B
51-85087-*A
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CY7C1041DV33
Document #: 38-05473 Rev. *E Page 12 of 13
Document History Page
Document Title: CY7C1041DV33 4 Mbit (256K x 16) Static RAM
Document Number: 38-05473
Rev. ECN No. Orig. of
Change Submission Date Description of Change
** 201560 SWI See ECN Advance Data sheet for C9 IPP
*A 233729 RKF See ECN 1.AC, DC parameters are modified as per EROS(Spec # 01-2165)
2.Pb-free offering in the ‘Ordering information’
*B 351117 PCI See ECN Changed from Advance to Preliminary
Removed 15 and 20 ns Speed bin
Corrected DC voltage (min) value in maximum ratings section from - 0.5 to
- 0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10
and 12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mAfor 10 and 12ns speed
bins respectively
Added Static Discharge Voltage and latch-up current spec
Added VIH(max)spec in Note# 2
Changed Note# 4 on AC Test Loads
Changed reference voltage level for measurement of Hi-Z parameters from
±500 mV to ±200 mV
Added Data Retention Characteristics/Waveform and footnote # 11, 12
Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram
Changed Package Diagram name from 44-Pin TSOP II Z44 to 44-Pin TSOP II
ZS44 and from 44-Pin (400-mil) Molded SOJ V34 to 44-Pin (400-mil) Molded
SOJ V44
Changed part names from Z to ZS in the Ordering Information Table
Added 8 ns Product Information
Added Pin-Free Ordering Information
Shaded Ordering Information Table
*C 446328 NXR See ECN Converted from Preliminary to Final
Removed -8 speed bin
Removed Commercial Operating Range product information
Included Automotive Operating Range product information
Updated Thermal Resistance table
Updated footnote #8 on High-Z parameter measurement
Updated the ordering information and replaced Package Name column with
Package Diagram in the Ordering Information Table
*D 480177 VKN See ECN Added -10BVI product ordering code in the Ordering Information table
*E 2541850 VKN/PYRS 07/22/08 Added -10BVJXI part
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CY7C1041DV33
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for thesole purpose of creating custom software and orfirmware insupport of licensee product tobe used only in conjunctionwith a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code exceptas specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05473 Rev. *E Revised July 17, 2008 Page 13 of13
All product and company names mentioned in this document are the trademarks of their respective holders.
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