Cypress Semiconductor Quad HOTLink II CYV15G0404RB User manual

Independent Clock Quad HOTLink II™
Deserializing Reclocke
r
CYV15G0404RB
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-02102 Rev. *C Revised February 16, 2007
Features
• Second-generation HOTLink®technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Quad channel video reclocking deserializer
— 195 to 1500 Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supportsreceptionofeither1.485or1.485/1.001Gbpsdata
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
— Internal DC restoration
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power: 3W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
•0.25µBiCMOS technology
Functional Description
The CYV15G0404RB Independent Clock Quad HOTLink II™
Deserializing Reclocker is a point-to-point or point-to-multi-
point communications building block enabling data transfer
over a variety of high speed serial links including SMPTE 292
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps for each serial link. The four
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs. Figure 1, "HOTLink II™ System Connections,"
on page 2 illustrates typical connections between independent
video coprocessors and corresponding CYV15G0404RB
ReclockingDeserializerandCYV15G0403TBSerializer chips.
The CYV15G0404RB is SMPTE-259M and SMPTE-292M
compliant according to SMPTE EG34-1999 Pathological Test
Requirements.
As a second generation HOTLink device, the
CYV15G0404RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices.
Eachchannel of the CYV15G0404RB Quad HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and DataRecoveryPLL, recovers
the timing information necessary for data reconstruction. The
device reclocks and retransmits recovered bit-stream through
the reclocker serial outputs. It also deserializes the recovered
serial data and presents it to the destination host system.
Each channel contains an independent BIST pattern checker.
This BIST hardware enables at speed testing of the
high-speed serial data paths in each receive section of this
device, each transmit section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0404RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 2 of 27
Figure 1. HOTLink II™ System Connections
Video Coprocessor
10
10
10
10
Video Coprocessor
10
10
10
10
Serial Links
Independent
CYV15G0403TB
Independent
Reclocking Deserializer
Serializer
Channel
CYV15G0404RB
Channel
Reclocked
Outputs
Reclocked
Outputs
CYV15G0404RB Deserializing Reclocker Logic Block Diagram
x10
Deserializer
Reclocker RX
RXDA[9:0]
ROUTA1±
ROUTA2±
INA1±
INA2± TRGCLKA±
x10
Deserializer
Reclocker RX
RXDB[9:0]
ROUTB1±
ROUTB2±
INB1±
INB2± TRGCLKB±
x10
Deserializer
Reclocker RX
RXDC[9:0]
ROUTC1
±
ROUTC2
±
INC1
±
INC2
±
TRGCLKC±
x10
Deserializer
Reclocker RX
RXDD[9:0]
ROUTD1
±
ROUTD2
±
IND1
±
IND2
±
TRGCLKD±
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 3 of 27
Reclocking Deserializer Path Block Diagram
INA1+
INA1–
INA2+
INA2–
INSELA
Clock &
Data
Recovery
PLL
Shifter
LFIA
10 RXDA[9:0]
Receive
Signal
Monitor
Output
Register
RXCLKA+
RXCLKA–
÷2
RXPLLPDA
SPDSELA
ULCA
RXRATEA
10
BIST LFSR
10
RXBISTA[1:0]
LDTDEN SDASEL[2..1]A[1:0]
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
ROE[2..1]A
TRGCLKA x2
TRGRATEA
BISTSTA
Character-Rate Clock A
Reclocker
RECLKOA
Register
Recovered Character Clock Recovered Serial Data
REPDOA
Clock Multiplier A
Output PLL ROE[2..1]A
INB1+
INB1–
INB2+
INB2–
INSELB
Clock &
Data
Recovery
PLL
Shifter
LFIB
10 RXDB[9:0]
Receive
Signal
Monitor
Output
Register
RXCLKB+
RXCLKB–
÷2
RXPLLPDB
SPDSELB
ULCB
RXRATEB
10
BIST LFSR
10
RXBISTB[1:0]
LDTDEN SDASEL[2..1]B[1:0]
ROUTB1+
ROUTB1–
ROUTB2+
ROUTB2–
ROE[2..1]B
TRGCLKB x2
TRGRATEB
BISTSTB
Character-Rate Clock B
Reclocker
RECLKOB
Register
Recovered Character Clock Recovered Serial Data
REPDOB
Clock Multiplier B
Output PLL ROE[2..1]B
= Internal Signal
JTAG
Boundary
Scan
Controller TDO
TMS
TCLK
TDI
RESET
TRST
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 4 of 27
Reclocking Deserializer Path Block Diagram (continued) = Internal Signal
INC1+
INC1–
INC2+
INC2–
INSELC
Clock &
Data
Recovery
PLL
Shifter
LFIC
10 RXDC[9:0]
Receive
Signal
Monitor
Output
Register
RXCLKC+
RXCLKC–
÷2
RXPLLPDC
SPDSELC
ULCC
RXRATEC
10
BIST LFSR
10
RXBISTC[1:0]
LDTDEN SDASEL[2..1]C[1:0]
ROUTC1+
ROUTC1–
ROUTC2+
ROUTC2–
ROE[2..1]C
TRGCLKC x2
TRGRATEC
BISTSTC
Character-Rate Clock C
Reclocker
RECLKOC
Register
Recovered Character Clock Recovered Serial Data
REPDOC
Clock Multiplier C
Output PLL ROE[2..1]C
IND1+
IND1–
IND2+
IND2–
INSELD
Clock &
Data
Recovery
PLL
Shifter
LFID
10 RXDD[9:0]
Receive
Signal
Monitor
Output
Register
RXCLKD+
RXCLKD–
÷2
RXPLLPDD
SPDSELD
ULCD
RXRATED
10
BIST LFSR
10
RXBISTD[1:0]
LDTDEN SDASEL[2..1]D[1:0]
ROUTD1+
ROUTD1–
ROUTD2+
ROUTD2–
ROE[2..1]D
TRGCLKD x2
TRGRATED
BISTSTD
Character-Rate Clock D
Reclocker
RECLKOD
Register
Recovered Character Clock Recovered Serial Data
REPDOD
Clock Multiplier D
Output PLL ROE[2..1]D
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 5 of 27
WREN
ADDR[3:0]
DATA[7:0]
Device Configuration and Control Block Diagram = Internal Signal
RXRATE[A..D]
RXBIST[A..D]
SDASEL[A..D][1:0]
RXPLLPD[A..D]
ROE[2..1][A..D]
GLEN[11..0]
FGLEN[2..0]
Device Configuration
and Control Interface
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 6 of 27
Pin Configuration (Top View)[1]
Note
1. NC = Do not connect.
12345678910 11 12 13 14 15 16 17 18 19 20
AIN
C1– ROUT C1– IN C2– ROUT C2– VCC IN D1– ROUT D1– GND IN D2– ROUT D2– IN A1– ROUT A1– GND IN A2– ROUT A2– VCC IN B1– ROUT B1– IN B2– ROUT B2–
BIN
C1+ ROUT C1+ IN C2+ ROUT C2+ VCC IN D1+ ROUT D1+ GND IN D2+ ROUT D2+ IN A1+ ROUT A1+ GND IN A2+ ROUT A2+ VCC IN B1+ ROUT B1+ IN B2+ ROUT B2+
CTDI TMS INSELC INSELB VCC ULCD ULCC GND DATA
[7] DATA [5] DATA [3] DATA [1] GND VCC SPD SELD VCC LDTD EN TRST GND TDO
DTCLK RESET INSELD INSELA VCC ULCA SPD
SELC GND DATA [6] DATA [4] DATA [2] DATA [0] GND GND ULCB VCC NC VCC SCAN EN2 TMEN3
EVCC VCC VCC VCC VCC VCC VCC VCC
FRX
DC[8] RX DC[9] VCC VCC VCC RX DB[0] RE CLKOB RX DB[1]
GGND WREN GND GND SPD
SELB NC SPD SELA RX DB[3]
HGND GND GND GND GND GND GND GND
JGND GND GND GND BIST
STB RX DB[2] RX DB[7] RX DB[4]
KRX
DC[4] TRG CLKC– GND GND RX DB[5] RX DB[6] RX DB[9] LFIB
LRX
DC[5] TRG CLKC+ LFIC GND RX DB[8] RX CLKB+ RX CLKB– GND
MRX
DC[6] RX DC[7] VCC RE PDOC TRG CLKB+ TRG CLKB– RE PDOB GND
NGND GND GND GND GND GND GND GND
PRX
DC[3] RX DC[2] RX DC[1] RX DC[0] GND GND GND GND
RBIST
STC RE CLKOC RX CLKC+ RX CLKC– VCC VCC VCC VCC
TVCC VCC VCC VCC VCC VCC VCC VCC
UVCC VCC VCC VCC VCC RX
DD[4] RX DD[3] GND GND ADDR [0] TRG CLKD– GND GND GND VCC VCC RX DA[4] VCC BIST STA RX DA[0]
VVCC VCC VCC RX
DD[8] VCC RX DD[5] RX DD[1] GND BIST STD ADDR [2] TRG CLKD+ RE CLKOA GND GND VCC VCC RX DA[9] RX DA[5] RX DA[2] RX DA[1]
WVCC VCC LFID RX
CLKD– VCC RX DD[6] RX DD[0] GND ADDR [3] ADDR [1] RX CLKA+ RE PDOA GND GND VCC VCC LFIA TRG CLKA+ RX DA[6] RX DA[3]
YVCC VCC RX
DD[9] RX CLKD+ VCC RX DD[7] RX DD[2] GND RE CLKOD NC GND RX CLKA– GND GND VCC VCC RE PDOD TRG CLKA– RX DA[8] RX DA[7]
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 7 of 27
Pin Configuration (Bottom View)[1]
20 19 18 17 16 15 14 13 12 11 10 987654321
AROUT
B2– IN B2– ROUT B1– IN B1– VCC ROUT A2– IN A2– GND ROUT A1– IN A1– ROUT D2– IN D2– GND ROUT D1– IN D1– VCC ROUT C2– IN C2– ROUT C1– IN C1–
BROUT
B2+ IN B2+ ROUT B1+ IN B1+ VCC ROUT A2+ IN A2+ GND ROUT A1+ IN A1+ ROUT D2+ IN D2+ GND ROUT D1+ IN D1+ VCC ROUT C2+ IN C2+ ROUT C1+ IN C1+
CTDO GND TRST LDTD
EN VCC SPD SELD VCC GND DATA [1] DATA [3] DATA [5] DATA [7] GND ULCC ULCD VCC INSELB INSELC TMS TDI
DTMEN3 SCAN
EN2 VCC NC VCC ULCB GND GND DATA [0] DATA [2] DATA [4] DATA [6] GND SPD SELC ULCA VCC INSELA INSELD RESET TCLK
EVCC VCC VCC VCC VCC VCC VCC VCC
FRX
DB[1] RE CLKOB RX DB[0] VCC VCC VCC RX DC[9] RX DC[8]
GRX
DB[3] SPD SELA NC SPD SELB GND GND WREN GND
HGND GND GND GND GND GND GND GND
JRX
DB[4] RX DB[7] RX DB[2] BIST STB GND GND GND GND
KLFIB RX
DB[9] RX DB[6] RX DB[5] GND GND TRG CLKC– RX DC[4]
LGND RX
CLKB– RX CLKB+ RX DB[8] GND LFIC TRG CLKC+ RX DC[5]
MGND RE
PDOB TRG CLKB– TRG CLKB+ RE PDOC VCC RX DC[7] RX DC[6]
NGND GND GND GND GND GND GND GND
PGND GND GND GND RX
DC[0] RX DC[1] RX DC[2] RX DC[3]
RVCC VCC VCC VCC RX
CLKC– RX CLKC+ RE CLKOC BIST STC
TVCC VCC VCC VCC VCC VCC VCC VCC
URX
DA[0] BIST STA VCC RX DA[4] VCC VCC GND GND GND TRG CLKD– ADDR [0] GND GND RX DD[3] RX DD[4] VCC VCC VCC VCC VCC
VRX
DA[1] RX DA[2] RX DA[5] RX DA[9] VCC VCC GND GND RE CLKOA TRG CLKD+ ADDR [2] BIST STD GND RX DD[1] RX DD[5] VCC RX DD[8] VCC VCC VCC
WRX
DA[3] RX DA[6] TRG CLKA+ LFIA VCC VCC GND GND RE PDOA RX CLKA+ ADDR [1] ADDR [3] GND RX DD[0] RX DD[6] VCC RX CLKD– LFID VCC VCC
YRX
DA[7] RX DA[8] TRG CLKA– RE PDOD VCC VCC GND GND RX CLKA– GND NC RE CLKOD GND RX DD[2] RX DD[7] VCC RX CLKD+ RX DD[9] VCC VCC
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 8 of 27
Pin Definitions
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name IO Characteristics Signal Description
Receive Path Data and Status Signals
RXDA[9:0]
RXDB[9:0]
RXDC[9:0]
RXDD[9:0]
LVTTL Output,
synchronous to the
RXCLK± output
Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the
receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs
are complementary clocks operating at the character rate. The RXDx[9:0] outputs
for the associated receive channels follow the rising edge of RXCLKx+ or the
falling edge of RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock
outputs are complementary clocks operating at half the character rate. The
RXDx[9:0] outputs for the associated receive channels follow both the falling and
rising edges of the associated RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the RXDx[1:0] and BISTSTx
outputs present the BIST status. See Table 5, “Receive BIST Status Bits,” on
page 17 for each status that the BIST state machine reports. Also, while BIST is
enabled, ignore the RXDx[9:2] outputs.
BISTSTA
BISTSTB
BISTSTC
BISTSTD
LVTTL Output,
synchronous to the
RXCLKx± output
BIST Status Output.When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See Table 5, “Receive BIST Status Bits,”
on page 17 for the BIST status for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0] ≠10, ignore BISTSTx.
REPDOA
REPDOB
REPDOC
REPDOD
Asynchronous to
reclocker output
channel
enable / disable
Reclocker Powered Down Status Output.REPDOx asserts HIGH when the
associated channel’s reclocker output logic powers down. This occurs when
disabling ROE2x and ROE1x by setting ROE2x = 0 and ROE1x = 0.
Receive Path Clock Signals
TRGCLKA±
TRGCLKB±
TRGCLKC±
TRGCLKD±
Differential LVPECL or
single-ended
LVTTL input clock
CDR PLL Training Clock. The frequency detector (Range Controller) of the
associated receive PLL uses the TRGCLKx± clock inputs as the reference source
to reduce PLL acquisition time.
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When a single-ended LVCMOS or LVTTL clock source drives the clock, connect
the clock source to either the true or complement TRGCLKx input, and leave the
alternate TRGCLKx input open (floating). When an LVPECL clock source drives
it, the clock must be a differential clock, using both inputs.
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
LVTTL Output Clock Receive Clock Output. RXCLKx± is the receive interface clock that controls
timing of the RXDx[9:0] parallel outputs. These true and complement clocks
control timing of data output transfers. These clocks output continuously at either
the half-character rate (1/20 the serial bit-rate) or character rate (1/10 the serial
bit-rate) of the data being received, as selected by RXRATEx.
RECLKOA
RECLKOB
RECLKOC
RECLKOD
LVTTL Output Reclocker Clock Output. The associated reclocker output PLL synthesizes the
RECLKOx output clock, which operates synchronous to the internal recovered
character clock. RECLKOx operates at either the same frequency as RXCLKx±
(RXRATEx = 0), or at twice the frequency of RXCLKx± (RXRATEx = 1). The
reclocker clock outputs have no fixed phase relationship to RXCLKx±.
Device Control Signals
RESET LVTTL Input,
asynchronous,
internal pull up
Asynchronous Device Reset. RESET initializes all state machines, counters,
and configuration latches in the device to a known state. RESET must assert LOW
for a minimum pulse width. When the reset is removed, all state machines,
counters and configuration latches are at an initial state. According to the JTAG
specifications, the device RESET cannot reset the JTAG controller. Therefore, the
JTAG controller has to be reset separately. Refer to “JTAG Support” on page 17
for the methods to reset the JTAG state machine. See Table 3, “Device Configu-
ration and Control Latch Descriptions,” on page 14 for the initialize values of the
device configuration latches.
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 9 of 27
LDTDEN LVTTL Input,
internal pull up Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level Detector, Range Controller, and Transition Density Detector are all enabled
to determine if the RXPLL tracks TRGCLKx± or the selected input serial data
stream. If the Signal Level Detector, Range Controller, or Transition Density
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks
to TRGCLKx± until they become valid. The SDASEL[A..D][1:0] inputs configure
the trip level of the Signal Level Detector. The Transition Density Detector limit is
one transition in every 60 consecutive bits. When LDTDEN is LOW, only the
Range Controller determines if the RXPLL tracks TRGCLKx± or the selected input
serial data stream. Set LDTDEN = HIGH.
ULCA
ULCB
ULCC
ULCD
LVTTL Input,
internal pull up Use Local Clock. When ULCx is LOW, the RXPLL locks to TRGCLKx± instead of the received serial data stream. While ULCx is LOW, the LFIx for the associated
channel is LOW, indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications that need a stable
RXCLKx±. When valid data transitions are absent for a long time, or the high-gain
differential serial inputs (INx±) are left floating, the RXCLKx± outputs may briefly
be different from TRGCLKx±.
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select[2]
static control input Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range of each channel’s receive PLL.
LOW = 195–400 MBd
MID = 400–800 MBd
HIGH = 800–1500 MBd.
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous Receive Input Selector. The INSELx input determines which external serial bit stream passes to the receiver’s Clock and Data Recovery circuit. When INSELx
isHIGH, thePrimaryDifferentialSerial DataInput,INx1±, is theassociatedreceive
channel. When INSELx is LOW, the Secondary Differential Serial Data Input,
INx2±, is the associated receive channel.
LFIA
LFIB
LFIC
LFID
LVTTL Output,
asynchronous Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the logical OR of six internal conditions. LFIx asserts LOW when any of the following
conditions is true:
• Received serial data rate is outside expected range
• Analog amplitude is below expected levels
• Transition density is lower than expected
• Receive is channel disabled
•ULCx
is LOW
• TRGCLKx± is absent.
Device Configuration and Control Bus Signals
WREN LVTTL input,
asynchronous,
internal pull up
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.[3]
ADDR[3:0] LVTTL input
asynchronous,
internal pull up
Control Addressing Bus. The ADDR[3:0] bus is the input address bus that
configures the device. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.[3] Table 3,
“DeviceConfiguration and ControlLatchDescriptions,”onpage 14lists the config-
uration latches within the device, and the initialization value of the latches when
RESET is asserted. Table 4, “Device Control Latch Configuration Table,” on
page 16 shows how the latches are mapped in the device.
Notes
2. Use 3-Level Select inputs for static configuration. These are ternary inputs that use logic levels of LOW, MID, and HIGH. To implement the LOW level, connect
directly to VSS (ground). To implement the HIGH level, connect directly to VCC (power). To implement the MID level, do not connect the input (leave floating),
which allows it to self bias to the proper level.
3. See “Device Configuration and Control Interface” on page 13 for detailed information about the operation of the Configuration Interface.
Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name IO Characteristics Signal Description
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CYV15G0404RB
Document #: 38-02102 Rev. *C Page 10 of 27
DATA[7:0] LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[7:0] bus is the input data bus that configures the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.[3] Table 3, “Device Configu-
ration and Control Latch Descriptions,” on page 14 lists the configuration latches
within the device, and the initialization value of the latches when RESET is
asserted. Table 4, “Device Control Latch Configuration Table,” on page 16 shows
the way the latches are mapped in the device.
Internal Device Configuration Latches
RXRATE[A..D] Internal Latch[4] Receive Clock Rate Select.
SDASEL[2..1][A..D]
[1:0] Internal Latch[4] Signal Detect Amplitude Select.
RXPLLPD[A..D] Internal Latch[4] Receive Channel Power Control.
RXBIST[A..D][1:0] Internal Latch[4] Receive BIST Disabled.
ROE2[A..D] Internal Latch[4] Reclocker Differential Serial Output Driver 2 Enable.
ROE1[A..D] Internal Latch[4] Reclocker Differential Serial Output Driver 1 Enable.
GLEN[11..0] Internal Latch[4] Global Latch Enable.
FGLEN[2..0] Internal Latch[4] Force Global Latch Enable.
Factory Test Modes
SCANEN2 LVTTL input,
internal pull down Factory Test 2. The SCANEN2 input is for factory testing only. Leave this input as a NO CONNECT, or GND only.
TMEN3 LVTTL input,
internal pull down Factory Test 3. The TMEN3 input is for factory testing only. Leave this input as a NO CONNECT, or GND only.
Analog I/O
ROUTA1±
ROUTB1±
ROUTC1±
ROUTD1±
CML Differential
Output Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML outputs (+3.3V referenced) can drive terminated transmission lines or standard
fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
ROUTA2±
ROUTB2±
ROUTC2±
ROUTD2±
CML Differential
Output Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission
lines or standard fiber-optic transmitter modules, and must be AC coupled for
PECL-compatible connections.
INA1±
INB1±
INC1±
IND1±
Differential Input Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream passes to the receive CDR
circuit to extract the data content when INSELx = HIGH.
INA2±
INB2±
INC2±
IND2±
Differential Input Secondary Differential Serial Data Input. The INx2± input accepts the serial
data stream for deserialization. The INx2± serial stream passes to the receiver
CDR circuit to extract the data content when INSELx = LOW.
JTAG Interface
TMS LVTTL Input,
internal pull up Test Mode Select. Controls access to the JTAG Test Modes. If TMS is HIGH for >5 TCLK cycles, the JTAG test controller resets.
TCLK LVTTL Input,
internal pull down JTAG Test Clock.
Note
4. See Device Configuration and Control Interface for detailed information on the internal latches.
Pin Definitions (continued)
CYV15G0404RB Quad HOTLink II Deserializing Reclocker
Name IO Characteristics Signal Description
[+] Feedback