Cypress Semiconductor NoBL CY7C1352G User manual

4-Mbit(256Kx18)PipelinedSRAMwith
NoBL™ Architecture
CY7C1352G
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05514 Rev. *D Revised July 4, 2006
Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• Available in lead-free 100-Pin TQFP package
• Burst Capability—linear or interleaved burst order
• ZZ” Sleep Mode Option and Stop Clock option
Functional Description[1]
The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352G is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).
Write operations are controlled by the two Byte Write Select
(BW[A:B]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
A0, A1, A
C
MODE
BWA
BWB
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
A
DQP
B
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1 WRITE ADDRESS REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC A0'
A1'
D1
D0 Q1 Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
C
EN
WRITE
DRIVERS
ZZ
Sleep
Control
Logic Block Diagram
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CY7C1352G
Document #: 38-05514 Rev. *D Page 2 of 12
Selection Guide
250 MHz 200 MHz 166 MHz 133 MHz Unit
Maximum Access Time 2.6 2.8 3.5 4.0 ns
Maximum Operating Current 325 265 240 225 mA
Maximum CMOS Standby Current 40 40 40 40 mA
Pin Configuration
A A A A A1 A0
NC/288M
NC/144M
VSS
VDD
NC/36M
A A A A A
A
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
A A
CE1
CE2
NC NC
BWB BWA CE3 VDD VSS
CLK
WE
CEN OE
A A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
ADV/LD
ZZ
MODE
NC/72M
NC/18M
NC/9M
CY7C1352G
100-Pin TQFP Pinout
BYTE A
BYTE B
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CY7C1352G
Document #: 38-05514 Rev. *D Page 3 of 12
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous Address Inputs used to select one of the 256K address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:B] Input-
Synchronous Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK.
WE Input-
Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD Input-
Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2and CE3to select/deselect the device.
CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3to select/deselect the device.
CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.
OE Input-
Asynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the DQ pins are
allowed to behave as outputs. When deasserted HIGH,DQ pins are tri-stated, and act asinput
datapins. OEismaskedduringthedataportionof awritesequence,duringthefirst clockwhen
emerging from a deselected state, when the device has been deselected.
CEN Input-
Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
ZZ Input-
Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with data integrity preserved. During normal operation, this pin has to be low or left
floating. ZZ pin has an internal pull-down.
DQs I/O-
Synchronous BidirectionalDataI/OLines.Asinputs,theyfeedintoanon-chipdataregisterthatistriggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the address during the clock rise of the read cycle. The direction of the pins is
controlledbyOEandtheinternalcontrollogic.WhenOE isassertedLOW,thepinscanbehave
as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition. The outputs are
automatically tri-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state
of OE.
DQP[A:B] I/O-
Synchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQP[A:B] is controlled by BW[A:B] correspondingly.
MODE Input Strap Pin Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects
interleaved burst sequence.
VDD Power Supply Power supply inputs to the core of the device.
VDDQ I/OPower Supply Power supply for the I/O circuitry.
VSS Ground Ground for the device.
NC – No Connects. Not internally connected to the die.
NC/36M,
NC/72M,
NC/144M,
NC/288M
–No Connects.Notinternallyconnectedtothe die.NC/36M, NC/72M, NC/144M,NC/288M are
address expansion pins are not internally connected to the die.
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CY7C1352G
Document #: 38-05514 Rev. *D Page 4 of 12
Functional Overview
The CY7C1352G is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.6 ns (250-MHz
device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[A:B] can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through theoutput registerandonto the databus,providedOE
isactive LOW.Afterthe firstclockof thereadaccess theoutput
buffers are controlled by OE and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.
Burst Read Accesses
The CY7C1352G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM,asdescribedin theSingle ReadAccesssection above.
Thesequenceof theburst counter is determinedby theMODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginningof aburstcycle. Therefore,the typeofaccess (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
isasserted LOW. Theaddresspresentedto theaddressinputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP[A:B]. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and
DQP[A:B] (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the Write operation is controlled by
BW[A:B] signals. The CY7C1352G provides byte write
capabilitythatis describedin theWriteCycleDescriptiontable.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW[A:B]) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify thewrite operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
Because the CY7C1352G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQP[A:B] inputs. Doing
so will tri-state the output drivers. As a safety precaution, DQs
and DQP[A:B] are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1352G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:B] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the“sleep” mode.CE1, CE2,and CE3,must remain inactivefor
the duration of tZZREC after the ZZ input returns LOW.
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CY7C1352G
Document #: 38-05514 Rev. *D Page 5 of 12
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Snooze mode standby current ZZ > VDD − 0.2V 40 mA
tZZS Device operation to ZZ ZZ > VDD −0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ active to snooze current This parameter is sampled 2tCYC ns
tRZZI ZZ inactive to exit snooze current This parameter is sampled 0 ns
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State
WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State
IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H –
SNOOZE MODE None X H X X X X X X Tri-State
Truth Table for Read/Write [2, 3]
Function WE BWBBWA
Read H X X
Write − No bytes written L H H
Write Byte A − (DQA and DQPA)LHL
Write Byte B − (DQB and DQPB)LLH
Write All Bytes L L L
Notes:
2. X=”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for ALL Chip Enables active. BWX= L signifies at least one Byte Write Select is active, BWX= Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW[A:B], and WE. See Write Cycle Descriptions table.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when
OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.
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CY7C1352G
Document #: 38-05514 Rev. *D Page 6 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND .......−0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state..................................................−0.5V to VDDQ + 0.5V
DC Input Voltage ...................................... −0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature (TA)V
DD VDDQ
Commercial 0°C to +70°C 3.3V –5%
+10% 2.5V–5% to VDD
Industrial –40°C to +85°C
Electrical Characteristics Over the Operating Range[9, 10]
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ I/O Supply Voltage 2.375 VDD V
VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V
for 2.5V I/O, IOH = –1.0 mA 2.0 V
VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA 0.4 V
for 2.5V I/O, IOL = 1.0 mA 0.4 V
VIH Input HIGH Voltage[9] for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 VDD + 0.3V V
VIL Input LOW Voltage[9] for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V
IXInput Leakage Current
except ZZ and MODE GND ≤VI≤VDDQ −55µA
Input Current of MODE Input = VSS −30 µA
Input = VDD 5µA
Input Current of ZZ Input = VSS −5µA
Input = VDD 30 µA
IOZ Output Leakage Current GND ≤VI≤VDDQ, Output Disabled −55µA
IDD VDD Operating Supply
Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 325 mA
5-ns cycle, 200 MHz 265 mA
6-ns cycle, 166 MHz 240 mA
7.5-nscycle,133 MHz 225 mA
ISB1 Automatic CE
Power-Down
Current—TTL Inputs
VDD=Max,DeviceDeselected,
VIN ≥VIH or VIN ≤VIL
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz 120 mA
5-ns cycle, 200 MHz 110 mA
6-ns cycle, 166 MHz 100 mA
7.5-nscycle,133 MHz 90 mA
ISB2 Automatic CE
Power-down
Current—CMOS Inputs
VDD=Max,DeviceDeselected,
VIN ≤0.3V or
VIN > VDDQ – 0.3V, f = 0
All speeds 40 mA
ISB3 Automatic CE
Power-down
Current—CMOS Inputs
VDD=Max,DeviceDeselected,
or VIN ≤0.3V or
VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz 105 mA
5-ns cycle, 200 MHz 95 mA
6-ns cycle, 166 MHz 85 mA
7.5-nscycle,133 MHz 75 mA
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
10.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ <VDD.
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CY7C1352G
Document #: 38-05514 Rev. *D Page 7 of 12
ISB4 Automatic CE
Power-down
Current—TTL Inputs
VDD=Max,DeviceDeselected,
VIN ≥VIH or VIN ≤VIL, f = 0 All speeds 45 mA
Capacitance[11]
Parameter Description Test Conditions 100 TQFP Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
5pF
CCLK Clock Input Capacitance 5 pF
CI/O Input/Output Capacitance 5 pF
Thermal Resistance[11]
Parameter Description Test Conditions 100 TQFP Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and procedures for measuring
thermal impedance, per EIA/JESD51.
30.32 °C/W
ΘJC Thermal Resistance
(Junction to Case) 6.85 °C/W
AC Test Loads and Waveforms
Note:
11.Tested initially and after any design or process changes that may affect these parameters.
Electrical Characteristics Over the Operating Range[9, 10] (continued)
Parameter Description Test Conditions Min. Max. Unit
1ns
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
V
T
= 1.5V
3.3V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
≤1 ns ≤1 ns
(c)
OUTPUT
R = 1667Ω
R = 1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
VT= 1.25V
2.5V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
≤1 ns ≤1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
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CY7C1352G
Document #: 38-05514 Rev. *D Page 8 of 12
Switching Characteristics Over the Operating Range [16, 17]
Parameter Description
–250 –200 –166 –133
UnitMin. Max. Min. Max. Min. Max. Min. Max.
tPOWER VDD (typical) to the first Access[12] 1111ms
Clock
tCYC Clock Cycle Time 4.0 5.0 6.0 7.5 ns
tCH Clock HIGH 1.7 2.0 2.5 3.0 ns
tCL Clock LOW 1.7 2.0 2.5 3.0 ns
Output Times
tCO Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns
tDOH Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns
tCLZ Clock to Low-Z[13, 14, 15] 0000ns
tCHZ Clock to High-Z[13, 14, 15] 2.6 2.8 3.5 4.0 ns
tOEV OE LOW to Output Valid 2.6 2.8 3.5 4.0 ns
tOELZ OE LOW to Output Low-Z[13, 14, 15] 0000ns
tOEHZ OE HIGH to Output High-Z[13, 14, 15] 2.6 2.8 3.5 4.0 ns
Set-up Times
tAS Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
tALS ADV/LD Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
tWES GW, BW[A:B] Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 ns
tCENS CEN Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
tDS Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
tCES Chip Enable Set-up Before CLK Rise 1.2 1.2 1.5 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
tALH ADV/LD Hold after CLK Rise 0.3 0.5 0.5 0.5 ns
tWEH GW, BW[A:B] Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
tCENH CEN Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
tDH Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 ns
Notes:
12.This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
13.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) ofAC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
15.This parameter is sampled and not 100% tested.
16.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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CY7C1352G
Document #: 38-05514 Rev. *D Page 9 of 12
Switching Waveforms
Read/Write Timing[18, 19, 20]
Notes:
18.For this waveform ZZ is tied low.
19.When CE is LOW: CE1is LOW, CE2is HIGH and CE3is LOW. When CE is HIGH: CE1is HIGH or CE2 is LOW or CE3is HIGH.
20.Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
WRITE
D(A1)
123456789
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW[A:B]
ADV/LD
t
AH
t
AS
ADDRESS A1 A2 A3 A4 A5 A6 A7
t
DH
t
DS
Data
I
n-Out (DQ)
t
CLZ
D(A1) D(A2) D(A5)Q(A4)Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2) BURST WRITE
D(A2+1)
READ
Q(A3) READ Q(A4) BURST READ
Q(A4+1)
WRITE
D(A5) READ Q(A6) WRITE D(A7) DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE UNDEFINED
Q(A6)
Q(A4+1)
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CY7C1352G
Document #: 38-05514 Rev. *D Page 10 of 12
NOP, STALL, and DESELECT Cycles[18, 19, 21]
ZZ Mode Timing[22, 23]
Notes:
21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
23.DQs are in high-Z when exiting ZZ sleep mode.
Switching Waveforms (continued)
READ
Q(A3)
45678910
CLK
CE
WE
CEN
BW [A:B]
ADV/LD
ADDRESS A3 A4 A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4) STALLWRITE D(A1)
123
READ
Q(A2) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT
DON’T CARE UNDEFINED
t
CHZ
A2
D(A1) Q(A2) Q(A3)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
A
LL INPUTS
(except ZZ)
IDDZZ
tZZI
tRZZI
DESELECT or READ Only
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CY7C1352G
Document #: 38-05514 Rev. *D Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code Package Diagram Package Type Operating Range
133 CY7C1352G-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1352G-133AXI Industrial
166 CY7C1352G-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1352G-166AXI Industrial
200 CY7C1352G-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1352G-200AXI Industrial
250 CY7C1352G-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1352G-250AXI Industrial
Package Diagram
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
3. DIMENSIONS IN MILLIMETERS
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
0.30±0.08
0.65
20.00±0.10
22.00±0.20
1.40±0.05
12°±1°
1.60 MAX.
0.05 MIN.
0.60±0.15
0° MIN.
0.25
0°-7°
(8X)
STAND-OFF
R 0.08 MIN.
TYP.
0.20 MAX.
0.15 MAX.
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
14.00±0.10
16.00±0.20
0.10
SEE DETAIL A
DETAIL
A
1
100
30
31 50
51
80
81
GAUGE PLANE
1.00 REF.
0.20 MIN.
SEATING PLANE
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
51-85050-*B
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CY7C1352G
Document #: 38-05514 Rev. *D Page 12 of 12
Document History Page
Document Title: CY7C1352G 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05514
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 224362 See ECN RKF New data sheet
*A 288431 See ECN VBL Deleted 100 MHz and 225 MHz
Changed TQFP package in Ordering Information section to lead-free TQFP
*B 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP Package as per
JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal Resis-
tance table
Added lead-free product information for 119 BGA
Updated the Ordering Information by shading and unshading MPNs as per avail-
ability
*C 419256 See ECN RXU Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified test condition from VIH < VDD to VIH < VDD
Modified test condition from VDDQ < VDD to VDDQ <VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
ReplacedPackageNamecolumnwithPackageDiagramintheOrderingInformation
table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D 480124 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Updated the Ordering Information table.
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