Cypress Semiconductor STK14C88-3 User manual

STK14C88-3
256 Kbit (32K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document Number: 001-50592 Rev. ** Revised January 29, 2009
Features
■ 35 ns and 45 ns access times
■ Automatic nonvolatile STORE on power loss
■ Nonvolatile STORE under Hardware or Software control
■ Automatic RECALL to SRAM on power up
■ Unlimited Read/Write endurance
■ Unlimited RECALL cycles
■ 1,000,000 STORE cycles
■ 100 year data retention
■ Single 3.3V+0.3V power supply
■ Commercial and Industrial Temperatures
■ 32-pin (300mil) SOIC and 32-pin (600 mil) PDIP packages
■ RoHS compliance
Functional Description
The Cypress STK14C88-3 is a 256 Kb fast static RAM with
a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
™
technology producing the world’s most reliable nonvolatile
memory. The SRAM provides unlimited read and write
cycles, while independent, nonvolatile data resides in the
highly reliable QuantumTrap cell. Data transfers from the
SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power down. On power up, data
is restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC V
CAP
A13 -A0
A0A1A2A3A4A10
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Logic Block Diagram
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 2 of 17
Pin Configurations
Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP
Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP
Pin Name Alt IO Type Description
A
0
–A
14
Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
DQ
0
-DQ
7
Input or
Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
WE WInput Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
IO pins is written to the specific address location.
CE EInput Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
OE GInput Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
V
SS
Ground Ground for the Device.The device is connected to ground of the system.
V
CC
Power Supply Power Supply Inputs to the Device.
HSB Input or
Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).
V
CAP
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile elements.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 3 of 17
Device Operation
The STK14C88-3 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The STK14C88-3 supports unlimited reads and writes similar to
atypicalSRAM.In addition,it providesunlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The STK14C88-3 performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
onpins A
0–14
determines the32,768databytes accessed.When
the READ is initiated by an address transition, the outputs are
valid after a delay of t
AA
(READ cycle 1). If the READ is initiated
by CE or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
AWRITE cycleis performedwhenever CEand WEare LOWand
HSBisHIGH. Theaddressinputsmust bestableprior toentering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common IO
pins DQ
0–7
are written into the memory if it has valid t
SD
, before
the end of a WE controlled WRITE or before the end of an CE
controlledWRITE.KeepOEHIGHduringthe entireWRITEcycle
to avoid data bus contention on common IO lines. If OE is left
LOW,internalcircuitry turns off the output buffers t
HZWE
afterWE
goes LOW.
AutoStore
®
Operation
The STK14C88-3 can be powered in one of three storage opera-
tions:
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 2 shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. A charge storage capacitor
having a capacity of between 68 uF and 220 uF (+20%) rated at
4.7V should be provided.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc
reaches V
SWITCH
, then a 1 ohm resistor should be connected
between V
CC
and the system supply to avoid momentary excess
of current between V
CC
and V
CAP
.
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then V
CC
is tied to ground and +3.3V is applied to V
CAP
(Figure 3). This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the STK14C88-3 is operated in this configuration,
references to V
CC
are changed to V
CAP
throughout this data
sheet. In this mode, STORE
operations are triggered through
software control. It is not permissible to change between these
options “On the fly”.
Figure 2. AutoStore Mode
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 4 of 17
Hardware STORE (HSB) Operation
The STK14C88-3 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used
to request a hardware STORE cycle. When the HSB pin is
driven LOW, the STK14C88-3 conditionally initiates a STORE
operation after t
DELAY
. An actual STORE cycle only begins if a
WRITE to the SRAM takes place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition, while
the STORE (initiated by any means) is in progress. Pull up this
pin with an external 10K ohm resistor to V
CAP
if HSB is used
as a driver.
SRAM READ and WRITE operations, that are in progress
when HSB is driven LOW by any means, are given time to
complete before the STORE operation is initiated. After HSB
goes LOW, the STK14C88-3 continues SRAM operations for
t
DELAY
. During t
DELAY
, multiple SRAM READ operations take
place. If a WRITE is in progress when HSB is pulled LOW, it
allows a time, t
DELAY
to complete. However, any SRAM
WRITE cycles requested after HSB goes LOW are inhibited
until HSB returns HIGH.
The HSB pin is used to synchronize multiple STK14C88-3
while using a single larger capacitor. To operate in this mode,
the HSB pin is connected together to the HSB pins from the
other STK14C88-3. An external pull up resistor to V
CAP
is
required, since HSB acts as an open drain pull down. The
V
CAP
pins from the other STK14C88-3 parts are tied together
and share a single capacitor. The capacitor size is scaled by
the number of devices connected to it. When any one of the
STK14C88-3 detects a power loss and asserts HSB, the
common HSB pin causes all parts to request a STORE
cycle.
(A STORE
takes place in those STK14C88-3 that are written
since the last nonvolatile cycle.)
During any STORE operation, regardless of how it is initiated,
the STK14C88-3 continues to drive the HSB pin LOW,
releasing it only when the STORE is complete. After
completing the STORE operation, the STK14C88-3 remains
disabled until the HSB pin returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC
<
V
RESET
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycleisautomaticallyinitiated andtakest
HRECALL
tocomplete.
If the STK14C88-3 is in a WRITE
state at the end of power up
RECALL, the SRAM
data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
CC
or between CE and system V
CC
.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory
by a software address sequence. The STK14C88-3 software
STOREcycleisinitiatedbyexecutingsequentialCE controlled
READ cycles from six specific address locations in exact
order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed followed by a program of the
nonvolatile elements. When a STORE cycle is initiated, input
and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If they
intervene, thesequence isaborted andno STOREorRECALL
takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the
STORE cycle commences and the chip is disabled. It is
important that READ cycles and not WRITE cycles are used
in the sequence. It is not necessary that OE is LOW for a valid
sequence. After the t
STORE
cycle time is fulfilled, the SRAM is
again activated for READ and WRITE operation.
Figure 3. AutoStore Inhibit Mode
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 5 of 17
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with asequenceof READoperations ina manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALLisa two stepprocedure. First,theSRAM data
is cleared, and then the nonvolatile informationistransferredinto
the SRAM cells. After the t
RECALL
cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements.The
nonvolatile data can be recalled an unlimited number of times.
Preventing STORE
The STORE function can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a V
OH
of at least
2.2V, because it has to overpower the internal pull down device.
This device drives HSB LOW for 20 μs at the onset of a STORE.
When the STK14C88-3 is connected for AutoStore operation
(system V
CC
connected to V
CC
and a 68 μF capacitor on V
CAP
)
and V
CC
crosses V
SWITCH
on the way down, the STK14C88-3
attempts to pull HSB LOW. If HSB does not actually get below
V
IL
, the part stops trying to pull HSB LOW and aborts the STORE
attempt.
Hardware Protect
The STK14C88-3 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage condi-
tions. When V
CAP
<V
SWITCH
, all externally initiated STORE
operations and SRAM WRITEs are inhibited.
Noise Considerations
The STK14C88-3 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS,
using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the STK14C88-3 the benefit of
drawing significantly lesscurrent when itis cycledat times longer
than 50 ns. Figure 4 and Figure 5 show the relationship between
I
CC
and READ or WRITE cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 3.6V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK14C88-3
depends on the following items:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The V
CC
level
7. IO loading
Figure 4. Current Versus Cycle Time (READ)
Figure 5. Current Versus Cycle Time (WRITE)
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 6 of 17
Best Practices
nvSRAM products have been used effectively for over 15
years. While ease-of-use is one of the product’s main system
values, experience gained working with hundreds of applica-
tions has resulted in the following suggestions as best
practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites,sometimes,reprogramthesevalues.FinalNVpatterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in
a set programmed state. Routines that check memory
content values to determine first time system configuration
and cold or warm boot status, should always program a
unique NV pattern (for example, a complex 4-byte pattern of
46 E6 49 53 hex or more random bytes) as part of the final
system manufacturing test to ensure these system routines
work consistently. Power up boot firmware routines should
rewrite the nvSRAM into the desired state. While the
nvSRAMisshippedinapresetstate,bestpracticeistoagain
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs or incoming inspection routines).
■ The V
CAP
value specified in this data sheet includes a
minimumandamaximumvaluesize.Bestpracticeistomeet
this requirement and not exceed the max V
CAP
value
becausethe higher inrush currentsmayreduce the reliability
of the internal pass transistor. Customers who want to use a
larger V
CAP
value to ensure there is extra store charge
should discuss their V
CAP
size selection with Cypress to
understand any impact on the V
CAP
voltage level at the end
of a t
RECALL
period.
Table 2. Hardware Mode Selection
CE WE HSB A
13
– A
0
Mode IO Power
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active
[1]
L L H X Write SRAM Input Data Active
X X L X Nonvolatile Store Output High Z I
CC2[2]
LHH0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[1, 3, 4, 5]
LHH0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[1, 3, 4, 5]
Notes
1. I/O state assumes OE < V
IL
. Activation of nonvolatile cycles does not depend on state of OE.
2. HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go
into standby mode, inhibiting all operations until HSB rises.
3. CE and OE LOW and WE HIGH for output behavior.
4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
5. While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 7 of 17
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Temperature under bias.............................. –55°C to +125°C
Supply Voltage on V
CC
Relative to GND..........–0.5V to 7.0V
Voltage on Input Relative to Vss............–0.6V to V
CC
+ 0.5V
Voltage on DQ
0-7
or HSB .......................–0.5V to Vcc + 0.5V
Power Dissipation .........................................................1.0W
DC output Current (1 output at a time, 1s duration) ....15 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0°C to +70°C 3.0V to 3.6V
Industrial -40°C to +85°C 3.0V to 3.6V
DC Electrical Characteristics
Over the operating range (V
CC
= 3.0V to 3.6V)
[6]
Parameter Description Test Conditions Min Max Unit
I
CC1
Average V
CC
Current t
RC
= 35 ns
t
RC
= 45 ns
Dependentonoutputloadingandcyclerate.Values
obtained without output loads.
I
OUT
= 0 mA.
Commercial 50
42 mA mA
Industrial 52
44 mA mA
I
CC2
Average V
CC
Current
during STORE All Inputs Do Not Care, V
CC
= Max
Average current for duration t
STORE
3mA
I
CC3
Average V
CC
Current
at t
RC
= 200 ns, 5V,
25°C Typical
WE > (V
CC
– 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. Values obtained without
output loads.
9mA
I
CC4
AverageV
CAP
Current
during AutoStore
Cycle
All Inputs Do Not Care, V
CC
= Max
Average current for duration t
STORE
2mA
I
SB1[7]
Average V
CC
Current
(Standby, CyclingTTL
Input Levels)
t
RC
=35ns, CE > V
IH
t
RC
=45ns, CE > V
IH
Commercial 18
16 mA
Industrial 19
17 mA
I
SB2[7]
V
CC
Standby Current
(Standby, Stable
CMOS Input Levels)
CE > (V
CC
– 0.2V). All others V
IN
<0.2V or > (V
CC
– 0.2V). 1 mA
I
IX
InputLeakage Current V
CC
= Max, V
SS
< V
IN
<V
CC
-1 +1 μA
I
OZ
Off State Output
Leakage Current V
CC
= Max, V
SS
< V
IN
<V
CC
, CE or OE > V
IH
or WE < V
IL
-1 +1 μA
V
IH
Input HIGH Voltage 2.2 V
CC
+
0.5 V
V
IL
Input LOW Voltage V
SS
–
0.5 0.8 V
V
OH
Output HIGH Voltage I
OUT
= –4 mA except HSB 2.4 V
V
OL
Output LOW Voltage I
OUT
= 8 mA except HSB 0.4 V
V
BL
Logic ‘0’ Voltage on
HSB output I
OUT
= 3 mA 0.4 V
V
CAP
Storage Capacitor Between V
CAP
pin and Vss, 68 to 220uF +20%, 4.7V rated. 54 264 uF
Notes
6. V
CC
reference levels throughout this data sheet refer to V
CC
if that is where the power supply connection is made, or V
CAP
if V
CC
is connected to ground.
7. CE > V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 8 of 17
Data Retention and Endurance
Parameter Description Min Unit
DATA
R
Data Retention 100 Years
NV
C
Nonvolatile STORE Operations 1,000 K
Capacitance
In the following table, the capacitance parameters are listed.
[8]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 0 to 3.0 V 5pF
C
OUT
Output Capacitance 7 pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
[8]
Parameter Description Test Conditions 32-SOIC 32-PDIP Unit
Θ
JA
Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and proceduresformeasuring thermalimpedance,per
EIA / JESD51.
TBD TBD °C/W
Θ
JC
Thermal Resistance
(Junction to Case) TBD TBD °C/W
Figure 6. AC Test Loads
AC Test Conditions
3.3V
Output
30 pF
R1 317Ω
R2
351Ω
Input Pulse Levels..................................................0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels................... 1.5 V
Note
8. These parameters are guaranteed by design and are not tested.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 9 of 17
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 35 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
t
ACE
t
ELQV
Chip Enable Access Time 35 45 ns
t
RC [9]
t
AVAV,
t
ELEH
Read Cycle Time 35 45 ns
t
AA [10]
t
AVQV
Address Access Time 35 45 ns
t
DOE
t
GLQV
Output Enable to Data Valid 15 20 ns
t
OHA [10]
t
AXQX
Output Hold After Address Change 5 5 ns
t
LZCE [11]
t
ELQX
Chip Enable to Output Active 5 5 ns
t
HZCE [11]
t
EHQZ
Chip Disable to Output Inactive 13 15 ns
t
LZOE [11]
t
GLQX
Output Enable to Output Active 0 0 ns
t
HZOE [11]
t
GHQZ
Output Disable to Output Inactive 13 15 ns
t
PU [8]
t
ELICCH
Chip Enable to Power Active 0 0 ns
t
PD [8]
t
EHICCL
Chip Disable to Power Standby 35 45 ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled
[9, 10]
Figure 8. SRAM Read Cycle 2: CE and OE Controlled
[9]
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Notes
9. WE and HSB must be HIGH during SRAM Read Cycles.
10.I/O state assumes CE and OE < V
IL
and WE > V
IH
; device is continuously selected.
11. Measured ±200 mV from steady state output voltage.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 10 of 17
Table 3. SRAM Write Cycle
Parameter Description 35 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
t
WC
t
AVAV
Write Cycle Time 35 45 ns
t
PWE
t
WLWH,
t
WLEH
Write Pulse Width 25 30 ns
t
SCE
t
ELWH,
t
ELEH
Chip Enable To End of Write 25 30 ns
t
SD
t
DVWH,
t
DVEH
Data Setup to End of Write 12 15 ns
t
HD
t
WHDX,
t
EHDX
Data Hold After End of Write 0 0 ns
t
AW
t
AVWH,
t
AVEH
Address Setup to End of Write 25 30 ns
t
SA
t
AVWL,
t
AVEL
Address Setup to Start of Write 0 0 ns
t
HA
t
WHAX,
t
EHAX
Address Hold After End of Write 0 0 ns
t
HZWE [11,12]
t
WLQZ
Write Enable to Output Disable 13 15 ns
t
LZWE [11]
t
WHQX
Output Active After End of Write 5 5 ns
Switching Waveforms
Figure 9. SRAM Write Cycle 1: WE Controlled
[13, 14]
Figure 10. SRAM Write Cycle 2: CE Controlled
[13, 14]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
12.If WE is Low when CE goes Low, the outputs remain in the high impedance state.
13.CE or WE must be greater than V
IH
during address transitions.
14.HSB must be HIGH during SRAM WRITE cycles.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 11 of 17
AutoStore or Power Up RECALL
Parameter Alt Description STK14C88-3 Unit
Min Max
t
HRECALL [15]
t
RESTORE
Power up RECALL Duration 550 μs
t
STORE [16, 17]
t
HLHZ
STORE Cycle Duration 10 ms
t
VSBL[16]
Low Voltage Trigger (V
SWITCH
) to HSB low 300 ns
V
RESET
Low Voltage Reset Level 2.4 V
V
SWITCH
Low Voltage Trigger Level 2.7 2.95 V
t
DELAY[16]
t
BLQZ
Time Allowed to Complete SRAM Cycle 1 μs
Switching Waveforms
Figure 11. AutoStore/Power Up RECALL
WE
Notes
15.t
HRECALL
starts from the time V
CC
rises above V
SWITCH
.
16.CE and OE low and WE high for output behavior.
17.HSB is asserted low for 1us when V
CAP
drops through V
SWITCH
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no
store will take place.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 12 of 17
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
[18, 19]
Parameter Alt Description 35 ns 45 ns Unit
Min Max Min Max
t
RC[16]
t
AVAV
STORE/RECALL Initiation Cycle Time 35 45 ns
t
SA[18, 19]
t
AVEL
Address Setup Time 0 0 ns
t
CW[18, 19]
t
ELEH
Clock Pulse Width 25 30 ns
t
HACE[18, 19]
t
ELAX
Address Hold Time 20 20 ns
t
RECALL
RECALL Duration 20 20 μs
Switching Waveforms
Figure 12. CE Controlled Software STORE/RECALL Cycle
[19]
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
18.The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).
19.The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 13 of 17
Hardware STORE Cycle
Parameter Alt Description STK14C88-3 Unit
Min Max
t
PHSB
t
HLHX
Hardware STORE Pulse Width 15 ns
t
DHSB [16, 20]
t
RECOVER,
t
HHQX
Hardware STORE High to Inhibit Off 700 ns
t
HLBL
Hardware STORE Low to STORE Busy 300 ns
Switching Waveforms
Figure 13. Hardware STORE Cycle
3+6%
Note
20.t
DHSB
is only applicable after t
STORE
is complete.
[+] Feedback

STK14C88-3
Document Number: 001-50592 Rev. ** Page 14 of 17
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
35 STK14C88-3NF35TR 51-85127 32-pin SOIC Commercial
STK14C88-3NF35 51-85127 32-pin SOIC
STK14C88-3WF35 51-85018 32-pin PDIP
STK14C88-3NF35ITR 51-85127 32-pin SOIC Industrial
STK14C88-3NF35I 51-85127 32-pin SOIC
STK14C88-3WF35I 51-85018 32-pin PDIP
45 STK14C88-3NF45TR 51-85127 32-pin SOIC Commercial
STK14C88-3NF45 51-85127 32-pin SOIC
STK14C88-3WF45 51-85018 32-pin PDIP
STK14C88-3NF45ITR 51-85127 32-pin SOIC Industrial
STK14C88-3NF45I 51-85127 32-pin SOIC
STK14C88-3WF45I 51-85018 32-pin PDIP
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
Packaging Option:
TR = Tape and Reel
Blank = Tube
Speed:
35 - 35 ns
45 - 45 ns
Package:
N = Plastic 32-pin 300 mil SOIC
Part Numbering Nomenclature
STK14C88- 3N F 45 I TR
Temperature Range:
Blank - Commercial (0 to 70°C)
W
= Plastic 32-pin 600 mil DIP
Lead Finish
F = 100% Sn (Matte Tin)
I - Industrial (-40 to 85°C)
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STK14C88-3
Document Number: 001-50592 Rev. ** Page 15 of 17
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
51-85058 *A
PIN 1 ID
SEATING PLANE
116
17 32
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.292[7.416]
0.299[7.594]
0.405[10.287]
0.419[10.642]
0.050[1.270]
TYP.
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.0100[0.254]
0.006[0.152]
0.012[0.304]
0.021[0.533]
0.041[1.041]
0.026[0.660]
0.032[0.812]
0.004[0.101]
REFERENCE JEDEC MO-119
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
0.014[0.355]
0.020[0.508]
0.810[20.574]
0.822[20.878]
51-85127-*A
[+] Feedback

STK14C88-3
Document Number: 001-50592 Rev. ** Page 16 of 17
Figure 15. 32-Pin (600 Mil) PDIP (51-85018)
Package Diagrams (continued)
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51-85018-*A
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Document Number: 001-50592 Rev. ** Revised January 29, 2009 Page 17 of 17
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective
holders.
STK14C88-3
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components inlife-support systems where a malfunctionor failure may reasonably be expected toresult in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to beused only inconjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specifiedabove is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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USB psoc.cypress.com/usb
Document Title: STK14C88-3 256 Kbit (32K x 8) AutoStore nvSRAM
Document Number: 001-50592
Rev. ECN No. Orig. of
Change Submission Date Description of Change
** 2625096 GVCH/PYRS 12/19/08 New data sheet
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