Cypress Semiconductor NoBL CY7C1470BV25 User manual

72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-15032 Rev. *D Revised February 29, 2008
Features
■Pin-compatible and functionally equivalent to ZBT™
■Supports 250 MHz bus operations with zero wait states
❐Available speed grades are 250, 200, and 167 MHz
■Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■Fully registered (inputs and outputs) for pipelined operation
■Byte Write capability
■Single 2.5V power supply
■2.5V IO supply (VDDQ)
■Fast clock-to-output times
❐3.0 ns (for 250-MHz device)
■Clock Enable (CEN) pin to suspend operation
■Synchronous self-timed writes
■CY7C1470BV25, CY7C1472BV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV25
available in Pb-free and non-Pb-free 209-ball FBGA package
■IEEE 1149.1 JTAG Boundary Scan compatible
■Burst capability—linear or interleaved burst order
■“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back read
or write operations with no wait states. The CY7C1470BV25,
CY7C1472BV25, and CY7C1474BV25 are equipped with the
advanced (NoBL) logic required to enable consecutive read or
write operations with data beingtransferred on everyclock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent read or write transitions. The
CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWdfor CY7C1470BV25, BWa–BWbfor
CY7C1472BV25, and BWa–BWhfor CY7C1474BV25) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description 250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 3.0 3.0 3.4 ns
Maximum Operating Current 450 450 400 mA
Maximum CMOS Standby Current 120 120 120 mA
[+] Feedback

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 2 of 29
Logic Block Diagram – CY7C1470BV25 (2M x 36)
Logic Block Diagram – CY7C1472BV25 (4M x 18)
A0, A1, A
C
MODE
BW a
BW b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQ
s
DQ
P a
DQ
P
b
DQ
P c
DQ
P
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
C
LK
C
EN
WRITE
DRIVERS
BW c
BW d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
A0, A1, A
C
MODE
BW
a
BW b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQ
s
DQ
P
a
DQ
P b
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
C
LK
C
EN
WRITE
DRIVERS
ZZ Sleep
Control
[+] Feedback

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 3 of 29
Logic Block Diagram – CY7C1474BV25 (1M x 72)
A0, A1, A
C
MODE
CE1
CE2
CE3
OE
READ LOGIC
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
BW a
BW b
WE
ZZ
Sleep
Control
BW
c
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW d
BW
e
BW f
BW
g
BW
h
[+] Feedback

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 4 of 29
Pin Configurations
A A A A
A1
A0
VSS
VDD
A
A A A A
A
VDDQ
VSS
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
DQa
DQa
VDDQ
VSS
DQa
DQa
VSS
VDDQ
VDDQ
VSS
DQc
DQc
VSS
VDDQ
DQc
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
VSS
VDDQ
A A
CE1
CE2 BWa CE3 VDD VSS
CLK WE CEN OE
A A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AA
ADV/LD
ZZ
CY7C1470BV25
A
A A A
A1
A0
VSS
VDD
A
A
A A A
A
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
VDD
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
A A
CE1
CE2
NC NC
BWb
BWa CE3
VDD VSS
CLK WE CEN OE
A A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AA
ADV/LD
ZZ
MODE
CY7C1472BV25
BWd
MODE
BWc
DQc
DQc
DQc
DQc
DQPc
DQd
DQd
DQd
DQPb
DQb
DQa
DQa
DQa
DQa
DQPa
DQb
DQb
(2M × 36) (4M × 18)
BWb
NC
NC
NC
DQc NC
NC(288)
NC(144)
NC(288)
NC(144)
DQPd
A
A
A
A
A
A
Figure 1. 100-Pin TQFP Pinout
[+] Feedback

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 5 of 29
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1470BV25 (2M x 36)
CY7C1472BV25 (4M x 18)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
DQPc
DQc
DQPd
NC
DQd
ACE1BWbCE3
BWcCEN
ACE2
DQc
DQd
DQd
MODE
NC
DQc
DQc
DQd
DQd
DQd
A
VDDQ
BWdBWaCLK WE
VSS VSS VSS VSS
VDDQ VSS
VDD VSS VSS
VSS
NC
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD VSS
VDD VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCKA0
VSS TDI
A
A
DQcVSS
DQcVSS
DQc
DQcNC VSS VSS
VSS VSS
NC
VSS
A1
DQdDQd
NC/144M NC
VDDQ
VSS
TMS
891011
NC/288M
AAADV/LD NC
OE AANC
VSS VDDQ NC DQPb
VDDQ
VDD DQbDQb
DQb
NC
DQb
NC
DQa
DQa
VDD VDDQ
VDD VDDQ DQb
VDD NC
VDD DQa
VDD VDDQ DQa
VDDQ
VDD
VDD VDDQ
VDD VDDQ DQa
VDDQ
AA
VSS A
A
A
DQb
DQb
DQbZZ
DQaDQa
DQPa
DQa
A
VDDQ
A
A
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
NC
NC
DQPb
NC
DQb
ACE1CE3
BWbCEN
ACE2
NC
DQb
DQb
MODE
NC
DQb
DQb
NC
NC
NC
A
VDDQ
BWaCLK WE
VSS VSS VSS VSS
VDDQ VSS
VDD VSS VSS
VSS
NC
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD VSS
VDD VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCKA0
VSS TDI
A
A
DQbVSS
NC VSS
DQb
NC NC VSS VSS
VSS VSS
NC
VSS
A1
DQbNC
NC/144M NC
VDDQ
VSS
TMS
891011
NC/288M
AA
ADV/LD A
OE AANC
VSS VDDQ NC DQPa
VDDQ
VDD NC DQa
DQa
NC
NC
NC
DQa
NC
VDD VDDQ
VDD VDDQ DQa
VDD NC
VDD NCVDD VDDQ DQa
VDDQ
VDD
VDD VDDQ
VDD VDDQ NC
VDDQ
AA
VSS A
A
A
DQa
NC
NC ZZ
DQaNC
NC
DQa
A
VDDQ
A
A
NC
NC
[+] Feedback

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 6 of 29
Pin Configurations (continued)
CY7C1474BV25 (1M × 72)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
123456789 1110
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
NC
DQPg
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQPd
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
NC
DQPf
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQPa
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
AAAA
NC NC
NC/144M
A A NC/288M
AAA
AA AA1
A0
AAA
AA
A
NC/576M
NC
NC
NC NC
NC
BWSbBWSf
BWSeBWSa
BWScBWSg
BWSd BWSh
TMS TDI TDO TCK
NC
NC MODE NC
CEN VSS
NC
CLK NC VSS
VDD VDD VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS VSS
VSS
VSS
VSS
VSS VSS
VSS
NC/1G
VDD
NC
OE
CE3
CE1
CE2ADV/LD
WE
VSS
VSS
VSS
VSS VSS VSS VSS
ZZ
VSS VSS VSS VSS
NC
VDDQ
VSS
VSS NC VSS VSS
VSS VSS VSS VSS
NC
VSS
VDDQ VDDQ VDDQ VDDQ
VDDQ NC VDDQ VDDQ
VDDQ VDDQ NC VDDQ VDDQ
VDDQ VDDQ NC VDDQ VDDQ
VDDQ
VDDQ
VDDQ VDDQ
VDDQ VDDQ VDDQ VDDQ
[+] Feedback

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 7 of 29
Table 1. Pin Definitions
Pin Name IO Type Pin Description
A0
A1
A
Input-
Synchronous Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK.
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
Input-
Synchronous Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWacontrols DQa and DQPa, BWbcontrols DQb and DQPb, BWccontrols
DQcand DQPc, BWdcontrols DQd and DQPd, BWecontrols DQe and DQPe, BWfcontrols DQf and
DQPf, BWgcontrols DQg and DQPg, BWhcontrols DQh and DQPh.
WE Input-
Synchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD Input-
Synchronous Advance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device foran access. Afterbeing deselected, ADV/LD must be driven
LOW to load a new address.
CLK Input-
Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
CE1Input-
Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2and CE3to select/deselect the device.
CE2Input-
Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1and CE3to select/deselect the device.
CE3Input-
Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.
OE Input-
Asynchronous OutputEnable,ActiveLOW.Combinedwiththesynchronouslogicblockinsidethedevicetocontrol the direction of the IO pins. When LOW, the IO pins can behave as outputs. When deasserted HIGH,
IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has
been deselected.
CEN Input-
Synchronous Clock Enable Input,ActiveLOW.Whenasserted LOWthe clocksignalis recognizedbythe SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
DQsIO-
Synchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[18:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by
OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQhare placed in a tri-state condition. The outputs are automatically tri-stated during
the data portion ofa write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE.
DQPXIO-
Synchronous BidirectionalDataParity IO Lines.Functionally, thesesignalsare identical toDQ[71:0].Duringwrite sequences, DQPais controlled by BWa, DQPbis controlled by BWb, DQPcis controlled by BWc, and
DQPdiscontrolledbyBWd,DQPeiscontrolled byBWe,DQPfiscontrolledbyBWf,DQPgiscontrolled
by BWg, DQPhis controlled by BWh.
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE must not change states during operation. When
left floating MODE defaults HIGH, to an interleaved burst order.
TDO JTAG Serial
Output
Synchronous
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
TDI JTAG Serial Input
Synchronous Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
[+] Feedback

CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 8 of 29
Functional Overview
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
are synchronous-pipelined Burst NoBL SRAMs designed specif-
ically to eliminate wait states during read or write transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
ClockEnable inputsignal (CEN).IfCENisHIGH, theclock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 3.0 ns
(250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). BW[x] can be used to conduct Byte Write opera-
tions.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the input signal WE is
deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
Address Register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW to drive out the requested
data. During the second clock, a subsequent operation (read,
write, or deselect) can be initiated. Deselecting the device is also
pipelined. Therefore, when the SRAM is deselected at clock rise
by one of the chip enable signals, its output tri-states following
the next clock rise.
Burst Read Accesses
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the Single Read
Accesses section. The sequence of the burst counter is deter-
mined by the MODE input signal. A LOW input on MODE selects
a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the Address Register. The write signals are latched
into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV25, DQa,b/DQPa,b for
CY7C1472BV25, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV25). In addition, the address for the subsequent
TMS Test Mode Select
Synchronous TMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
TCK JTAG Clock Clock Input to the JTAG Circuitry.
VDD Power Supply Power Supply Inputs to the Core of the Device.
VDDQ IO Power Supply Power Supply for the IO Circuitry.
VSS Ground Ground for the Device. Must be connected to ground of the system.
NC – No Connects. This pin is not connected to the die.
NC(144M,
288M,
576M, 1G)
–These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G
densities.
ZZ Input-
Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. For normal operation, this pin has must be LOW or left floating.
ZZ pin has an internal pull down.
Table 1. Pin Definitions (continued)
Pin Name IO Type Pin Description
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CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 9 of 29
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV25, DQa,b/DQPa,b for
CY7C1472BV25, DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV25) (or a subset for Byte Write operations, see
“Partial Write Cycle Description” on page 11 for details) inputs is
latched into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1470BV25, BWa,b for CY7C1472BV25, and
BWa,b,c,d,e,f,g,h for CY7C1474BV25) signals. The
CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
provides Byte Write capability that is described in “Partial Write
Cycle Description” on page 11. Asserting the WE input with the
selected BW input selectively writes to only the desired bytes.
Bytes not selected during a Byte Write operation remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte Write capability
has been included to greatly simplify read, modify, or write
sequences, which can be reduced to simple Byte Write opera-
tions.
Because the CY7C1470BV25, CY7C1472BV25, and
CY7C1474BV25 are common IO devices, data must not be
driven into the device while the outputs are active. OE can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV25, DQa,b/DQPa,b for
CY7C1472BV25, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV25) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1470BV25, DQa,b/DQPa,b for CY7C1472BV25, and
DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV25) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in “Single Write Accesses”
on page 8. When ADV/LD is driven HIGH on the subsequent
clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs
are ignored and the burst counter is incremented. The correct
BW (BWa,b,c,d for CY7C1470BV25, BWa,b for CY7C1472BV25,
and BWa,b,c,d,e,f,g,h for CY7C1474BV25) inputs must be driven
in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pendingwhenentering the“sleep”modearenotconsideredvalid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Table 2. Linear Burst Address Table (MODE = GND)
First
Address Second Address Third Address Fourth Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Table 3. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address Second Address Third Address Fourth Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ >VDD − 0.2V 120 mA
tZZS Device operation to ZZ ZZ > VDD −0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns
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CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D Page 10 of 29
Table 4. Truth Table
The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. [1, 2, 3, 4, 5, 6, 7]
Operation Address
Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle
(Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle
(Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read
(Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read
(Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle
(Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle
(Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/Write Abort
(Begin Burst) None L L L L H X L L-H Tri-State
Write Abort
(Continue Burst) Next X L H X H X L L-H Tri-State
Ignore Clock Edge (Stall) Current X L X X X X H L-H –
Sleep Mode None X H X X X X X X Tri-State
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx= L signifies at least one Byte Write Select is active, BWx= Valid
signifies that the desired Byte Write Selects are asserted, see “Partial Write Cycle Description” on page 11 for details.
2. Write is defined by WE and BW[a:d]. See “Partial Write Cycle Description” on page 11 for details.
3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQsand DQP[a:d] = tri-state when OE is
inactive or when the device is deselected, and DQs = data when OE is active.
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