Cypress CY62128B User manual

1-Mbit (128K x 8) Static RAM
CY62128B
MoBL®
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-05300 Rev. *C Revised March 7, 2005
Features
• Temperature Ranges
—Commercial: 0°C to 70°C
—Industrial: –40°C to 85°C
—Automotive: –40°C to 125°C
• 4.5V–5.5V operation
• CMOS for optimum speed/power
• Low active power
(70 ns, LL version, Commercial, Industrial)
—82.5 mW (max.) (15 mA)
• Low standby power
(70 ns, LL version, Commercial, Industrial)
—110µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• EasymemoryexpansionwithCE1,CE2,andOEoptions
Functional Description[1]
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1),
an active HIGH Chip Enable (CE2), an active LOW Output
Enable (OE), and three-state drivers. This device has an
automatic power-down feature that reduces power
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE1) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0through A16).
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2LOW), the outputs are disabled (OE HIGH), or
duringawrite operation (CE1LOW,CE2HIGH,andWELOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
14 15
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE2
I/O1
I/O2
I/O3
512x256x8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13 A12
A A10
CE1
A A16
A9
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CY62128B
MoBL®
Document #: 38-05300 Rev. *C Page 2 of 11
Pin Configurations
Product Portfolio
Product VCC Range (V) Speed (ns)
Power Dissipation
Operating, ICC
(mA) Standby, ISB2 (µA)
Min. Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.
CY62128BLL Industrial 4.5 5.0 5.5 55 7.5 20 2.5 15
Industrial 70 6 15 2.5 15
Automotive 70 6 25 2.5 25
Pin Definitions
Input A0-A16. Address Inputs
Input/Output I/O0-I/O7. Data lines. Used as input or output lines depending on operation
Input/Control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ
is conducted.
Input/Control CE1. Chip Enable 1, Active LOW.
Input/Control CE2. Chip Enable 2, Active HIGH.
Input/Control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
Ground GND. Ground for the device
Power Supply VCC. Power supply for the device
Note:
2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production
variations as measured at VCC = 5.0V, TA= 25°C, and tAA = 70 ns.
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
12
13
29
32
31
30
16
15 17 18
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O
7
I/O
6
I/O
5
I/O
4
A2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A10
I/O
3
A1
A0
A11
CE
2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
SOIC
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
Reverse TSOP I
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
(not to scale)
Top View
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
STSOP
Top View
(not to scale)
25
30
26
27
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A59
10
32
1
2
3
4
5
6
7
8
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
25
GN
gnc
G
g
GND
I/O6
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CY62128B
MoBL®
Document #: 38-05300 Rev. *C Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] ....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[3]....................................–0.5V to VCC + 0.5V
DC Input Voltage[3].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient Temperature (TA)[4] VCC
Commercial 0°C to +70°C 5V ±10%
Industrial –40°C to +85°C5V±10%
Automotive –40°C to +125°C5V±10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions CY62128B-55 CY62128B-70 Unit
Min. Typ.[2] Max. Min. Typ.[2] Max.
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+ 0.3 2.2 VCC + 0.3 V
VIL Input LOW Voltage[3] –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND ≤VI≤VCC –1 +1 –1 +1 µA
Automotive –10 +10 µA
IOZ Output Leakage
Current GND ≤VI ≤VCC, Output Disabled –1 +1 –1 +1 µA
Automotive –10 +10 µA
IOS Output Short Circuit
Current[5] VCC = Max., VOUT = GND –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
Industrial,
Commercial 7.5 20 6 15 mA
Automotive 625mA
ISB1 Automatic CE
Power-down Current
—TTL Inputs
Max. VCC,
CE1≥VIH
or CE2< VIL,
VIN ≥VIH or
VIN ≤VIL, f = fMAX
Industrial
Commercial 0.1 20.11mA
Automotive 0.1 2 mA
ISB2 Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE1≥VCC – 0.3V,
or CE2≤0.3V,
VIN ≥VCC – 0.3V,
or VIN ≤0.3V, f = 0
Industrial
Commercial 2.5 15 2.5 15 µA
Automotive 2.5 25 µA
Notes:
3. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
4. TAis the “Instant On” case temperature.
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
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CY62128B
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Document #: 38-05300 Rev. *C Page 4 of 11
Thermal Resistance[6]
Parameter Description Test Conditions 32 SOIC 32 TSOP 32 STSOP 32 RTSOP Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and procedures for
measuring thermal impedance, per
EIA / JESD51.
66.17 97.44 105.14 97.44 °C/W
ΘJC Thermal Resistance
(Junction to Case) 30.87 26.05 14.09 26.05 °C/W
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 5.0V 9pF
COUT Output Capacitance 9 pF
AC Test Loads and Waveforms
90%
10%
VCC
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT 100 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R1 1800ΩR1 1800Ω
R2
990 R2 990Ω
639Ω
Equivalent to: THÉVENIN EQUIVALENT
1.77V
Rise TIme:
1 V/ns Fall TIme
:
1 V/ns
Ω
Data Retention Waveform
Data Retention Characteristics (Over the Operating Range for “LL” version only)
Parameter Description Conditions Min. Typ. Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V, CE1≥ VCC – 0.3V,
or CE2≤0.3V, VIN ≥VCC – 0.3V or, VIN ≤
0.3V
1.5 15 µA
tCDR Chip Deselect to Data Retention
Time 0ns
tROperation Recovery Time 70 ns
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
VCC, min.
VCC, min.
tCDR VDR >2 V
DATA RETENTION MODE
tR
CE1
VCC
CE2
or
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CY62128B
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Document #: 38-05300 Rev. *C Page 5 of 11
Switching Characteristics[7] Over the Operating Range
Parameter Description
62128B-55 62128B-70
UnitMin. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5 ns
tACE CE1LOW to Data Valid, CE2HIGH to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 20 35 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[7, 9] 20 25 ns
tLZCE CE1LOW to Low Z, CE2HIGH to Low Z[9] 55ns
tHZCE CE1HIGH to High Z, CE2LOW to High Z[8, 9] 20 25 ns
tPU CE1LOW to Power-up, CE2HIGH to Power-up 0 0 ns
tPD CE1HIGH to Power-down, CE2LOW to Power-down 55 70 ns
WRITE CYCLE[10]
tWC Write Cycle Time 55 70 ns
tSCE CE1LOW to Write End, CE2HIGH to Write End 45 60 ns
tAW Address Set-up to Write End 45 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Width 45 50 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[9] 55ns
tHZWE WE LOW to High Z[8, 9] 20 25 ns
Switching Waveforms
Read Cycle No.1[12, 13]
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. The internal write time of the memory is defined by the overlap of CE1LOW, CE2HIGH, and WE LOW. CE1and WE must be LOW and CE2HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
11. No input may exceed VCC + 0.5V.
12. Device is continuously selected. OE, CE1= VIL, CE2= VIH.
13. WE is HIGH for read cycle.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
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CY62128B
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Document #: 38-05300 Rev. *C Page 6 of 11
Read Cycle No. 2 (OE Controlled)[13, 14]
Write Cycle No. 1 (CE1or CE2Controlled)[15, 16]
Notes:
14. Address valid prior to or coincident with CE1transition LOW and CE2transition HIGH.
15. Data I/O is high impedance if OE= VIH.
16. If CE1goes HIGH or CE2goes LOW simultaneously with WE going HIGH, the outputremains in a high-impedance state.
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
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Document #: 38-05300 Rev. *C Page 7 of 11
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]
Write Cycle No.3 (WE Controlled, OE LOW)[15, 16]
Note:
17. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tSCE
tWC
tHZOE
DATAINVALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE 17
DATA VALID
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tSCE
tWC
tHZWE
CE1
ADDRESS
CE2
WE
DATAI/O NOTE 17
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CY62128B
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Document #: 38-05300 Rev. *C Page 8 of 11
Truth Table
CE1CE2OE WE I/O0–I/O7Mode Power
H X X X High Z Power-down Standby (ISB)
X L X X High Z Power-down Standby (ISB)
LHLHDataOut Read Active(I
CC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed (ns) Ordering Code Package Name Package Type Operating Range
55 CY62128BLL-55SI S34 32-Lead 450-Mil SOIC Industrial
CY62128BLL-55SXI S34 32-Lead 450-Mil SOIC (Pb-Free) Industrial
CY62128BLL-55SC S34 32-Lead 450-Mil SOIC Commercial
CY62128BLL-55SXC S34 32-Lead 450-Mil SOIC (Pb-Free) Commercial
CY62128BLL-55ZI Z32 32-Lead TSOP Type I Industrial
CY62128BLL-55ZXI Z32 32-Lead TSOP Type I (Pb-Free) Industrial
CY62128BLL-55ZAI ZA32 32-Lead STSOP Type I Industrial
CY62128BLL-55ZAXI ZA32 32-Lead STSOP Type I (Pb-Free) Industrial
CY62128BLL-55ZRI ZR32 32-Lead Reverse TSOP Type I Industrial
70 CY62128BLL-70SI S34 32-Lead 450-Mil SOIC I Industrial
CY62128BLL-70SXI S34 32-Lead 450-Mil SOIC I (Pb-Free) Industrial
CY62128BLL-70SC S34 32-Lead 450-Mil SOIC I Commercial
CY62128BLL-70SXC S34 32-Lead 450-Mil SOIC I (Pb-Free) Commercial
CY62128BLL-70SE S34 32-Lead 450-Mil SOIC I Automotive
CY62128BLL-70SXE S34 32-Lead 450-Mil SOIC I (Pb-Free) Automotive
CY62128BLL-70ZI Z32 32-Lead TSOP Type I Industrial
CY62128BLL-70ZC Z32 32-Lead TSOP Type I Commercial
CY62128BLL-70ZE Z32 32-Lead TSOP Type I Automotive
CY62128BLL-70ZXE Z32 32-Lead TSOP Type I (Pb-Free) Automotive
CY62128BLL-70ZAI ZA32 32-Lead STSOP Type I Industrial
CY62128BLL-70ZAXI ZA32 32-Lead STSOP Type I (Pb-Free) Industrial
CY62128BLL-70ZAE ZA32 32-Lead STSOP Type I Automotive
CY62128BLL-70ZAXE ZA32 32-Lead STSOP Type I (Pb-Free) Automotive
CY62128BLL-70ZRXE ZR32 32-Lead Reverse TSOP Type I (Pb-Free) Automotive
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CY62128B
MoBL®
Document #: 38-05300 Rev. *C Page 9 of 11
Package Diagrams
0.546[13.868]
0.440[11.176]
0.101[2.565]
0.050[1.270]
0.014[0.355]
0.118[2.997]
0.004[0.102]
0.047[1.193]
0.006[0.152]
0.023[0.584]
0.793[20.142]
0.450[11.430]
0.566[14.376]
0.111[2.819]
0.817[20.751]
BSC.
0.020[0.508]
MIN.
MAX.
0.012[0.304]
0.039[0.990]
0.063[1.600]
SEATING PLANE
116
17 32
0.004[0.102]
32-Lead (450 MIL) Molded SOIC S34
51-85081-*B
51-85056-*D
32-Lead Thin Small Outline Package Type I (8x20 mm) Z32
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CY62128B
MoBL®
Document #: 38-05300 Rev. *C Page 10 of 11
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package (8x13.4 mm) ZA32
51-85094-*D
51-85089-*C
32-Lead Reverse Thin Small Outline Package ZR32
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