Cypress PSoC DESIGNER ImageCraft M8C User manual

ImageCraft Assembly Language Guide
Document # 001-44475 Rev. *B
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com
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2 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
Copyrights
Copyrights
Copyright © 2001 - 2011 Cypress Semiconductor Corporation. The information contained herein is subject to change without
notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embod-
ied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not war-
ranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to
an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical compo-
nents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the
user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of
such use and in doing so indemnifies Cypress against all charges.
PSoC Designer™, Programmable System-on-Chip™ is trademarks and PSoC® is a registered trademark of Cypress Semi-
conductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by
and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty
provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom soft-
ware and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as speci-
fied in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATE-
RIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described
herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein.
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support sys-
tems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all
charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B 3
Contents
1. Introduction 7
1.1 Chapter Overviews ......................................................................................................7
1.2 Support ........................................................................................................................8
1.2.1 Technical Support Systems..............................................................................8
1.2.2 Product Upgrades ............................................................................................8
1.3 Documentation Conventions........................................................................................8
1.4 Revision History...........................................................................................................9
2. M8C Microprocessor 11
2.1 Internal Registers.......................................................................................................11
2.2 Address Spaces.........................................................................................................12
2.3 Instruction Set Summary ...........................................................................................14
2.4 Instruction Formats ...................................................................................................16
2.4.1 One-Byte Instruction ......................................................................................16
2.4.2 Two-Byte Instructions.....................................................................................16
2.4.3 Three-Byte Instructions ..................................................................................17
2.5 Addressing Modes .....................................................................................................18
2.5.1 Source Immediate ..........................................................................................18
2.5.2 Source Direct .................................................................................................19
2.5.3 Source Indexed ..............................................................................................19
2.5.4 Destination Direct...........................................................................................20
2.5.5 Destination Indexed .......................................................................................20
2.5.6 Destination Direct Source Immediate.............................................................21
2.5.7 Destination Indexed Source Immediate .........................................................21
2.5.8 Destination Direct Source Direct ....................................................................22
2.5.9 Source Indirect Post Increment......................................................................22
2.5.10 Destination Indirect Post Increment ...............................................................23
3. ImageCraft Assembler 25
3.1 Source File Format ....................................................................................................25
3.1.1 Labels.............................................................................................................26
3.1.2 Mnemonics.....................................................................................................27
3.1.3 Operands .......................................................................................................28
3.1.4 Comments......................................................................................................29
3.1.5 Directives .......................................................................................................30
3.2 Listing File Format .....................................................................................................30
3.3 Map File Format.........................................................................................................30
3.4 ROM File Format .......................................................................................................30
3.5 Intel® HEX File Format..............................................................................................32
3.6 Convention for Restoring Internal Registers..............................................................34
3.7 Compiling a File into a Library Module ......................................................................34
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4 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
Contents
4. M8C Instruction Set 37
Add with Carry................................................................................................................... ADC 38
Add without Carry.............................................................................................................. ADD 39
Bitwise AND ...................................................................................................................... AND 40
Arithmetic Shift Left ............................................................................................................ ASL 41
Arithmetic Shift Right......................................................................................................... ASR 42
Call Function ....................................................................................................................CALL 43
Non-Destructive Compare.................................................................................................CMP 44
Complement Accumulator ..................................................................................................CPL 45
Decrement......................................................................................................................... DEC 46
Halt ...................................................................................................................................HALT 47
Increment ............................................................................................................................INC 48
Relative Table Read.......................................................................................................INDEX 49
Jump Accumulator........................................................................................................... JACC 50
Jump if Carry ........................................................................................................................ JC 51
Jump...................................................................................................................................JMP 52
Jump if No Carry ................................................................................................................JNC 53
Jump if Not Zero................................................................................................................. JNZ 54
Jump if Zero ..........................................................................................................................JZ 55
Long Call ........................................................................................................................LCALL 56
Long Jump........................................................................................................................LJMP 57
Move..................................................................................................................................MOV 58
Move Indirect, Post-Increment to Memory ......................................................................... MVI 59
No Operation ..................................................................................................................... NOP 60
Bitwise OR........................................................................................................................... OR 61
Pop Stack into Register..................................................................................................... POP 62
Push Register onto Stack................................................................................................PUSH 63
Return.................................................................................................................................RET 64
Return from Interrupt .........................................................................................................RETI 65
Rotate Left through Carry...................................................................................................RLC 66
Absolute Table Read...................................................................................................... ROMX 67
Rotate Right through Carry ............................................................................................... RRC 68
Subtract with Borrow ..........................................................................................................SBB 69
Subtract without Borrow .................................................................................................... SUB 70
Swap .............................................................................................................................. SWAP 71
System Supervisor Call ..................................................................................................... SSC 72
Test for Mask...................................................................................................................... TST 73
Bitwise XOR ...................................................................................................................... XOR 74
5. Assembler Directives 75
Area................................................................................................................................. AREA 76
5.1.1 Code Compressor and the AREA Directive................................................... 77
NULL Terminated ASCII String ...................................................................................... ASCIZ 78
RAM Block in Bytes............................................................................................................ BLK 79
RAM Block in Words .......................................................................................................BLKW 80
Define Byte...........................................................................................................................DB 81
Define Floating-point Number .............................................................................................. DF 82
Define ASCII String ..............................................................................................................DS 83
Define UNICODE String .................................................................................................... DSU 84
Define Word, Big Endian Ordering ......................................................................................DW 85
Define Word, Little Endian Ordering..................................................................................DWL 86
Equate Label ..................................................................................................................... EQU 87
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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B 5
Contents
Export .........................................................................................................................EXPORT 88
Conditional Source ........................................................................................ IF, ELSE, ENDIF 89
Include Source File....................................................................................................INCLUDE 90
Prevent Code Compression of Data ..................................................LITERAL, .ENDLITERAL 91
Macro Definition...............................................................................................MACRO, ENDM 92
Area Origin ....................................................................................................................... ORG 93
Section for Dead-Code Elimination ............................................... .SECTION, .ENDSECTION 94
Suspend/Resume Code Compressor ..........................................................OR F,0; ADD SP,0 94
6. Builds and Error Messages 97
6.1 Assemble and Build ...................................................................................................97
6.2 Linker Operations ......................................................................................................97
6.3 Code Compressor and Dead-Code Elimination Error Messages ..............................98
A. Reference Tables Appendix 99
A.1 Assembly Syntax Expressions...................................................................................99
A.2 Operand Constant Formats. ......................................................................................99
A.3 Assembler Directives Summary...............................................................................100
A.4 ASCII Code Table....................................................................................................101
A.5 Instruction Set Summary ........................................................................................102
Index 105
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6 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
Contents
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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B 7
1. Introduction
The PSoC Designer Assembly Language Guide documents the assembly language instruction set
for the M8C microcontroller as well as other compatible assembly practices. It covers the ImageCraft
Assembler.
The PSoC Designer Integrated Development Environment (IDE) software is available free of charge
and supports development in assembly language. For customers interested in developing in C,
compilers are available. Please contact your local distributor if you are interested in purchasing a C
Compiler for PSoC Designer. For more information about developing in C for the PSoC device,
please read the PSoC Designer C Language Compiler Guide available at the Cypress web site at
www.cypress.com.
1.1 Chapter Overviews
Table 1-1. Overview of the Assembly Language Guide
Chapter Description
Introduction
(on page 7)
Describes the purpose of this guide, overviews each chapter, supplies product
support and upgrade information, and lists documentation conventions.
M8C Microprocessor
(on page 11)
Discusses the microprocessor and explains address spaces, instruction format,
and destination of instruction results. It also lists all addressing modes and pro-
vides examples of each.
ImageCraft Assembler
(on page 25)
Provides assembly language source syntax including labels, mnemonics, oper-
ands, comments, and directives. Describes the various file formats created by
the ImageCraft Assembler, along with the convention for restoring internal regis-
ters and compiling a file into a library module.
M8C Instruction Set
(on page 37)
Provides a detailed list of all M8C instructions. Information about individual M8C
instructions is also available via PSoC Designer Online Help.
Assembler Directives
(on page 75) Provides a detailed list of all ImageCraft Assembler directives.
Builds and Error Messages
(on page 97)
Supplies several lists of assembler-related errors and warnings, along with their
possible solutions.
Appendix A
Reference Tables Appendix
(on page 99)
Serves as a quick reference to the M8C instruction set, and assembler directives
and syntax expressions, along with an ASCII code table.
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8 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
Introduction
1.2 Support
Free support for PSoC Designer is available online, just click on PSoC Mixed-Signal Controllers then
Technical Support. Resources include Training Seminars, Discussion Forums, Application Notes,
PSoC Consultants, TightLink Technical Support Email/Knowledge Base, and Application Support
Technicians.
Before utilizing the Cypress support services, know the version of PSoC Designer installed on your
system. To quickly determine the version, build, or service pack of your current installation of PSoC
Designer, click Help > About PSoC Designer.
Support for the ImageCraft C Compiler and Assembler is available from ImageCraft.
http://www.imagecraft.com/
1.2.1 Technical Support Systems
Enter a technical support request in this system with a guaranteed response time of four hours at
http://www.cypress.com/support/login.cfm
1.2.2 Product Upgrades
Cypress provides scheduled upgrades and version enhancements for PSoC software free of charge.
You can order upgrades from your distributor on CD-ROM or download them directly from
www.cypress.com under Software and Drivers. Critical updates to system documentation are also
available on the Cypress web site.
1.3 Documentation Conventions
The following are easily identifiable conventions used throughout this guide.
The following are acronyms used throughout this guide.
Table 1-2. Documentation Conventions
Convention Usage
Courier New Displays file locations, user entered text, and source code:
C:\ ...cd\icc\
Italics Displays file names and reference documentation:
Read about the sourcefile.hex file in the PSoC Designer Guide.
[Bracketed, Bold]Displays keyboard commands in procedures:
[Enter] or [Ctrl] [C]
File > Open Represents menu paths:
File > Open > New Project
Bold Displays commands, menu paths, and icon names in procedures:
Click the File icon and then click Open.
Text in gray boxes Presents cautions or unique functionality of the product.
Table 1-3. Acronyms
Acronym Description
A CPU_A register (accumulator)
CF carry flag
F CPU_F register (flags ZF, CF, and others)
GIE global enable interrupt
IDE integrated development environment
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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B 9
Introduction
1.4 Revision History
NOP no operation
PC CPU_PC register (program counter)
POR power-on-reset
RAM random access memory
REG register space
ROM read only memory
SP CPU_SP register (stack pointer)
SROM supervisory read only memory
SSC supervisory system call
WDR watchdog timer reset
X CPU_X register (index)
XRES external reset
ZF zero flag
Table 1-4. Revision History
Revision
PDF
Creation
Date
Origin
of
Change
Description of Change
** May 20, 2008 FSU Put the original ImageCraft Assembly Guide in a new template and assigned a Spec Num-
ber.
*A Sept 11, 2008 OGNE/
PYRS Made changes in the Assembly instructions chapter, page 72.
*B June 06, 2011 RAVG Made changes in the Assembly Assembler Introduction. And added Note under section
3.1.1 - Labels
Table 1-3. Acronyms
Acronym Description
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10 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
Introduction
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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B 11
2. M8C Microprocessor
This chapter covers internal M8C registers, address spaces, instruction summary and formats, and
addressing modes for the M8C microprocessor. The M8C is a 4 MIPS 8-bit Harvard architecture
microprocessor. Code selectable processor clock speeds from 93.7 kHz to 24 MHz allow the M8C to
be tuned to a particular application’s performance and power requirements. The M8C supports a rich
instruction set which allows for efficient low-level language support. For a detailed description of all
M8C instructions, refer to the M8C Instruction Set chapter on page 37.
2.1 Internal Registers
The M8C has five internal registers that are used in program execution:
■Accumulator (A)
■Index (X)
■Program Counter (PC)
■Stack Pointer (SP)
■Flags (F)
All of the internal M8C registers are 8 bits in width, except for the PC (CPU_PC register) which is 16
bits wide. Upon reset, A, X, PC, and SP are reset to 0x00. The Flag register CPU_F (F) is reset to
0x02 indicating that the Zflag is set.
With each stack operation, the SP is automatically incremented or decremented so that it always
points at the next stack byte in Random Access Memory (RAM). If the last byte in the stack is at
address 0xFF in RAM, the Stack Pointer (CPU_SP or SP) will wrap to RAM address 0x00. It is the
firmware developer’s responsibility to ensure that the stack does not overlap with user-defined vari-
ables in RAM.
As shown in Table 2- 1, the Flag register has 6 of 8 bits defined. The PgMode and XIO bits are used
to control the active register and RAM address spaces in the PSoC device. The C and Z bits are the
Carry and Zero flags respectively. These flags are affected by arithmetic, logical, and shift operations
provided in the M8C instruction. The GIE bit is the Global Interrupt Enable. When set, this bit allows
the M8C to be interrupted by the PSoC device’s interrupt controller.
Table 2-1. M8C Internal Flag (F) Register (CPU_F)
Bits 7 6 5 4 3 2 1 0
Name PgMode[1:0] XIO C Z GIE
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12 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
M8C Microprocessor
With the exception of the CPU_F register, the M8C internal registers are not accessible via an
explicit register address. PSoC parts in the CY8C25xxx and CY8C26xxx device family do not have a
readable CPU_F register. The OR F, expr and AND F, expr instructions must be used to set and
clear CPU_F register bits. The internal M8C registers are accessed using special instructions such
as:
■MOV A, expr
■MOV X, expr
■SWAP A, SP
■OR F, expr
■JMP
The CPU_F register may be read by using address 0xF7 in any register bank, except in CY8C25xxx
and CY8C26xxx devices.
2.2 Address Spaces
The M8C microcontroller has three address spaces: ROM, RAM, and registers. The Read Only
Memory (ROM) address space is accessed via its own address and data bus. Figure 2-1 illustrates
the arrangement of the PSoC device address spaces.
The ROM address space is composed of the Supervisory ROM and the on-chip Flash program
store. Flash is organized into 64-byte blocks. The user need not be concerned with program store
page boundaries, because the M8C automatically increments the 16-bit CPU_PC register (PC) on
every instruction making the block boundaries invisible to user code. Instructions occurring on a 256-
byte Flash page boundary (with the exception of jump instructions) incur an extra M8C clock cycle
because the upper byte of the Program Counter (PC) is incremented.
The register address space is used to configure the PSoC device’s programmable blocks. It consists
of two banks of 256 bytes each. To switch between banks, the XIO bit in the Flag register is set or
cleared (set for Bank1 = Configuration Space, cleared for Bank0 = User Space). The common con-
vention is to leave the bank set to Bank0 (XIO cleared), switch to Bank1 as needed (set XIO), then
switch back to Bank0.
RAM is broken into 256-byte pages. For PSoC devices with 256 bytes of RAM or less, the program
stack is stored in RAM Page 0. For PSoC devices with 512 bytes of RAM or more, the stack is con-
strained to the last RAM page. For information on RAM configuration in a specific device, refer to the
device-specific data sheet.
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ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B 13
M8C Microprocessor
Figure 2-1. M8C Microcontroller Address Spaces
Registers RAM ROM
Bank 0
256 Bytes
Bank 1
256 Bytes
Page 0
256 Bytes SROM
Flash
M x 64
Byte Blocks
LEGEND
M: Total number of Flash bocks in device
n: Total number of RAM pages minus 1
in device
XIO: Register bank selection
IOR: Register read
IOW: Register write
MR: Memory read
MW: Memory write
MW MRIOW IOR XIO DB[7:0]
DA[7:0]
ID[7:0] PC[15:0]
M8C
A
F
SP
PC
X
PAGE
Page 1
256 Bytes
Page n
256 Bytes
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14 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B
M8C Microprocessor
2.3 Instruction Set Summary
The instruction set is summarized in both Tab le 2- 2 and Table 2-3 (in numeric and mnemonic order,
respectively), and serves as a quick reference.
Table 2-2. Instruction Set Summary Sorted Numerically by Opcode
Opcode Hex
Cycles
Bytes
Instruction For-
mat Flags
Opcode Hex
Cycles
Bytes
Instruction Format Flags
Opcode Hex
Cycles
Bytes
Instruction Format Flags
00 15 1SSC 2D 8 2 OR [X+expr], A Z5A 5 2 MOV [expr], X
01 4 2 ADD A, expr C, Z 2E 9 3 OR [expr], expr Z5B 4 1 MOV A, X Z
02 6 2 ADD A, [expr] C, Z 2F 10 3OR [X+expr], expr Z5C 4 1 MOV X, A
03 7 2 ADD A, [X+expr] C, Z 30 9 1HALT 5D 6 2 MOV A, reg[expr] Z
04 7 2 ADD [expr], A C, Z 31 4 2 XOR A, expr Z5E 7 2 MOV A, reg[X+expr] Z
05 8 2 ADD [X+expr], A C, Z 32 6 2 XOR A, [expr] Z5F 10 3MOV [expr], [expr]
06 9 3 ADD [expr], expr C, Z 33 7 2 XOR A, [X+expr] Z60 5 2 MOV reg[expr], A
07 10 3ADD [X+expr], expr C, Z 34 7 2 XOR [expr], A Z61 6 2 MOV reg[X+expr], A
08 4 1PUSH A 35 8 2 XOR [X+expr], A Z62 8 3 MOV reg[expr], expr
09 4 2 ADC A, expr C, Z 36 9 3 XOR [expr], expr Z63 9 3 MOV reg[X+expr], expr
0A 6 2 ADC A, [expr] C, Z 37 10 3XOR [X+expr], expr Z64 4 1ASL A C, Z
0B 7 2 ADC A, [X+expr] C, Z 38 5 2ADD SP, expr 65 7 2ASL [expr] C, Z
0C 7 2 ADC [expr], A C, Z 39 5 2CMP A, expr
if (A=B) Z=1
if (A<B) C=1
66 8 2ASL [X+expr] C, Z
0D 8 2 ADC [X+expr], A C, Z 3A 7 2CMP A, [expr] 67 4 1ASR A C, Z
0E 9 3 ADC [expr], expr C, Z 3B 8 2CMP A, [X+expr] 68 7 2ASR [expr] C, Z
0F 10 3ADC [X+expr], expr C, Z 3C 8 3CMP [expr], expr 69 8 2ASR [X+expr] C, Z
10 4 1PUSH X 3D 9 3CMP [X+expr], expr 6A 4 1RLC A C, Z
11 4 2SUB A, expr C, Z 3E 10 2MVI A, [ [expr]++ ] Z6B 7 2RLC [expr] C, Z
12 6 2SUB A, [expr] C, Z 3F 10 2MVI [ [expr]++ ], A 6C 8 2RLC [X+expr] C, Z
13 7 2SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1RRC A C, Z
14 7 2SUB [expr], A C, Z 41 9 3AND reg[expr], expr Z6E 7 2RRC [expr] C, Z
15 8 2SUB [X+expr], A C, Z 42 10 3AND reg[X+expr], expr Z6F 8 2RRC [X+expr] C, Z
16 9 3SUB [expr], expr C, Z 43 9 3 OR reg[expr], expr Z70 4 2AND F, expr C, Z
17 10 3SUB [X+expr], expr C, Z 44 10 3OR reg[X+expr], expr Z71 4 2 OR F, expr C, Z
18 5 1POP A Z45 9 3XOR reg[expr], expr Z72 4 2XOR F, expr C, Z
19 4 2SBB A, expr C, Z 46 10 3XOR reg[X+expr], expr Z73 4 1CPL A Z
1A 6 2SBB A, [expr] C, Z 47 8 3TST [expr], expr Z74 4 1INC A C, Z
1B 7 2SBB A, [X+expr] C, Z 48 9 3TST [X+expr], expr Z75 4 1INC X C, Z
1C 7 2SBB [expr], A C, Z 49 9 3TST reg[expr], expr Z76 7 2INC [expr] C, Z
1D 8 2SBB [X+expr], A C, Z 4A 10 3TST reg[X+expr], expr Z77 8 2INC [X+expr] C, Z
1E 9 3SBB [expr], expr C, Z 4B 5 1SWAP A, X Z78 4 1DEC A C, Z
1F 10 3SBB [X+expr], expr C, Z 4C 7 2SWAP A, [expr] Z79 4 1DEC X C, Z
20 5 1POP X 4D 7 2SWAP X, [expr] 7A 7 2DEC [expr] C, Z
21 4 2AND A, expr Z4E 5 1SWAP A, SP Z7B 8 2DEC [X+expr] C, Z
22 6 2AND A, [expr] Z4F 4 1 MOV X, SP 7C 13 3LCALL
23 7 2AND A, [X+expr] Z50 4 2 MOV A, expr Z7D 7 3 LJMP
24 7 2AND [expr], A Z51 5 2 MOV A, [expr] Z7E 10 1RETI C, Z
25 8 2AND [X+expr], A Z52 6 2 MOV A, [X+expr] Z7F 8 1RET
26 9 3AND [expr], expr Z53 5 2 MOV [expr], A 8x 5 2JMP
27 10 3AND [X+expr], expr Z54 6 2 MOV [X+expr], A 9x 11 2CALL
28 11 1ROMX Z55 8 3 MOV [expr], expr Ax 5 2 JZ
29 4 2 OR A, expr Z56 9 3 MOV [X+expr], expr Bx 5 2 JNZ
2A 6 2 OR A, [expr] Z57 4 2 MOV X, expr Cx 5 2 JC
2B 7 2 OR A, [X+expr] Z58 6 2 MOV X, [expr] Dx 5 2 JNC
2C 7 2 OR [expr], A Z59 7 2 MOV X, [X+expr] Ex 7 2 JACC
Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. Fx 13 2INDEX Z
Note 2 The number of cycles required by an instruction is increased by one for instructions that
span 256 byte page boundaries in the Flash memory space.
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M8C Microprocessor
Table 2-3. Instruction Set Summary Sorted Alphabetically by Mnemonic
Opcode Hex
Cycles
Bytes
Instruction Format Flags
Opcode Hex
Cycles
Bytes
Instruction Format Flags
Opcode Hex
Cycles
Bytes
Instruction Format Flags
09 4 2 ADC A, expr C, Z 76 7 2INC [expr] C, Z 20 5 1POP X
0A 6 2 ADC A, [expr] C, Z 77 8 2INC [X+expr] C, Z 18 5 1POP A Z
0B 7 2 ADC A, [X+expr] C, Z Fx 13 2INDEX Z10 4 1PUSH X
0C 7 2 ADC [expr], A C, Z Ex 7 2 JACC 08 4 1PUSH A
0D 8 2 ADC [X+expr], A C, Z Cx 5 2 JC 7E 10 1RETI C, Z
0E 9 3 ADC [expr], expr C, Z 8x 5 2JMP 7F 8 1RET
0F 10 3ADC [X+expr], expr C, Z Dx 5 2 JNC 6A 4 1RLC A C, Z
01 4 2 ADD A, expr C, Z Bx 5 2 JNZ 6B 7 2RLC [expr] C, Z
02 6 2 ADD A, [expr] C, Z Ax 5 2 JZ 6C 8 2RLC [X+expr] C, Z
03 7 2 ADD A, [X+expr] C, Z 7C 13 3LCALL 28 11 1ROMX Z
04 7 2 ADD [expr], A C, Z 7D 7 3 LJMP 6D 4 1RRC A C, Z
05 8 2 ADD [X+expr], A C, Z 4F 4 1 MOV X, SP 6E 7 2RRC [expr] C, Z
06 9 3 ADD [expr], expr C, Z 50 4 2 MOV A, expr Z6F 8 2RRC [X+expr] C, Z
07 10 3ADD [X+expr], expr C, Z 51 5 2 MOV A, [expr] Z19 4 2SBB A, expr C, Z
38 5 2ADD SP, expr 52 6 2 MOV A, [X+expr] Z1A 6 2SBB A, [expr] C, Z
21 4 2AND A, expr Z53 5 2 MOV [expr], A 1B 7 2SBB A, [X+expr] C, Z
22 6 2AND A, [expr] Z54 6 2 MOV [X+expr], A 1C 7 2SBB [expr], A C, Z
23 7 2AND A, [X+expr] Z55 8 3MOV [expr], expr 1D 8 2SBB [X+expr], A C, Z
24 7 2AND [expr], A Z56 9 3MOV [X+expr], expr 1E 9 3SBB [expr], expr C, Z
25 8 2AND [X+expr], A Z57 4 2MOV X, expr 1F 10 3SBB [X+expr], expr C, Z
26 9 3AND [expr], expr Z58 6 2MOV X, [expr] 00 15 1SSC
27 10 3AND [X+expr], expr Z59 7 2MOV X, [X+expr] 11 4 2SUB A, expr C, Z
70 4 2AND F, expr C, Z 5A 5 2MOV [expr], X 12 6 2SUB A, [expr] C, Z
41 9 3AND reg[expr], expr Z5B 4 1MOV A, X Z13 7 2SUB A, [X+expr] C, Z
42 10 3AND reg[X+expr], expr Z5C 4 1MOV X, A 14 7 2SUB [expr], A C, Z
64 4 1ASL A C, Z 5D 6 2MOV A, reg[expr] Z15 8 2SUB [X+expr], A C, Z
65 7 2ASL [expr] C, Z 5E 7 2MOV A, reg[X+expr] Z16 9 3SUB [expr], expr C, Z
66 8 2ASL [X+expr] C, Z 5F 10 3MOV [expr], [expr] 17 10 3SUB [X+expr], expr C, Z
67 4 1ASR A C, Z 60 5 2MOV reg[expr], A 4B 5 1SWAP A, X Z
68 7 2ASR [expr] C, Z 61 6 2MOV reg[X+expr], A 4C 7 2SWAP A, [expr] Z
69 8 2ASR [X+expr] C, Z 62 8 3MOV reg[expr], expr 4D 7 2SWAP X, [expr]
9x 11 2CALL 63 9 3MOV reg[X+expr], expr 4E 5 1SWAP A, SP Z
39 5 2CMP A, expr
if (A=B)
Z=1
if (A<B)
C=1
3E 10 2MVI A, [ [expr]++ ] Z47 8 3TST [expr], expr Z
3A 7 2CMP A, [expr] 3F 10 2MVI [ [expr]++ ], A 48 9 3TST [X+expr], expr Z
3B 8 2CMP A, [X+expr] 40 4 1 NOP 49 9 3TST reg[expr], expr Z
3C 8 3CMP [expr], expr 29 4 2OR A, expr Z4A 10 3TST reg[X+expr], expr Z
3D 9 3CMP [X+expr], expr 2A 6 2OR A, [expr] Z72 4 2XOR F, expr C, Z
73 4 1CPL A Z2B 7 2OR A, [X+expr] Z31 4 2XOR A, expr Z
78 4 1DEC A C, Z 2C 7 2 OR [expr], A Z32 6 2XOR A, [expr] Z
79 4 1DEC X C, Z 2D 8 2 OR [X+expr], A Z33 7 2XOR A, [X+expr] Z
7A 7 2DEC [expr] C, Z 2E 9 3 OR [expr], expr Z34 7 2XOR [expr], A Z
7B 8 2DEC [X+expr] C, Z 2F 10 3OR [X+expr], expr Z35 8 2XOR [X+expr], A Z
30 9 1HALT 43 9 3OR reg[expr], expr Z36 9 3XOR [expr], expr Z
74 4 1INC A C, Z 44 10 3OR reg[X+expr], expr Z37 10 3XOR [X+expr], expr Z
75 4 1INC X C, Z 71 4 2OR F, expr C, Z 45 9 3XOR reg[expr], expr Z
Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles. 46 10 3XOR reg[X+expr], expr Z
Note 2 The number of cycles required by an instruction is increased by one for instructions
that span 256 byte page boundaries in the Flash memory space.
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M8C Microprocessor
2.4 Instruction Formats
The M8C has a total of seven instruction formats which use instruction lengths of one, two, and three
bytes. All instruction bytes are fetched from the program memory (Flash), using an address and data
bus that are independent from the address and data buses used for register and RAM access.
While examples of instructions are given in this section, refer to the M8C Instruction Set chapter on
page 37 for detailed information on individual instructions.
2.4.1 One-Byte Instruction
Many instructions, such as some of the MOV instructions, have single-byte forms, because they do
not use an address or data as an operand. As shown in Table 2- 4, one-byte instructions use an 8-bit
opcode. The set of one-byte instructions can be divided into four categories, according to where their
results are stored.
The first category of one-byte instructions are those that do not update any registers or RAM. Only
the one-byte no operation (NOP) and supervisory system call (SSC) instructions fit this category.
While the program counter is incremented as these instructions execute, they do not cause any
other internal M8C registers to be updated, nor do these instructions directly affect the register
space or the RAM address space. The SSC instruction will cause SROM code to run, which will
modify RAM and the M8C internal registers.
The second category has only the two PUSH instructions in it. The PUSH instructions are unique,
because they are the only one-byte instructions that cause a RAM address to be modified. These
instructions automatically increment the CPU_SP register (SP).
The third category has only the HALT instruction in it. The HALT instruction is unique, because it is
the only one-byte instruction that causes a user register to be modified. The HALT instruction modi-
fies user register space address FFh (CPU_SCR register).
The final category for one-byte instructions are those that cause updates of the internal M8C regis-
ters. This category holds the largest number of instructions: ASL, ASR, CPL, DEC, INC, MOV, POP,
RET, RETI, RLC, ROMX, RRC, SWAP. These instructions can cause the CPU_A, CPU_X, and CPU_SP
registers, or SRAM to update.
2.4.2 Two-Byte Instructions
The majority of M8C instructions are two bytes in length. While these instructions can be divided into
categories identical to the one-byte instructions, this would not provide a useful distinction between
the three two-byte instruction formats that the M8C uses.
Table 2-4. One-Byte Instruction Format
Byte 0
8-Bit Opcode
Table 2-5. Two-Byte Instruction Formats
Byte 0 Byte 1
4-Bit
Opcode 12-Bit Relative Address
8-Bit Opcode 8-Bit Data
8-Bit Opcode 8-Bit Address
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M8C Microprocessor
The first two-byte instruction format, shown in the first row of Table 2 -5,is used by short jumps and
calls: CALL, JMP, JACC, INDEX, JC, JNC, JNZ, JZ. This instruction format uses only four bits for the
instruction opcode, leaving 12 bits to store the relative destination address in a two’s-complement
form. These instructions can change program execution to an address relative to the current
address by -2048 or +2047.
The second two-byte instruction format, shown in the second row of Table 2-5,is used by instruc-
tions that employ the Source Immediate addressing mode (see “Source Immediate” on page 18).
The destination for these instructions is an internal M8C register, while the source is a constant
value. An example of this type of instruction would be ADD A, 7.
The third two-byte instruction format, shown in the third row of Table 2-5,is used by a wide range of
instructions and addressing modes. The following is a list of the addressing modes that use this third
two-byte instruction format:
■Source Direct (ADD A, [7])
■Source Indexed (ADD A, [X+7])
■Destination Direct (ADD [7], A)
■Destination Indexed (ADD [X+7], A)
■Source Indirect Post Increment (MVI A, [7])
■Destination Indirect Post Increment (MVI [7], A)
For more information on addressing modes see “Addressing Modes” on page 18.
2.4.3 Three-Byte Instructions
The three-byte instruction formats are the second most prevalent instruction formats. These instruc-
tions need three bytes because they either move data between two addresses in the user-accessible
address space (registers and RAM) or they hold 16-bit absolute addresses as the destination of a
long jump or long call.
The first instruction format, shown in the first row of Tab le 2- 6 ,is used by the LJMP and LCALL
instructions. These instructions change program execution unconditionally to an absolute address.
The instructions use an 8-bit opcode, leaving room for a 16-bit destination address.
The second three-byte instruction format, shown in the second row of Ta bl e 2 -6 ,is used by the fol-
lowing two addressing modes:
■Destination Direct Source Immediate (ADD [7], 5)
■Destination Indexed Source Immediate (ADD [X+7], 5)
The third three-byte instruction format, shown in the third row of Table 2- 6,is for the Destination
Direct Source Direct addressing mode, which is used by only one instruction. This instruction format
uses an 8-bit opcode followed by two 8-bit addresses. The first address is the destination address in
RAM, while the second address is the source address in RAM. The following is an example of this
instruction:
MOV [7], [5]
Table 2-6. Three-Byte Instruction Formats
Byte 0 Byte 1 Byte 2
8-Bit Opcode 16-Bit Address (MSB, LSB)
8-Bit Opcode 8-Bit Address 8-Bit Data
8-Bit Opcode 8-Bit Address 8-Bit Address
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M8C Microprocessor
2.5 Addressing Modes
The M8C has ten addressing modes:
■“Source Immediate” on page 18.
■“Source Direct” on page 19.
■“Source Indexed” on page 19.
■“Destination Direct” on page 20.
■“Destination Indexed” on page 20.
■“Destination Direct Source Immediate” on page 21.
■“Destination Indexed Source Immediate” on page 21.
■“Destination Direct Source Direct” on page 22.
■“Source Indirect Post Increment” on page 22.
■“Destination Indirect Post Increment” on page 23.
2.5.1 Source Immediate
For these instructions, the source value is stored in operand 1 of the instruction. The result of these
instructions is placed in either the M8C CPU_A, CPU_F, or CPU_X register as indicated by the
instruction’s opcode. All instructions using the Source Immediate addressing mode are two bytes in
length.
Source Immediate Examples:
Table 2-7. Source Immediate
Opcode Operand 1
Instruction Immediate Value
Source Code Machine Code Comments
ADD A, 7 01 07 The immediate value 7 is added to the Accumulator.
The result is placed in the Accumulator.
MOV X, 8 57 08 The immediate value 8 is moved into the CPU_X
register.
AND F, 9 70 09 The immediate value of 9 is logically AND’ed with
the CPU_F register and the result is placed in the
CPU_F register.
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M8C Microprocessor
2.5.2 Source Direct
For these instructions, the source address is stored in operand 1 of the instruction. During instruction
execution, the address will be used to retrieve the source value from RAM or register address space.
The result of these instructions is placed in either the M8C CPU_A or CPU_X register as indicated
by the instruction’s opcode. All instructions using the Source Direct addressing mode are two bytes
in length.
Source Direct Examples:
2.5.3 Source Indexed
For these instructions, the source offset from the CPU_X register is stored in operand 1 of the
instruction. During instruction execution, the current CPU_X register value is added to the signed off-
set, to determine the address of the source value in RAM or register address space. The result of
these instructions is placed in either the M8C CPU_A or CPU_X register as indicated by the instruc-
tion’s opcode. All instructions using the Source Indexed addressing mode are two bytes in length.
Source Indexed Examples:
Table 2-8. Source Direct
Opcode Operand 1
Instruction Source Address
Source Code Machine Code Comments
ADD A, [7] 02 07 The value in memory at address 7 is added to the
Accumulator and the result is placed into the Accu-
mulator.
MOV A, REG[8] 5D 08 The value in the register space at address 8 is
moved into the Accumulator.
Table 2-9. Source Indexed
Opcode Operand 1
Instruction Source Index
Source Code Machine Code Comments
ADD A, [X+7] 03 07 The value in memory at address X+7 is added to the
Accumulator. The result is placed in the Accumula-
tor.
MOV X, [X+8] 59 08 The value in RAM at address X+8 is moved into the
CPU_X register.
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M8C Microprocessor
2.5.4 Destination Direct
For these instructions, the destination address is stored in the machine code of the instruction. The
source for the operation is either the M8C CPU_A or CPU_X register as indicated by the instruction’s
opcode. All instructions using the Destination Direct addressing mode are two bytes in length.
Destination Direct Examples:
2.5.5 Destination Indexed
For these instructions, the destination offset from the CPU_X register is stored in the machine code
for the instruction. The source for the operation is either the M8C CPU_A register or an immediate
value as indicated by the instruction’s opcode. All instructions using the Destination Indexed
addressing mode are two bytes in length.
Destination Indexed Example:
Table 2-10. Destination Direct
Opcode Operand 1
Instruction Destination Address
Source Code Machine Code Comments
ADD [7], A 04 07 The value in the Accumulator is added to memory at
address 7. The result is placed in memory at
address 7. The Accumulator is unchanged.
MOV REG[8], A 60 08 The Accumulator value is moved to register space at
address 8. The Accumulator is unchanged.
Table 2-11. Destination Indexed
Opcode Operand 1
Instruction Destination Index
Source Code Machine Code Comments
ADD [X+7], A 05 07 The value in memory at address X+7 is added to the
Accumulator. The result is placed in memory at
address X+7. The Accumulator is unchanged.
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